JPS58108587A - Frequency controller for electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a frequency control device for a W child musical instrument.

Is there a music synthesizer as one of the electronic musical instruments?
This type of electronic musical instrument is based on vaguely analog circuits.
1 There aren't any.

However, 19 different studies have been conducted on methods for digitally obtaining musical sound waveforms in II-child organs, etc.
t,, -I think it's Amano who has been used for SW. However, one way to obtain such a musical sound waveform is to use
There is an address counter that cumulatively adds a fixed value, and the output of the cough address counter specifies the RL) Mtl address.In this way, the waveform is read out from the ROM and performs frequency modulation, vibrato, etc. In this method, the waveform data (ie, one frequency data) is multiplied by a vibrato waveform that is vertically symmetrical with respect to the reference level. For this reason, the depth of frequency modulation differs between the plus side and the minus side and is not equal, resulting in an unnatural vibrato. for example.

With this method, the standard frequency is 440H! I am trying to apply a vertically symmetrical vibrato waveform as described above.

Therefore, when the positive side VC changes by 200 cents from 440Hz, the frequency is 493°5Hz (+=g4i
o + 53.9) Hz, and when multiplied by the above 440 Hz, which is a vertically symmetrical vibrato waveform, the negative side becomes (440-53,9-)386, 1 Hz.Therefore, the change in pitch is 226 cents. It becomes.

Also, with this method, the frequency data is changed to twice the original frequency data on the plus side, that is, one octave higher.
When *v* digit, the negative side cancels out and the frequency becomes O
It becomes K. The drawback is that modulation of more than ±1 octave cannot be applied with this method? %be.

1! In this method, if we want to construct the same deep-pitched vipla across the diatonic scale, we will need the data (
vibrato waveform) or scale.

Another drawback is that frequency control becomes extremely complex.

This invention was made under the above-mentioned circumstances.

Its purpose is to generate sound f through arithmetic processing using digital circuits. l! For example, when performing frequency modulation using the same wave number, the frequency can be changed equally on the plus side and minus side by simple arithmetic processing.

Moreover, it is an object of the present invention to provide a frequency control device for an electronic musical instrument that can easily perform frequency modulation of a semitone or more.

An embodiment in which a ξ music synthesizer is applied to the present invention 1 will be described below with reference to one drawing. FIG. 1 shows a system configuration diagram of a musical synthesizer according to the above embodiment. In the figure, dP-board IK has multiple media.
is provided, and each key outputs key operation notes. The switch section 2 has a rectangular wave and a PWM wave (asymmetric square wave).
, -Various sound source waveforms such as leprosy waves (fundamental wave > yh: switch to select, average rate frequency calculation section 4, digital filter 6, envelope generator γ, etc. to be described later), and various switches are provided. It is being

The respective outputs from the keyboard 1 and the switch unit 2 are both supplied to a CPU (central processing unit) 3.

The CPU 3 is a device for controlling all operations of this Zj-thick synthesizer, and is composed of a microprocessor, etc., but the details thereof will be omitted.

The average rate frequency calculating section 4 is a circuit that always calculates frequency data # and gv according to the average rate from the scale frequency code I''1 frequency modulation code a' given from epus, regardless of frequency modulation.

Unibu generator S [, above data β, - and e)
``U: Data r supplied from a, KK Motobu color This is a circuit that creates the above sound source waveform t by digital calculation.1 The created waveform data is supplied to the digital filter 6.The digital filter 6 is C1'US. III from
Based on the llIll signal, a part of the overtone component in the waveform data is decoded and its output is supplied to the envelope generator 7. Also, the envelope a-puji generator rHcP
A control digital/analog converter 8 is supplied from Us. The digital/analog converter 8 is a circuit that converts the input digital musical tone signal into an analog musical tone signal.This analog musical tone signal is sent to an amplifier connected to the output side of the digital/analog converter 8. 9. Speaker 1
04 and is emitted as a musical tone.

Note that this digital filter 8KH%l[1IH8B
No.-531711 [Digital filter device] 1. For the envelope generator 7, Japanese Patent Application No. 56-74244 entitled "Envelope Control Method for Electronic Musical Instruments" can be applied.

Next, the specific configuration of the Unibu generator S will be explained with reference to FIG. 2Y. A input terminal A1s to A of full adder 15
The 16-bit data output from the shift register 17 and circulated is applied to s. In addition, 16-bit data a (a
IINg・) is applied. And a high level signal is applied to the terminal C1n! H" is always applied. Therefore, the full adder 15 subtracts the input data aIv to the B input terminal from the input data at the A input terminal, and outputs the result from the data v8 output terminal SSS~8. A input terminal of the full adder 16 that comes into contact with A ts NA
・Mark mfru. B input terminal aSS of this full adder 16~
B@ contains the scale frequency code β (in the case of creating a rectangular wave or sawtooth wave) output from the gate circuit G1 or the data p±(β-K)r (P
In the case of WM wave creation), respectively, Antogame) 1 g I
Preset via I~18/Y. Note that the carry output output from the terminal Gout' of the full adder 15 is applied to each control input terminal of the Ant 0 gates 1811 to 18. via the inverter 19t'.

The result data of full adder 16 is S output terminal f3@@distribution S.
It is output from the full adder 16 (ff output side VC and connected to the above shift register 17!).In the drum, this music synthesizer is now a polyphonic synthesizer with 8 notes (fll, t).

The shift register 17 consists of a 16-bit capacity shift register ftB with a cascade connection. The circuit shown in FIG. 2 executes time-sharing processing operations under the control of the CPU 3.

Of the output data of the shift register 17, the data of the lower 9 pits is applied to the exclusive O'7 data) 20 to 20. Furthermore, each of the 10- to 15-bit data of the output data is transmitted through inverters 21-1 to 21-6, respectively. It is applied to each of the control input terminals 2-1 to 22-6. q! , the upper bit data of the above output data is passed through the inverter 21-7. It is applied to the other input terminal of 2-6. AND GATE 22-1~22-
6 [As shown in the figure, they are connected in series, so the output of the AND gate 22-6 is the source of the voltage applied to the other input terminal of the AND gate 22-6;
Each outcome of 22-2 is shown in each ant game in the latter stage) 2g-4 to 2
2-1 is applied to each other incoming end. The output of the AND gate 22-1 is applied to the exclusive OR days) 20- to 20@.

The output of 20.~2o. (exclusive or day) is applied as the head address data of RUM (leat "only memory) 23 fiA.~A.The ROM 23 is the 38th!J
It stores 174 waveforms of sine wave data Y shown in FIG. This waveform data is used to interpolate points where the amplitude level of the rectangular wave generated by the Unibu generator S suddenly changes.

The 7-bit waveform data read from output terminals 0.about.Oo of R(JM23) is applied to OR gates 24.about.24.

ORGATE 246~S14# also has ant 0 game) 2
The output of 2-z is applied via an inverter 25 and a transformer 7 argate 26v. And or day 1f!
The output of 4@-v24 is an exclusive OR gate 27-~2γ
0 to each end. Exclusive or Day)! 74N2
The outputs of the other terminals Kd, 22-1 of 7 and 7 are applied through the input 5+-I 28 and the transfer gate 29v.

The outputs of the exclusive OR gates 27e to 27. are as follows.

A input fiA of the full adder 30 that constitutes an inverting circuit
-f- applied to ~A. t rs full adder 30 (
The output of the AND gate 22-1 is connected to the nA input terminal Ay of the inverter 28. Transfer Gate S! ll.

47/<-$3111 mark 71 is entered. Furthermore, the input Cin vc of the full adder 30 is also an AND gate S! 2
-1 output is inverter! 8. ) Lance Fagate 29
In addition, the output of a polarity inverting circuit 32, which will be described later, is applied via a transfer voltage of -33v. The data output from the output terminals 8 to S of the full adder 30 is transferred to the transfer gate 34! .about.34 is sent to the digital filter 6.・In addition, the above transfer game) 26 is a square wave and P
When a switch designated for each WM wave is operated, a control signal output from the vcePUs is applied to the gate to control opening and closing. In addition, when the switch for specifying the sawtooth wave is operated, the transfer gate 29.8B applies i[11%i%i to the control a**V output from cc)'US, and applies this to the transfer gate 33 via the inverter 36v. , controlled opening and closing.

Furthermore, the transfer gates 34ma to 34e are the outputs of the AND gate 22-2. Inverter 2! s.

Transfutigate 35. Inverter 87! The voltage applied to each via gate is controlled to open and close.

The subtraction circuit 41 receives scale frequency code)/and data K(
constant values) are applied respectively. And the result day 1fi
- is applied to the multiplication circuit 42 and the division circuit 44, respectively. Multiplication circuit 42 Ktftk data r data r
If the value of the frame 0≦r≦1, 9° (which is data that determines the duty ratio) is applied as an application source, and the resultant data (β-K)r is applied to the addition/subtraction circuit 43 ζ4. The scale frequency code p is applied to the other end of the addition/subtraction circuit 43, and the output of the polarity inverting circuit 32 is applied to the control input terminal ty.

Then, the result data I±(#r−K)r of the addition/subtraction circuit 32
is applied to the gate circuit Gg. In addition, the gauge circuit Gs
is controlled to open and close by the 1111111 signal outputted by KcPtys when the switch that specifies the rectangular wave and the sawtooth wave ν is operated, and the gate circuit @Gm is controlled by the control # signal that is output when the switch that specifies the PWM wave is operated. The opening/closing side is @.

Output data M and data K of the shift register 17 are input to the subtraction circuit 45 . And the fruit data M-K
H voltage is applied to the irises removal circuit 44vc. The resultant data CM-K)/(#-K) of the division circuit 44 is sent to the digital filter 6 as tooth wave data via seven transformers and gates 46i to 46. Each gate of transfer gate 46mer 46 has an ant game) 22-1
! The output of is inverter 2! I,) Lance 7 Argate 3
S.

Invar l 37 *, 4? It is applied via V and is opened and closed.

The polarity inversion circuit 32 includes a shift register 48 and an exclusive OR gate 49 connected to the output i1m of the shift register 48. The other input terminal of the exclusive OR gate 49 is the output terminal C' of the full adder 11S.
The output from is applied via the inverter 5°Y. Further, the output of the exclusive OR gate 49 is fed back to the hexagonal sides of the shift register 48.

In the case of the above-mentioned 8-tone polyphonic synthesizer, the shift register 48 is a shift register v with a capacity of 1 bit.
It consists of 8 stages connected in cascade. Further, the output terminal C' of the full adder 115 is connected to the full adder 1! Fl@Ka day 1
r 512 J Kfk Outputs a ``H'' level signal (dP carry).

Next is the 7th r! Various embodiments of the average rate frequency operation xWh4 will be explained with reference to ItJ to @1B diagrams. First, FIG. 7 is a circuit diagram of the first embodiment. In fig.

Scale frequency code β'1 Frequency scale code a' are both N
Consists of bits. And the pitch (pitch) of lower n bits is less than a semitone! Specify the upper 4 bits of Note v, and then specify the higher rank of violation (N-n-4
) bit specifies the octave.

The data specifying the above 4-bit note is expressed in hexadecimal code, and the value of f is expressed in binary code as I!
be revealed.

Scale frequency code lj I, local wave convergence 11: I-Do'
The (N-n-4) bit data specifying each octave Y are applied to the binary adder/subtractor 61.

! ! The 4-bit data to be read are both marked by the hexadecimal adder/subtractor 62jfC, and 1! The lower n bits of data specifying the pitch of a semitone or less are sent to the binary adder/subtractor 63.
is applied to Also, binary cool subtractor 61.12 decimal addition f
IR calculation■62. Simultaneous vccP for binary adjuster 63
An addition/subtraction command (-) from Us is applied, and in response to this, each adder/subtractor 61 to 63 performs an addition or subtraction operation on its input data. Then, the carry output of the binary adder/subtracter '1i 63 is output from the terminal C and is sent to the decimal output r subtracter 6z.
Terminal Gin K is applied. Also, the hexadecimal adder/subtractor 62
The carry output of is outputted from terminal C and applied to terminal Cin yC of binary adder/subtractor 61. Each result data of the binary adder/subtractor 61 and the 124 adder/subtractor 6 is applied to the ROM 615 as address data tL.

On the other hand, the result data of the binary adder/subtractor 63 is stored in the ROM 65.
is applied as address data. ROM64 distributes the scale frequency coat °IV according to the average rate, and also distributes the R
The OM615 stores semitone (100 cent) frequency modulation code YtgY exponential function data according to the average rate. Then, the scale frequency code β and the 11th frequency scale code gff read from the ROM 64 and 65 are both sent to the Unibu generator ls.4. Ru.

Figure 8 shows an example of actual power in the 7-year-old school in a hexadecimal code.
The 4-bit note specified data expressed by m is expressed by binary data, so in this case, 1
An inter-scale wave number code p' and a frequency modulation code a' are sent to two binary adders/subtractors 66.

An addition/subtraction command (-) may also be applied. Then, the upper N-n bits of the result data of the average rate frequency calculation executed 19 times in the binary reactor multiplier 66 are sent to 80M67, and the trT position n
Bit HR (applied to each JMs8 as address data, and RL) M67ij has the same function as the above ROM64, and R and UMIII are upper lf! ROM65
Same function as ROM64, scale frequency code)
## is tR(JM611$ etc. 1 wave number modulation code a is respectively 1i5!) ・491L army 8 figure real power example 15 ivy(, UM68%' is removed and replaced with binary or subtractor 6LC, which is the result of throwing 71V, is expressed by binary data, and both of the 6LC and 1W! subtractor 66 are represented by binary data. tlil16G.Then, the data HR (JM6
Same function as 7 (F) input to ROM70, sound 11m1
Wavenumber coat °βvw! put out. Ikekata, is the lower n bits of data Y a binary adder/subtractor? lK is applied. The other end of this binary addition/subtraction @71 is applied with data X that is equal to @ of the frequency t''1ml code 1 when R wave number modulation is not performed.Then, the resultant data X of the binary addition/subtraction @71 is applied.
Let ±Y be the frequency modulation code g, then one two a = X * Y =) (e 2 two
us outputs. For example, suppose I/m is n-6.

Also, binary addition/subtraction 1s71 is addition 1! When it functions as a L′ device, the data Y (data Y range between 0 and 630 [
If we take V) v63, then from equation (1).

X+63==X・21m・number Therefore, rl059J is selected as X.

Given by epua.

In this practical example, the semitones below show a layer-like change, but it is a practical earthen floor @ stile φ.

@lO Diagram, Binary adder/subtractor 71 in Figure 9? remove,
Decoder instead? By providing 4V, the hardware configuration becomes even simpler. Therefore, the binary adder/subtracter 72 has the same function as the binary adder/subtracter 69, and R and 0M7B have the same function as the binary adder/subtractor 69.
It has the same functions as OMyo. On the other hand, binary adder/subtractor 7
The data of the lower n bits of the result data of No. 2 is sent to the decoder 74.
The outputs of the decoder 74 after applying 4c and the data X are output as a frequency modulation code X.

On the drum, data X [lower n bits? The data is all @0#. Therefore, the following relationship (2) is established.

Therefore, data Y is given by the following equation (8) K.

Y==+X (2 = snow... -1)
(3) For example, if n=s, the lower 6 bits are all @011, and the value of X is 1111000000 (=r960J).

At this time, Y is calculated as "56" from equation (3).

Therefore, the decoder 74v is configured so that the decoder output (data Y) takes a value from ◎ to 56 according to the output of the lower 6 bits of the binary adder/subtractor 72, and the frequency modulation code a is added to the lower 6 bits of the data X. You can send it as . If you do it like this.

By changing Y to 0-Sa, the musical tone changes from ◎ to 100 cents, that is, the maximum semitone, and the pitch changes to f.As another example, for X-1101000000 (=j832J), the pitch is O≦Y≦48. .

@1ill is a frequency modulation coat °α′ and the vibrato waveform and vibrato depth designation signal are multiplied by Y [for Y-
This is an example in which the in this case.

A vibrato waveform signal is output from a predetermined waveform generator (as shown) under the control of the CPU 5, and a vibrato depth ζ indicator signal is output by operating a predetermined switch on the switch section 2. Therefore, the vibrato waveform signal and the vibrato depth designation signal are both input to the multiplier 75 and multiplied together. And of the perfect result data, the lower bit data corresponding to a semitone is.

The control signal a output from the ePIJs is applied to the average rate frequency calculator 76. Also, this average rate frequency calculator 76 has a scale frequency code °β' marked rJr!
#Receive. Therefore, the average rate frequency calculator 76 is
The circuit shown in Figure S may be used.

In this embodiment, when the control signal mv@o' level is output and the gate circuit Gt' is closed, the frequency modulation code g' in which the lower bit data corresponding to a semitone is all 101 is the average rate frequency calculator. 76-Since it is applied,
The scale frequency code p output by the average rate frequency calculator 76
4. A vibrato waveform that changes chromatically is obtained by the '1 frequency modulation code α'. Ru.

Figure 12 shows an embodiment Y in which voltament movement can be performed only during monophonic performance.

That is, the code NEW KEY C0DE, which is output when a new key is turned on, is applied to the terminal T of the ratio circuit 77. At this time, the code of the key that was previously turned on and vh is circulated as an output from the 7 lip-flop 80 to terminal 8, and is marked fJD? IR is available. and comparison circuit 77
compares the magnitude relationship between the chords T and 8, and when the chord at terminal T is smaller than the chord at terminal S, that is, when the current pitch is lower than the previous pitch, it is mis.
A level signal is output from the terminal 8)T and applied to the control terminal (-)vc of the binary adder/subtractor 7,90, causing the binary adder/subtractor γ to perform a subtraction operation t'w. On the other hand, when the chord at terminal T is thicker than the chord at terminal S, that is, the current pitch is higher than the previous pitch - and 1! 0#0# level number terminal 8)T is applied to the control terminal (c) of the binary adder/subtractor 79, and the binary adder/subtracter 79 executes the addition operation.Furthermore, the comparator circuit 7γ When the coats of both terminals T and 8 do not match, a @1# level signal is output from the terminal S to open the AND gate 78, and on the other hand,
If it matches, it outputs @0 level signal and goes to AND gate 7.
8v close.

This art/toge door 11m periodically outputs a signal Bx
gcuTg is applied, and while the AND gate 78 is open, it is given as a +1 signal 't or a -1 signal to the binary adder/subtractor 79. The binary adder/subtractor 79Vc converts the lower m bits of data to the chromatic scale of the N bits of data latched in the 7-lip filter 80 to the gate circuit GV.
The upper N-m bits of data are directly input in a circular manner through the input terminal. Therefore, the binary adder/subtractor 79 outputs the signal EXECUT to the data provided from the 7-lip-flop 80.
Execute +1 operation or -1 operation for each input of E.

The result is output to the data v7 lip 7el tube 80.

Of the N-bit data output from the 7-rip 7a tube 80, the upper N-n bits of data t! The scale frequency code r'βV is applied to the ROM81 and the FLt)M81 outputs the scale frequency code r'βV, and the data of the lower n bits is applied to the RUMBjK and the frequency high contrast code gvl! put out. Note that the gate is controlled by the gate circuit G frame tffllll signal a.

With the above configuration, when the pitch of the newly turned on key is 19 times lower than the pitch of the previous key, the binary adder/subtractor 79 executes a subtraction operation, while the pitch of the newly turned on key is 19 times lower than that of the previous key. When the pitch 19 is high, an addition operation is performed by the binary adder/subtractor 79, giving a portamento effect. Also, the control signal a v@Q
# If you output it as a level, you can get the change f6 portame/g for each chromatic scale @ IE13 diagram t! I made it possible to get a glide effect! i
! Example (b) Road is shown. The code NBW KEY C (JDF) is connected to the terminal T of the comparator circuit 83 and one end of the binary adder/subtractor 4 when a new controller is turned on.
Further, the voltage can be applied through the gate circuit Qs. At the same time as tπ, glide width data is applied to the other end of the binary addition/subtraction @84 via the gate circuit G-.

At the same time, the control terminal (-)vc of the binary adder/subtractor 84
A signal UP/dOWN is applied through a 9/X7 fugate 91. At this time, the binary calculation is $84d, and the signal is UP/down is the UP command (
@1mVbek) Throat 1! ! VcfXJ-TO NEWKgY
e(Execute glide width subtraction operation for JDEK,
On the other hand, on the negative side of the down command (@o'' level), an addition operation of the glide degree width is performed on the coat 'NBW KBY C0DE.The rice feeding data is applied to the 7 lip-flop 85.

The result data latched in the flip-flop 85 is transferred to the terminal 8vC of the comparison circuit 83 after the key is turned on.
, and a binary adder/subtractor 84 via the gate circuit Ga11'.
This can be applied to one end of . At the same time, the upper N-n bits of the effect data are supplied to the ROM 86 to read out the scale frequency code voice, and the lower n bits are supplied to R (7M87) where the frequency quality code °α is read out. The binary adder/subtractor 84 further has a control terminal (-) at which a comparator circuit 83 compares the magnitudes of the input data to both terminals 8.T, and outputs a result signal from the terminal SvT.

A signal gxgeUTE is applied to the transformer 7 through the gate 921 and applied to the other end of the binary adder/subtractor 584.
is ant 0 gate 89' and transfer gate 9
Applied through 0. Therefore, after the key is turned on, the binary adder/subtractor 84 performs an addition operation t or a subtraction operation t1! on the result data from the flip-flop 8s every time the signal EXECUTFi is input. go Then, the comparison circuit 83 determines whether the input data at terminals 8 and T match? When detected, the addition or subtraction operation of the binary adder/subtractor 84 is stopped, and the glide effect operation is stopped.

That is, the comparator circuit S3 frame terminal 8. If the two data to T do not match, a signal of ik'l' level is output, and if they match, a signal of mOs level is output from terminal S.

The voltage is applied to the above-mentioned ant game) 89. Also, the comparator circuit 8
3 is larger than the data of 4 children S or the data of terminal T @@1
On the other hand, when the level is low, a comparison result signal of 10a level is output from terminal 8) T. Furthermore, when the key is on, a signal NEW KEY t) N is output from the gate circuit Q.
s, Qs, ) transfer gates 91 are each configured to open when the key is turned on. Further, the above-mentioned signals NEW KEY 0Nv (a signal obtained by inverting the y-bar #88Vczo is applied to the gate circuit G$ and the transformer 7A-D) 9rJ and 92Vc are respectively applied, and these are opened together after the key is turned on.

Note that the signal [Jp/down and the glide width data are output in response to the switch operation on the switch section 2.

Next, the operation of the above embodiment will be explained with reference to the guard 41 to the sixth guard. First, the operation when the rectangular wave is generated by the unique wave generator 5 will be explained with reference to the time chart of FIG. In this case, first, turn on the switch for specifying the rectangular wave on the switch section 2, and operate the other necessary switches. In this case, it is assumed that no frequency change W such as vibrato is performed. Then, by turning on the square wave designation switch, the CPU 5 turns on the gate circuits Gt and QsVC5M of the Unibu generator 5.
L Huk, “H” (l [l?), ‘l’
) Level 4 ft:tz "L" (that is, @O") level signal ytM is applied. Therefore, from now on, gate circuit G1
Kaisei [1. And the gate circuit () is closed. Also(
,')'U3 is 111 for transfer gate 26
1 level signal V skewer, U transfer gate 29
．． Outputs @o# level signal to 35. Therefore, thereafter, the transfer cage 26 is opened and the transfer gates 29 and 35 are closed. Also, as a result of the above transfer game) 29.35 closing, transformer 7T
-) t'-) 33 and Hitrans 7-1'-) 3
4ma ~ 34・ is opened, and transformer 7age) 46v
〜46· or precocious.

Upper e shape W! The following will explain the case where, for example, one key on the keyboard 1 is turned on at 4Vc. in this case,
When one of the above keys is turned on, the CPU 8rl average rate frequency calculation section 4 receives a scale frequency code β corresponding to the operation key.
' and a frequency quality check code a' when there is no frequency change. Accordingly, the average rate frequency calculation unit 4
outputs the corresponding scale frequency code I and frequency quality request needle by the average rate frequency calculation, and supplies them to the unique generator 8. And this scale frequency code °β is passed through the gate circuit Qsv under construction.
It can be applied to 18u to 18. And now full adder 1
The output rz"o' of the output terminal Cout of the inverter 19 causes the output "1#" of the inverter 19 to open the AND gates 18.about.18. Therefore, the above-mentioned scale frequency code I is marked on the B input terminal B11NB@ of the AND gate 1811 arrangement 8 and the full adder 16.

On the other hand, at this time, the 8 output terminals F3u to S of the full adder 15
16-bit all @O11 data is applied from the full adder 16 to the A input terminals AI8 to A. Therefore, the result data of the full adder 16 at that time will be data with the same value as the set above-mentioned scale frequency code -, and when it is output from the 8 output terminals 3ss to S, it is input to the shift register 17 j6° and this data is shifted j , and then outputted from the shift register 17, it is circulated to the A input terminals As- to A. of the full adder 1s.

Exclusive ORGATE S! 0-~Wo@, Inver! Senior 1
211.

By the way, in the case of this example, all i[d of the scale frequency code β of each scale can be output as thicker μ values than “1024”. That is,! Top 11-16 of 6 pitt data
Any of the bits always contains data of 11". Therefore, when the above one key is turned on, the above scale frequency code °I is set. Next, the shift register 17 outputs data of the same value. At this time, the AND gate 22-21iF'1 output is always at the "0" level as shown in FIG. 4(e).
) 22-1 is also at the vc''O' level while the output of the AND gate 22-1 is @0'' as shown in tJIL4 diagram Φ).

Furthermore, at this time, the output of the inverter 50 is at the K"l" level as shown in FIG.
The output of No. 2 is at the K "O" level as shown in Fig. 4 ←). As a result, a signal at the AND gate 22-10'''O1 level is supplied to the exclusive OR days) 20- to 2o, and the data of the lower 9 bits of the output of the shift register 17 is directly sent to the A input terminal AsNA of the tRUMzs. applied.t
The ``0'' signal of the AND gate 22-2 is applied to the inverter 25 and the inverted ''l#l# level is applied to the OR gates 24.
A @P level signal is output from each of the gates 24 and 24, and applied to one end of each exclusive OR gate 27@27. The @0 level output of the polarity inversion circuit 32 is applied to the other ends of the exclusive OR gates 27.about.27. Therefore, the outputs of exclusive OR gates 27.about.-27.all become signals of @1 level. Further, the output of the inverter 31 is also at the @1m level. As a result, full adder 30a
All 11" data is input to the A input terminals A to A@. Further, the carry input terminal eirl[d of the full adder 30 is input with the output ("O" signal) of the polarity inverting circuit 32.

However, the result data for Full Adder 30 is 8.
Bit all @ 1# As data, S output terminal S
Output from 7 transformers being opened - Gate 34! ~3
The signal is sent out to the digital filter 6 via 4. Waveform 1 in FIG. 4(a) shows a rectangular cedar wave that is sent to this digital filter 6.

Therefore, the digital filter 6 removes the specified harmonic components under the control of the dcPU 3, and the envelope generator 7 applies an envelope to the output.
Generation and emission of musical tones of the scale of the operation keys is started.

When data with the same value as the set scale frequency code p is input in circulation to the A input terminals An to A of the full adder 15,
The constant value data (frequency modulation code) outputted from the average rate frequency calculating section 4 is inputted to the 1,000B input terminal BssmB in the form of 16-bit data. Also, since the carry input terminal C1n rL is always set at the 1H'' level, the full adder 18 performs the first subtraction operation t1! of β-1 at this time.

The result is output from the data Y8 output terminal, and the full adder r-I
JL, equivalent to tamono. Therefore, when executing this subtraction operation, K
l! The output of the carry output terminal Cout of the full adder 15 becomes the 11# level, so the output of the inverter 19 becomes @Om, and the ant 0 gates 1811 to 18 are closed. Therefore, the input of the scale frequency code β to the input terminal of the full adder 160B is blocked. Therefore, the result data of the full adder 16 at this time is the same as the result data of the first time of the full adder 15, and the shift register 17
give to Then, when this first result data is output from the shift register 17, it is circularly input to the A input terminal of the full adder 15, while exclusive or game) 2ol to 20.
, the data input state 1M of the A input terminal of the full adder 30 and the dP carry input terminal eln after this first calculation are unchanged from the previous time, so 8-bit all @1'' data is sent to the digital filter 6.

Full adder 15. AND GATE 181 GEI～18・.

Full adder 16. In shift register 17, the following.

The cumulative subtraction operation is exactly the same as the first subtraction operation described above, or the resultant data, that is, the output of the shift register 17 is 1.
This process is repeated until 10!4J (see Figure 4(f)). During this period, the input conditions to the A input terminal and the carry input terminal C1n of the pull adder 30 are also constantly changing, so that 8-bit all 11m data is continuously sent to the deseal filter 6 during this darkness. Then, when the output of the shift register 17 becomes smaller than "lOS!4" by the next subtraction operation.

The data of the 11th to 16th high-order bits of the output of the shift register 17 are now 10m in total.

Therefore, ANDGATE S! 2-3! The output of is shown in Figure 4 (
Invert to 1111 level as shown in e). Therefore, from now on, the output of the inverter 25 is @Om level,
Input to Rich Auto 24・-3!4・.

- 10,000, the output of the shift register 17 is the voice "1024" mentioned above.
” to “s12J”, the 10th bit data of the output of one shift register is 11”
r hold and therefore during this time.

As shown in FIG. 4(b), the AND gate 22-
The output of 1 is 10" and '1h, exclusive or day) 20
Supply to Hatake ~ 20. For this reason, the above [1(Ma4J
The lower 9 bits of the output of the shift register 17 continue to be applied as is to the A input end of the ROM2B. Also, during the above period, the polarity inversion circuit 32 is applied as shown in Figure (d) of @4. The output of continues to be diagnostic@0-level.

Therefore, if the output of the shift register 17 is assumed to be at the moment when jxo24J or less, for example 102sJ, then the lower 9 bits of the output of the shift register 17 are all @1, and the A input of the ROM23 Applied to the end. Therefore, R, (JMzaH) is addressed by this 9-bit address data of 11m, and as shown in FIG.
f- Evening is read. This 7-bit signal @1m data is exclusive to OR gate 2 via OR gates 24# to 24aY.
76-27o. As mentioned above, the carry input terminal C1nvc of the exclusive OR gates 27 to 21 and the full adder 30 is still receiving a 10'' level signal, and therefore the A input (li
nt! 8-bit all @1 data is input μ, and the resulting data also comes out as 8-bit all @pi data.

This 6° is sent to the digital filter 6.Next, for the next cumulative subtraction operation, the output of the shift register 17 is 1! from r1023J. When data a becomes a smaller value, the ROM 23 has the above-mentioned 9 bits all 1! ``The address is specified by address data that is a size smaller than the data (i.e., rsttJ). Therefore, as shown in Figure @3, from 80M23, the above-mentioned 7-bit value @1m data Lr) is small ζ ζ42, t
rS The amplitude value data is output as is without having its polarity inverted by the full adder 30 and exits to the digital filter 6 t'L.

Thereafter, in the same manner, the output of the shift register 17 decreases by Lva for each cumulative subtraction operation.

Until that point reaches [5tzJ, the address data in the ROM 23 will be sequentially addressed in the direction of decreasing ζ, and each time, the amplitude value data with a smaller value than the previous one will be assigned. Read out. During this time, the input state of data to the A input terminal and the carry input terminal C of the full adder 30 is the same as that described above, and accordingly, the input state of the data to the digital filter 6 is as described above, and the amplitude becomes smaller than rS. The sound data is sent. Then, when the output of the shift register 17 is "512J," ROM2B is addressed by address data of 9 bits all 10.Next, the result data of the cumulative subtraction operation is transferred to the full adder 15.
When changing from [sxwJ to a value equal to or less than 1s11 J, the distance from the output terminal C' of the full adder 15 to
Accordingly, one pulse signal is outputted from the inverter 50 as shown in FIG. II4 (C)K. As a result, as shown in @4 figure (d).

Polarity reversal circuit 3S! The output is inverted to 11 levels.

The exclusive OR gates 27- to 27. are applied to the inverter 31 and the full adder 30 (n carry input terminal Cin K, respectively).

Therefore, this [511J or less data is shown in Fig. 4(f)]
When the shift register 17 outputs the data as shown in Figure 4, the upper 1ON 16 bits of the output become all @0# data, so the output of the azide gate 22-1 changes to the 11'' level as shown in Figure 4). 20s to 20. On the other hand, 9 bits all 11# are again applied to the other end of exclusive open day) 20m-20.
The data is applied, and the output is 9 bits all @
The signal is inverted to 01 and applied to the A input terminal of the ROM2s.

Therefore, the result data of cumulative subtraction is r511J~rOJK.
ll [Next, the tsuba-by-small ζ power check is ROM23.

This means that the address data is sequentially addressed from all 10m to all 11# in an increasing direction. Further, the resulting amplitude value data gradually increases as shown in FIG. 3, but the amplitude value data is passed through exclusive OR gates 276 to 27 to
A@, a 10" signal is input to the human input terminal A, and a 10" signal is input to the human input terminal A, and a 10" signal is input to the human input terminal C1nVcrL@1°, so the data HROP42B output from the full adder 30 at the intersection of ζ The polarity of the successively outputted amplitude value data is likely to be inverted, and that data is sent to the digital filter 6.

As shown in @4 (f), the shift register 17 output is r
Between 1024J and "0", the amplitude of the rectangular wave shown in FIG.

When the cumulative subtraction result is jOJK as described above, the carry output terminal Cou of the vC full adder 15 is output during the next subtraction operation.
101 signal is output from t, this result.

Ant 1 gates 181S to 18. are temporarily opened, and the scale frequency code I is input to the B input terminals Bsi to B of the full adder 16.
The voltage is applied to the area. Then, when the data applied to the A input terminal of the full adder 16 and this scale frequency code °β are added, and the resulting data is output from the shift register 17, the upper ml data, that is, the scale frequency code βartoS ! 4 (b) and (e) from this point onwards for the reason mentioned above.
As shown in Antgame t'! Each output of 2-1.22-2 is ``Om0m level/l/.

After the scale frequency code ρ is set again as described above, proceed as described above.

The cumulative subtraction operation of α is executed, and the shift register 17
The output decreases from β by α, and decreases in the range of j1oz4J. During this time, the full adder 30
8-bit all @O° data is input to the A input terminal A-A-H, and @ill is input to the carry input terminal Cin.
Since the signal is being input, 8-bit all+i 0 s data is sent to the digital film 6 during this time.

The cumulative subtraction result is "1O24" or less, and further becomes "512".
”, first, as shown in FIG. 4(f),
The output of the ant 1 gate 22-2 is inverted to the 11# level from the time when it becomes smaller than zaJ, that is, less than jx02sJ. Therefore, between 11023'' and jls I SEJ, the output of the full adder 30 is.

R (JM2811t's large address (9 bits all @ 1m data) to the minimum address (9 bits all “0”)
``'' data) is sequentially addressed and read out.

-To, cumulative castle/11. ? When the fN result reaches 512J, as mentioned above, a sound 1# is output from the output terminal Cl of the full adder 15.
A signal is output, and in response to this, the output of the AND gate 22-1 becomes @1, and the output of the full adder 30 becomes t! , ROM 23Y is sequentially addressed from the minimum address 0 to the maximum address, and the data matches the amplitude value data read out, and is sent to the digital filter 6.

As shown in FIG. 4(f), the output of the shift register 17 is interpolated between j1024J and "0" using the waveform data from the square wave H1ROM 23 with the amplitude of the rectangular wave shown in FIG. 4(5m). When the cumulative subtraction result becomes less than rOJ, the carry output terminal cout of the full adder 15 is used for the next calculation.
When the ``O#O# signal is input from VC and the scale frequency code p6% is again set to the full adder 16, the next synchronous rectangular wave collapse calculation process begins.

Above is the calculation section 13 for generating one cycle of rectangular waves! I operation ends. Therefore, an example shown in Figure 4'
For example, the output of the shift register 17 tends to change from "0" to "0" -f, the sampling period (120th, the relationship between the previous and current scale frequency codes β set respectively) tT', the sampling period Y: Ts Then, the calculation period T' is given by the following equation (4
) can be expressed as 0.

T# +=*'I", @' -(
4) α Furthermore, when the frequency f of the rectangular wave generated as described above is set to the sampling frequency yt-, the linear equation (5) is expressed as follows.

! T' Next, the operation for generating PWM waves will be explained with reference to FIG. First, the PWM wave designated switch on the switch unit 2 is turned on. As a result, gate circuit G1 is closed and gate circuit Os is opened. Further, transfer gates 26, 33.34f to 34. are opened, and transformer 7 agate 29.degree. 35.48v to 46. is closed. Then, in the above-mentioned state, when one keyboard button is pressed on the keyboard 1, the calculation and generation process of the PWM wave is started.

vsi, 6th v! The explanation will start from the timing of the shift register 17.output #1 OJ ("O" at the left end of the figure), which indicates J (f>vc. That is, at this point, the output of the polarity inversion circuit 32 is shown in Fig. 5-). As shown in , the signal is 1111 levels, so the addition command is given to the adder/subtractor circuit 43KH, and the exclusive OR gates 27.about.27., inverters 31. Full adder 30 carry input terminal Gin
The @11 signal is applied to each of the K signals.

On the other hand, the subtraction circuit 41 outputs the result data #-Klil and gives it to the multiplication circuit 42, and the multiplication circuit 42 outputs the result data Cf1-K)? 'lk' is output and given to the addition/subtraction circuit 43. Further vctm subtraction circuit 43 result data #+(#
-K) r': Outputted and given to the gate circuit Qs.

In the above data, ζ-e is rxogaJ, and the data r that determines the duty ratio by t is.

Take [O≦r≦1.

Therefore, when the above l@ key is turned on, the full adder is activated according to the same operation as described for the square wave generation operation.
Data β+(β−K)r is set at the start of the 16KH calculation process. Then, a cumulative subtraction operation is performed to subtract data α (a constant value) from this setting data p+(β−K)r. and the resulting data, i.e., shift register 17
Until the output of is decreased by a until jlO3!4J.

As shown in FIGS. 5(a), (c), (d), and (e), ant gate 2g-1, inverter 50. Each output of the polarity reversing circuit 34 (Ten V game) 22-2 is m
It holds the following levels: O@, s 1%@Ill, and @Qm. Therefore, during this period, the read waveform from HROMgB becomes invalid and the data output from the full adder 30 and sent to the digital filter 6 becomes 8-bit all @Qll data.

When the result data of the cumulative Nt calculation, that is, the output of the shift register 17 becomes smaller than "1024", the output of the AND gate 22-2 is inverted to 11 levels. Therefore, while the above result data changes from "1O24" to "512J", f'
Data obtained by inverting the polarity of the amplitude value data read by sequentially addressing the LUM 23 from the maximum address to the minimum address is output from the full adder 30 and sent to the digital filter 6.

When the result data becomes "S12J", the polarity inversion circuit 32
The output is inverted to <°0# level as shown in (d), and a subtraction command is given to the addition/subtraction circuit 43.

Exclusive or gate 276-27, inverter 31
．． Full adder 30 carry human power tml child ein ゛0
1 signal is applied. Also, the above result data is j511J
As shown in Fig. 5 Φ), the AND gate 22
-1 output is inverted to @1 level. Therefore, until the result data changes from "511J" to "0゛",
The output of the full adder 30 ij:, RL) M23t' The amplitude g [data that can be addressed and read from the minimum address toward the maximum address is output for that time and sent to the digital filter 6.

And the 5th r! I! As shown in J(f), when the resultant data is less than or equal to rOJ, data β-(β-K)r is set to the full adder 16 during the primary subtraction operation. As shown in FIG. 5(b) and (6)K, when the result data is "O", the AND gate 22-1.22-
Each output of 2 is inverted to @0 level.

When the data .beta.-(.beta.-K)r is set to full adder, the subtraction operation by .alpha. is performed once again. As a result, until the data is reduced to "1024", the output of the full adder 30 is held as 8-bit all 111 data.

Then, when the result data of "f" as shown in Figure 1S (f) becomes "1024" ↓ 9 small, the output of Antogame) 2g-2 becomes @1 level as shown in Figure 5 (e) iC. Inversion-
Fru. Therefore, the resultant data that decreases to "sIS!" becomes the same data as the amplitude value data read out by addressing the output HRUMzs of the full adder 30 from the maximum address to the minimum address, and is sent to the digital filter 6.

Next yc, the result data is “s I S! Jyo* Small t!-
71 - 7% while decreasing to Kr0J, AND gate 22-1. The outputs of the polarity inverting circuit 32 are both inverted and held at the 11'' level. Therefore, the outputs of the full adder 30 during this time, the amplitude value data that can be addressed and read from the FLOM2av minimum address to the large amount address. V is the data with the polarity reversed.

The signal is sent to the digital filter 6.

This concludes the 1lillll- calculation processing operation of the PWM wave! end.

The following is a quick recap of what was said above. The frequency f. is the same as in the case of a rectangular wave, and is expressed by K in equation 1 (5).

Next, the case of a sawtooth wave will be explained with reference to FIG.

First, the sawtooth wave designated switch on the switch unit 2 is turned on. As a result, gate circuit G! is opened, and gate circuit Gs is closed. Also, transfer gate 29.
35 is opened, and transfer gates 26 and 33 are closed. And the keyboard in the above condition! 1 above
When the medium of -V is violated, the arithmetic processing for generating a sawtooth wave starts.

Now, the output of the shift register 17 shown in FIG. 6(d) is "
The explanation will start from the tinging of "0"("0" at the left end of the figure). At this point, the scale frequency code β is full adder 1
It will be set up at 6. Therefore, when this scale frequency code β is subsequently output from the shift register 17, the code β
is data larger than r1024J, so Fig. 6 Φ
), (e) Wc as shown, and gate 22-1
．． Each output frame of 22-2 is inverted to the K"O" level. Since the output of the AND gate 22-2 is mOs, the output of the inverter 37 is @6 m, and the output of the inverter 47 is
The output of is @11 (transfer game) 34? ~34・Close and transfer 2-
46-46 are opened. Also full adder 115.
16. Shift register 17. anime game) 1B11-/
In 18・, data is directly obtained from the above scale frequency code 9β (-
The cumulative subtraction operation starts to subtract the electric power value). The output state of the AND gate 2-2 changes until the data as a result of the cumulative subtraction operation decreases by rl(M!4J'[K), and is divided into the digital filter 6. The output of the display circuit 44 is sent out through the open transfer gates 461-46.Y.Then, the division circuit WI!
The input terminal AK of 44 is the output data M-K of the subtraction circuit 45.
is input, and the output data I-K of the subtraction circuit 41 is applied to the input terminal BK. Therefore, the output data H' of the division circuit is given by the following equation (6)! I will be let down.

1M is the output of the shift register 17, the Ka-electric value, and in Jin's embodiment, jto24J,H is the large amplitude value, which is "256" in this embodiment. Therefore the expression (
6) can be rewritten as the following equation (7)・−1024 )1 # W X 256 ・−(
7) β -1024 As can be seen from equation (7), when the output M of one shift register, that is, the resultant data of cumulative subtraction becomes "lOha", the data sent to the digital filter 6 is " O
”. Then, as shown in Fig. 6 φ), if the resultant data is less than j10244, it is ant.

As shown in FIG. 6(C), the output of the gate 22-2 is @I
16 is inverted to II level, therefore, transformer 7 gates 34T to 34 are opened, and transfer gate 4 is opened.
6 ma to 46 · are closed. And the result data above is j!
Since the AND gate can operate until I decreases to 12J, the output 11m of the inverter 28 becomes exclusive or gate 27.9S through the open transfer gate 29v.
! 7., inverter 31. The carry input terminals C1n and VC of the full adder 30 are applied respectively. That is.

The dark value of the result data is r1o2sJ~jst.

RUM28t' The data in which the polarity of the amplitude value data which is sequentially addressed and read from the highest voltage address to the bell-smallest address is inverted is outputted to the full adder so or c, and is passed through the transfer gates 34 to 34 to the digital filter. 6.

When the result data is smaller than 12J, Figure 6 (b
)K As shown, the output of the gate 22-1 is also 11''
Flip to level. Therefore, after that 111m signal is applied to the exclusive OR gates 20I~20@, the ROM
23 is addressed from the small address to the maximum address while the output @Om of the inverter 28 is the exclusive OR gate 276-27.

Inverter 31. Full adder 30 input terminal G
are respectively applied to in. For this reason, “fillJ-rOJ
At this point, the amplitude value data read from the dROMzs is directly sent to the digital filter 6. Then, scale frequency code I is set again in full adder 16? be done.

This completes one cycle of sawtooth wave generation. The frequency f@ is expressed by the following equation (8).

f・　=fI・□　　　　・・・(8)□ It is necessary to double the scale frequency code p.

Next, an explanation will be given of the operation when applying frequency modulation, vibrato, etc. to the musical tone generated by the above-described operation. In this case, the average rate frequency calculation section 4 of each of the embodiments shown in FIGS. 7 to 13 is frequency modulated? Performing a different operation than when not performing the scale frequency code °β,
The data α, which is not a constant value but always changes, ie, the one-frequency modulation code 1, is output and supplied to the web generator 5.

First, in the case of the embodiment shown in FIG. 7, the data of each lower n pitch of the scale frequency code β'1 frequency modulation code a' outputted from the CPU 5 as data of both vcN bits is applied to the binary adder/subtractor 63&C.

Also, each data in the upper 4 bits of the hexadecimal code is 12
The upper Nn-4 bits of data 4 are applied to the binary adder/subtractor 62 and are applied to the binary adder/subtractor 61 as a signal 7JrI. Similarly, in each adder/subtractor 61 to 63, c
The addition command iy: from pua executes an addition operation or a subtraction operation according to the subtraction command. In that case, the carry output of the binary adder/subtractor 63 is applied to the terminal C1nK of the binary adder/subtracter @62, and the carry output of the binary adder/subtracter 62 is applied to the terminal Cin T/c of the binary adder/subtracter 61.
applied.

And each result data frame R of the binary adder/subtractor 61 and 62
It is applied to the OM 64, and the scale frequency code 1/71 corresponding to the scale of the operation key is read out. On the other hand.

The resultant data of the binary adder/subtractor 63 is applied to the ROM 65, whereupon a frequency modulation code is read out which changes the frequency of the generated tone by a semitone according to the average rate. That is, 1
As is obvious from equation (5) or equation (8), if one frequency modulation code value changes, the frequency f of the generated musical tone also changes, and frequency modulation such as vibrato is performed.

In the case of the embodiment shown in FIG. 8, the scale frequency code β and the frequency modulation code Ia' are both represented by binary data and applied, and the binary adder/subtractor 66 operates on both codes β.
' , g' f Add or subtract and supply the resulting data to the upper N-111 bits) yaOM67, and also to the lower n
Bip) @ROM158fC is supplied. I want to do it R, 0
M6? The scale frequency code p corresponding to the scale is read out, and the frequency modulation that is performed by ROMill or 6
In the embodiment of FIG. 9, the binary adder/subtractor 69 has a scale frequency code β' and a single wave number modulation code.

Add α' and subtract tr, resulting in data b upper N-n
It is applied to the bit yRUM 70 and also applied to the lower n bit data Yg binary 11 and the output P subtracter 71. Therefore, the UM70 has a scale frequency code β corresponding to the scale.
It can be read out. On the other hand, the other end K of the binary adder/subtractor 71
Data X having the same frequency modulation code value (constant value) when no frequency modulation t is applied is output from the CPU 5 and applied. This data X is calculated using the above equation (1). Therefore, a frequency modulation code based on the binary adder/subtractor result data X+Y or X-Yvc is output.

In the case of the embodiment shown in FIG. 1O, the binary adder/subtractor 72 has a scale frequency code β'1 frequency conversion using binary data, and a key code g'
, a subtraction command is applied to the addition command t, respectively. And the upper N-n bits of the resulting data are in the ROM? 3
1 is applied, and 1 is applied to the data 6-decoder 74 of the lower n bits.

Therefore, the scale frequency code p corresponding to the scale is read out from the ROM 7B. On the other hand, regarding the data X having the value when the lower n bits of data t are all IIQII, the decoder 74 outputs tt6 data Y calculated by the above equation (3). Then, data obtained by adding data Yt to the lower bits of data X is output as a frequency modulation code α. Therefore, frequency modulation is performed using a frequency modulation code that changes according to the nitridation of data Y.

In the case of the embodiment shown in FIG. 11, the vibrato depth can be specified by operating the switch on the switch section 2. Also, when a chromatic vibrato is not to be applied, other switches are operated in the same way, and the signal a is output as 111 to cause the gate circuit ovNw. As a result, after the key is turned on, the scale frequency code β' of that key is output and the average frequency calculator 76
If you apply it to it, it will be destroyed.

In addition, in multiplication $75, the vibrato waveform and each signal specifying the vibrato depth are multiplied, and as a result, the upper bits of the data + It is applied to the electronic device 76 as a frequency modulation code α''. Therefore, in the average rate frequency calculator 76, according to the operation of the embodiment circuit of FIG. It changes with the same depth and speed across the scale.

On the other hand, chromatic vibrato? When you hang it, operate the ercrz prescribed switch in that way, and the 10m signal a? Keep the gate circuit () closed with a small output. Therefore, multiplier 7
The average rate frequency calculator 76 uses all aSS as the lower bit data corresponding to the semitone of the @ result data output from 5.
1C is applied. Therefore, the frequency modulation code output from the average rate frequency calculator 76 is output as a signal indicating a change such as adding chromatic vibrato.

In the case of the example of the first diagram, when obtaining a voltament effect during monophonic performance, this 1! The example circuit operates. That is, when the current key is turned on after the key has been turned off * times, the signal INNgWKEYCC)DM of that key is output, and the terminal TK of the comparison circuit 77 is applied. At this time, the code of the previous function key is applied to terminal 8 of comparison circuit 77.

Therefore, the comparison circuit 77 determines whether the two codes are related in magnitude? There's a comparison. When the pitch of the previous key is low or the pitch of the current key is low, the comparator circuit 77 outputs a 1m level signal from the terminal S>T to the control terminal (-
) and subtract command? give. Also, a signal at the "1" level is now output from the terminal S to the comparator circuit 77, and the AND gate 78Y is opened. Binary addition/subtraction Wh
7 Signal EX via GH and GED78] 13eUT
Each time E is input, -1 operation Y is performed, and the code of the previous key is decreased by 1. It was. Assume that the signal a is currently being output as "!1. Therefore, the upper N-n bits of the result data from the above subtraction operation are applied to the ROM 81, and the lower n bits are applied to the ordinary UMIM!, respectively. The frequency code p1 is read out as a frequency modulation code.The frequency modulation code e1 in this case indicates a change in which the frequency decreases in sequence according to the average rate.On the other hand, if the above signal is output as t's, For short, frequency modulation code a indicates a change in frequency that decreases chromatically.

Then, the comparison circuit 77 connects both terminals 8. When each code of T is detected, a signal of @Om level is output from terminal 8NT, undate 781i/closed, and binary addition/subtraction 1j is performed.
The subtraction operation of L879 stops. That is, the voltament movement from the treble side to the bass side is completed by one or more operations.

On the other hand, if the pitch of the current key is higher than the pitch of the previous key, the comparison circuit 77 receives a @0 level signal from terminal 8) T? Output and add command to binary adder/subtractor 79? give.

For this reason, the binary adder/subtractor 79 has a comparison circuit 77 at both terminals 8. Each data of T executes +1 operation until P:I, and in response, the scale frequency code p for the - scale being operated is output from approximately 0M81, and ty, = ROM8
From 2 onwards, a frequency modulation code 6 is output, showing a change in which the frequency increases sequentially according to the average rate. Now signal a
If we set the frequency modulation code g to the 0° level, the frequency modulation code g can be changed in such a way that the frequency increases chromatically.Therefore, this scale changes.The speed changes over the entire range. It's uniform.

In the case of the example shown in Figure @13, the glide effect of tUP J4v
%, operate the switch in switch section 2 in the same way. Also, use the switch to set the glide width. Then, when the key is turned on, a single signal NEW KEYON (@1m) is output and the gate circuit Q1. Q*.

Transfer gates 91 are both opened FIt. Therefore, the binary adder/subtractor 84 is NWB KFIY ON
function as a subtractor. Also, from the above key on, the code NBW KEY C0DE is the gate circuit q1v.
t is applied to one end of the binary adder/subtractor 84, and a glide width is applied to the other end of the binary adder/subtractor 84 via a gate circuit q. Therefore, when the key is turned on, the binary adder/subtractor 84r echoes 'NEW KEY'.
C0DE or G) f9i V width? The resulting data is applied to the 7 lip-flop 85.

After outputting the first signal NEW KEY U”N, the output of the inverter 88 is inverted to @111 v,...d, and the transfer gates 90, 9M and gate circuit Ga
will be developed. Therefore, the above fruit yield data is
In addition to being applied to the terminal S of the binary adder/subtractor 84, a signal 71t1 is applied to one end of the binary adder/subtractor 84 via the gate circuit Gsv. The comparator circuit 83 thereafter connects the terminal 8. Compare each data of T, output a signal at the 0° level from terminal 8)
It is given via V and used as an addition instruction. Furthermore, the comparator circuit 83 outputs a ``1'' level signal from the terminal SfuT to
) 89 wnWt, and the signal BXBCUTB is applied to the other end of the binary adder/subtractor 84 via the ant 0 gate 89 and the transfer gate 90. Therefore, the binary adder/subtractor 84 performs a +1 operation on the result data each time the signal EXECUTH is input. And the top N-n pi)r of each result data! R (given to JM8@, and the lower n bits are given to ROM87. Therefore, from ROM86, the scale frequency code °
β can be read. Further, a frequency modulation code α is read out from the ROM 87 in a manner that the frequency increases sequentially according to the average rate.

You can get the glide effect of UP. Then, the comparison circuit 83 connects both terminals 8. When the data of T matches, a @O” level signal is output from terminal 8MT and ant 9 gate 89v is output.
It closes and the generation of UP's Glide 9 effect stops.

a7j, when you get the glide effect of DOWN.
of! 'Switch to 5? Manipulate. When the key Y is turned on, the binary adder/subtractor 84 outputs a signal NEW KEY (JN), and when the signal NEW
Execute glide width addition operation 1 for E.

As a result, -f is applied to the data Y flip 70 knob 85.

From then on, the binary adder/subtractor 84 performs one operation on the result data every time the signal EXHCUTH is output.
Its value decreases by 1.

For this reason, the scale frequency code β is read from R(JM86, while the water-tS wave number modulation code is read out from M87, which changes the frequency gradually decreasing according to the average rate, and the glide of DC)WN. Effects can be obtained. Therefore, the speed at which the scale changes remains constant over the entire range.

In the above-described square wave, PWM wave, and sawtooth wave generation operations, we have explained the case where only one key on the H1*-board 1 is turned on, but in this example, it is for polyphonic use of the music synthesizer vsit. , even if up to 8 keys are turned on at the same time.
Each of the circuits shown in FIG. 1 and FIG. 2 can simultaneously generate the above-mentioned fundamental waves for 6 out of 6 channels using the time-division processed product fl'F of 8 channels, but detailed explanation thereof will be omitted.

In the above embodiment, there are three types of fundamental waves: a rectangular wave, a PWM wave, and a sawtooth wave, but it is also possible to use other fundamental waves such as a triangular wave and a slope wave. In addition, this was done using an interpolated sine wave where the amplitude level of the fundamental wave suddenly changes, but the quadratic number,
Cubic function, 11 number function.

Other function pieces l1It# such as triangular relationships may also be used. Also, in the above embodiment, a 174-cycle sine wave is stored in the ROM2s. !
-Although I wanted to use a sine wave with one period or 1/2 period, it is also possible. More above! ! In the example, after setting the initial value 1ρY full value, the cumulative subtraction 11L operation was performed to subtract the constant value av @ next, but after setting the initial value I, the cumulative addition operation 1 was performed to sequentially add the electric value g9. , the fundamental wave similar to the above example?
You may also perform arithmetic processing to obtain.

Of course, the present invention is not limited to the musical instrument/synthesizer, but can also be used for other electronic musical instruments, and can be modified and applied at will without departing from the spirit of the present invention.

As explained above, in this invention, when a scale frequency is determined by arithmetic processing by a digital circuit and one frequency modulation is performed, equal crisis wave number modulation can be performed on the plus side and the minus side by simple arithmetic processing.

Moreover, since we have provided a frequency control device Y for electronic musical instruments that can easily perform frequency modulation of semitones or more, and can also easily perform gradations, voltament effects, and glide effects, the plus side and minus side are equal according to the average rate. The more easily the frequency modulation can be performed and the more natural vibrato effect etc. can be obtained, the more natural voltament effect, glide effect etc. can be obtained. Also, the calculation process is simple.

The hardware configuration has become simpler, and electronic musical instruments have become smaller, etc.
There is also the advantage of being able to give 4 points.

[Brief explanation of drawings]

@Figure 1 is a system diagram of a vc based synthesizer according to an embodiment of the present invention, Figure 2 is a specific circuit diagram of the Unibu generator 5, and Figure @3 is a memory waveform diagram of ROM2B.
l! Fig. 4 is a time chart explaining the rectangular wave generation operation, Fig. 5 is a time chart explaining the PWM wave generation operation, Fig. 6 is a time chart explaining the sawtooth wave generation operation, and Figs. FIG. 13 is a circuit diagram of various embodiments for performing frequency modulation. 1...Keyboard, 2...Switch section, 3.・
...CPU, 4...Average rate frequency calculation section,
5...Unibu generator, 6...Digital filter. 7... Envelope a-pusi generator, 81F digital/analog converter 11S, 1g, 310...
Full/゛1 adder, 1 piece...shift register, 18s
s~18...and gate, SC0-~20.,2
7・～27・φ・・Exclusive boteday), 21-7～2
1-1...Inverter, 22-6 to 22-1...-
Antogame), SC2...RUM, 241
~24...Toagame), 26. To 29,3 B,
35° 34mm ~ 34., 46mm ~ 46... Transfer gate, 31... Inverter, 32
...Polarity inversion circuit, 41.4fi...Subtraction circuit, 42...Multiplication circuit, 43...Addition/subtraction port,
44...Division circuit. (ls, G fable...gate circuit, 61.6B, 66゜69.71.72.79.84/(inari furnace subtractor, 62...bow S! base addition/subtraction device, 64.65゜6?
, 68. To, 78, 74, 81, 82゜86.8〕-
ROM, 74... Decoder, 7s... Multiplier, 76... Average rate frequency calculator, 77°83.
...Comparison circuit, 80,85...7 lip-flop, G, 01-Gs...gate, 8B...in I
(-ta, 89...and gate, 9O-9jJ
...Transfer gate. g, &J %J
'ill w---11

Claims (9)

[Claims] (1) Means for supplying first frequency information corresponding to a change in frequency of a semitone or more and second frequency information corresponding to a change in frequency within a semitone; From the initial value to the second frequency information V
When the output of the calculating means for adding or subtracting and the calculating means of C satisfies a predetermined condition, the first frequency information is supplied from the supply means to the calculating means again. The frequency mkl? of the output musical tone is calculated based on the output of the arithmetic means. 1. A frequency control device for an electronic musical instrument, characterized in that it performs ll control. (2) The first item supplied from the supply means. 2. The frequency control device for an electronic musical instrument according to claim 1, wherein the second frequency information has a value corresponding to the average rate frequency and is φ. (3) When the above supply means specifies 1 frequency modulation. Above 1. 3. The frequency control device for an electronic musical instrument according to claim 1, wherein the second frequency information vw4 is periodically variably controlled and given to the calculation means as a ytW signal. (4) When 1-frequency modulation is specified for the supply means. the above? 1! The frequency information of the electronic musical instrument as set forth in Claims @Claim 1 or @Clause 22, characterized in that only the frequency information of 1 is synchronously and variablely controlled and given to the calculation means, and the frequency of the output musical tone is modulated every semitone. Control device. (5) When one frequency modulation is applied to the supply means. One frequency modulation function information is added to the basic frequency information corresponding to the scale frequency, and the above-mentioned 1. Obtain the second frequency information, and obtain the first frequency information. The electronic musical instrument according to claim 1 or 2, characterized in that by supplying the second frequency information to the calculation means, frequency modulation of a constant depth is performed in the entire sound frequency range. Frequency control device. Mail (6) The above supplying means is provided with the above @1,112 for the musical tone being sounded by Voltapunto.
Based on the frequency information of
e 1st. The second frequency information is sequentially changed. The misaki wave number m+@ device for an electronic musical instrument according to claim 5tIIJ1 or 2, characterized in that the device supplies t to the calculation means. (7) The above-mentioned supply means is configured to perform portamento performance t'
Claimed claim ``@6, characterized in that only the first frequency information is changed and supplied to the calculation means, and a voltament effect that changes every semitone is applied to the output musical tone. Frequency control device for electronic musical instruments. (8) When glide performance is specified for the above supply means 1
Basic frequency information corresponding to the frequency of the musical tone to be produced
K. Sequentially changing the frequency information obtained by adding and subtracting a predetermined Iv to the basic frequency information, and supplying the changed frequency information to the calculation means as the frequency information of 1 gl and $2. Characteristic claims @1
A frequency control device for an electronic musical instrument according to item 1 or 2. (9) When glide performance is specified, the supply means
Only the frequency information of the above @l is changed by t and supplied to the above calculation means, and the output musical tone vc becomes quiet and gives a glide effect Y that changes every semitone. A single wave number control device for an electronic musical instrument according to claim 8.