JPS6374100A - Electronic musical instrument - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic musical instrument that generates and emits musical tones based on stored waveform information.

[Prior art and its problems] Conventionally, such electronic musical instruments sample external sweat at a predetermined period, perform A-D (analog-to-digital) conversion, and write this into a waveform memory. Due to storage capacity issues, a device with a loop function has been realized in which a portion of the waveform information in the waveform memory is repeatedly read out each time a musical tone is emitted.

In this case, if the waveform information that is repeatedly read out has a zero-crossing point where the waveform level becomes rQJ at the final address as shown in Figure 4, even if the waveform information is repeatedly read out, it will be relatively low as shown in Figure 5. Allows for smooth playback. However, as shown in Figure 6, if there is no zero-crossing point of the waveform at the final address, the waveform joints are not continuous, resulting in a clicking sound, or a frequency different from the original waveform frequency. There was a problem that the child was born alive.

[Object of the Invention] This issue 11 has been described above. '1 This was done in view of the national security situation, and its purpose is to create an electronic device that can reproduce music without making a creak sound or fluctuating the frequency when loop g & moat is executed. The goal is to provide musical instruments.

[Summary of the Invention J In order to achieve the above-mentioned object, the present invention has the following features: When reading out a stored waveform repeatedly, the readout waveform is
The main point is that the first address of the read address is corrected.

[Configuration of Embodiment] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In this embodiment, the waveform memory 3 has C as the waveform information storage means.
The PUI serves as a reading means, the sound system IO serves as a musical sound generation means, and an integer pitch data register 11. The decimal pitch data register 12, the integer part adder 18, and the decimal part adder 19 serve as stepping means, the comparator 22 serves as a detection means, the repeat address register 17 and the data selector 23 serve as return means, and the address correction register 1 day. The gates 24 respectively correspond to the correction means.

This embodiment is an electronic musical instrument having an 8-tone polyphonic configuration using time-division processing, and correspondingly, each register in this embodiment has an 8-stage configuration. The read address consists of an integer part and a decimal part.

Figure 1 shows the overall circuit of an electronic musical instrument. In the figure, 1 is a CPU that controls all operations of the electronic musical instrument. 2 in the figure is a microphone, which is used to pick up external sounds. The sound picked up by the microphone 2 is subjected to sampling processing by the CPU and is stored in the waveform memory 3. The waveform stored in the waveform memory 3 is displayed on the LCD 6 via the driver 5 by operating the switch section 4 . On the other hand, the switch unit 4 uses data, etc. for correcting the waveform readout start address, the final readout address, and the readout start address for repeatedly reading out the waveform data while viewing the waveform displayed on the LCD 6. The above data is set in the waveform control m8'I17. When a key on the keyboard 8 is pressed here, the waveform data stored in the waveform memory 3 is read out by the waveform control section 7, an interpolated waveform value is created by the waveform creation section 9, and then released by the sound system 10. make a sound

FIG. 2 shows the details of the waveform control section 7. In the figure, 11 and ]2 have an 8-stage configuration! an i number bee, a ti data register and a decimal pitch data register.

In these integer pitch data registers 11, zJ4 + pitch data 1/registers J and 2, step interval (pitch) data indicating the step interval of the waveform information read address is stored divided into an integer part and a decimal part. There is. This integer pitch data register 11, decimal pitch data register 1
The step interval data in 2 is shifted to the jlI order by the channel timing clock signal Φ, and the step interval data at the final stage is sent to the integer part adder 18 and the decimal part 11 calculator 19 as the data of the channel timing, respectively. At the same time, it is fed back to the integer pitch data register 11 and the decimal pitch data register 12, and is held in circulation. In this embodiment, the step interval data of each channel are always rl and OJ.

On the other hand, the 8-stage integer address data h l 4, 1± in the decimal address register 15, and 1 read address data of the waveform memory 3 in which waveform information is stored are also stored separately into an integer part and a small part. The read address data in the integer address register 14 and the decimal address register 15 are sequentially shifted by the channel timing clock signal φ, and the read address data of the final stage is given to the waveform memory 3 as the data of the channel timing. . In addition, the read address data from the integer address register 14 and the decimal address register 15 has an integer part that is sent to the data selector 23,
After the integer part of the step interval data from the integer pitch data register 11 is added to increment the address by the integer part adder 18 via the integer correction half addition ``A20'', the integer address register 14 The decimal part is returned to the decimal part adder 19 via the decimal correction full adder 21.
After the decimal part of the step interval data from the decimal pitch data register 12 is added to increment the address, it is fed back into the decimal address register 15. A carry signal generated by the addition in the decimal part adder 19 is given to the integer part adder 18 and carried to an integer value.

The waveform memory 3 is stored in the master and end address register 13.
The final address of the read address 1/ is stored. The final address data in the end address register 13 is sequentially shifted by the channel timing clock signal φ, and the final address data is sent to the comparator 2 as the final address data at the channel timing.
2 and the end address register 13
It is fed back into the circuit and held in circulation.

The comparator 22 compares the final address register data given from the end address register 13 with the integer value of the read address data given from the integer pitch data register 11, and when the integer value of the read address becomes greater than or equal to the value of the final address, , a detection signal indicating that the final address has been reached is sent to the gate 24 as an open signal, and is also given to the data selector 23 as a select/cut switching signal, so that the input selector destination of the data selector 23 is set to an integer pitch. The data register 11 is switched to the repeat address register 17.

Furthermore, in the repeat address register 17.

A starting address (repeat address) for reading out the waveform memory 3 is stored. The start address data in the repeat address register 17 is sequentially shifted by the channel timing clock signal φ, and the start address data of the final stage is output as the data of the channel timing, and is inputted back to the repeat address register 17. and is kept in circulation. This repeat address register 1
When the read address of the waveform memory 3 reaches the final address, the first address output from the waveform memory 3 is output from the data selector 23, the integer correction half adder 20, and the integer part addition base 1.
8 to the integer address register 14, and the read address is set as the first address.

The address correction register 16 stores a correction address for shifting and correcting the actual read start address so that one read waveform of the waveform memory 3 is continuous when the read address is returned to the start address. The corrected address data in the address correction register 16 is changed to l”4 by the channel timing clock signal φ.
After being shifted to the next stage, the corrected address data of the final stage is outputted as data for that channel timing, and is also inputted back into the address correction register 16 and held in circulation. The correction address output from this AT 1/S correction register 16 is the repeat address register 1.
Simultaneously with the input of the first address of 7 to the integer pitch data register 11, it is added to the decimal value of the read address from the decimal pitch data register 12 via the gate 24 in the decimal correction full addition 'LA21, and the decimal value is added to the decimal part adder 19. The data is input to the decimal pitch data register 12 via the decimal pitch data register 12, and the read start address is corrected. The carry signal generated by the addition in the decimal correction full adder 21 is integer correction ゛r addition'0
It is given to base 20 and carry is carried out to an integer value.

[Operation of the embodiment] Next, the operation of this embodiment will be described.

First, use microphone 2 to absorb sweat from the outside, and then
Sampling processing is performed using the UI, and the waveform information is stored in the waveform memory 3. FIG. 2 shows an example of the above waveform information.

Next, the switch unit 4 is operated to display the waveform, and the waveform based on the waveform information stored in the waveform memory 3 is displayed on the LCD 6. Furthermore, by operating the switch section 4, scroll the screen and search for the sampling point where the waveform value is "O".For convenience, let this sampling point be the address rQJ, and by operating the switch section 4, set the repeat address. Set the address “0” at this time in register 17. Next, address “0”
A value "8" corresponding to the next address of the zero-crossing point where the waveform value changes from minus to plus at a location other than that is set in the end address register 13. Thereafter, while pressing a key on the keyboard 8, the switch section 4 is operated to set the correction data in the address correction register 16. Here, when the audible sense of discomfort disappears, the operation of the switch section 4 is stopped. Now, the correction data is ro, 4
Suppose it becomes J. At this time, the waveform values of addresses rO, 4J and the waveform value of address "8" match.

Next, it is assumed that when the player enters the performance mode and presses a key on the keyboard 8, a channel such as the first channel whose read addresses of the integer address register 14 and the decimal address register 15 are rO and OJ is designated. When it comes time for the first channel! 1ia address register 14
Since "O" is output from the comparator 22, the detection signal is not output from the comparator 22. Therefore, the gate 24 is closed and no correction data is given to the decimal correction full adder 21, and the input select of the data selector 23 The destination is integer address 1 / register 1
4.

Integer address register 14, decimal address register 15
The read address of ro, 0+ output from
, are applied to the integer part addition base 18 and the decimal part adder 19 via the integer correction half adder 20 and the decimal part correction full adder 21. Since the integer part layer multiplier 18 and the decimal part adder 19 are given the step interval data of rl and OJ from the integer pitch data register 11 and the decimal pitch data register 12, the above-mentioned read address of rO and OJ is given. The data is r
l, OJ, and is fed back into the integer address register 14 and decimal address register 15. By repeating this process, the read address data of the waveform memory 3 becomes rl, o''r2. o” r3.
The waveform information is read out from the waveform memory 3 and sent out. The waveform values read out from the waveform memory 3 are subjected to interpolation processing in the waveform creation section 9, and are emitted by the sound system 10. .

Integer address register 14 and decimal address register 15
When the read address data from and becomes r8.0, a detection signal is output from the comparator 22, so ! Ii number correction correction half adder 20 is given "0" from repeat address register 17 instead of "8" from integer address register 14 via data selector 23, and decimal correction full adder 21 is given "0" from repeat address register 17 by the detection signal. ro, 4J from address correction register 16 to be opened is given.

As a result, in the decimal correction full adder 21, ro from the decimal address register 15, rQJ of OJ, ro from the address correction register 16, and "4" of 4J are added together and output to the decimal part addition 'r&19. half adder 2
0 from the repeat address register 17 is directly output to the integer layer multiplier 18. The integer part layer multiplier 18 and the decimal part adder 19 convert the step interval data of rl and OJ into the integer correction half adder 20 and the decimal correction full adder 21.
ro is added to 4J and incremented to rl, 4J, and the integer address register 14 and decimal address register 1
5 is input.

In this way, the next repeat start address after the read address of ``r8.0'' is corrected to rl, 4J instead of rl, OJ, and the waveform seam when the waveform is repeatedly read becomes continuous and smooth. At this time, the waveform generator 9 reads out the address “1” from the waveform memory 3.
” and the waveform value of address “2”, a waveform value corresponding to address r1.4J is determined by interpolation processing and output to the sound system 10.

Next, the read address data of the waveform memory 3 is r2.
．． 4J r3.4J r4.4J・・・・・・r7
．． 4J r8. When incremented to 4J, the address correction register 16 and repeat address register 17 are similarly set.
rQ,4'' is given, but this time the decimal part from the decimal address register 15 is not ``0'' but ``4'' of r8.4J.

The output from the decimal correction full adder 21 is “8” of rQ,8”
Therefore, the next read address data is rl, 8'' r
2.8"r3.8J...r7.8"r8.8
It becomes J. Similarly, the next read address data is r2.2. + r3.2" r4.2J...
・・r7.2J r8.2J, and henceforth r1.6
J r2.6" r3.6J...r7.6.
+ r8.6'', r2. o” r3. O.J.・
..., r7, Oj r8, OJ, and so on.

Note that the end address data is not limited to "8" mentioned above.
Furthermore, the value of at(/s) after the next zero crossing point may also be
Alternatively, different waveforms may be read out for each channel. Furthermore, the correction data of the correction means may be subtraction or the like in addition to addition, and is not limited to the above embodiment, and the same applies to the names of the other means 1.

[Effects of the Invention] As explained in detail above, this invention corrects the start address of the readout address so that the readout waveform is continuous when reproducing and reading out the stored waveform. When reading out the green color, the seams in the waveform become continuous.

This produces effects such as no click sound being generated and musical tones having the same frequency as the original waveform frequency being emitted.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is an overall circuit diagram of an electronic musical instrument, FIG. 2 is a detailed diagram of the waveform control section 7, and FIG.
4 shows the waveform information stored in the waveform memory 3, FIG. 4 shows the waveform repeatedly read from the waveform memory 3, and FIG.
8 are diagrams showing the correspondence between conventional storage waveforms and repeat readout waveforms. 1...CPU, 3...Waveform memory, 7
... Waveform control n section, 10 ... Sound system, 11 ... Integer pitch data register, 12 ... Decimal bif/chi data register, 16
...Address correction register. 17...Repeat address register, 1B...
...Integer part addition type, 19 ... Fractional part adder, 22 ... Comparator, 23 ... Data selector, 24 ... Gate, 25... Waveform memory. 7,,,:”',:, , ゛Agent Patent Attorney Machi 1) Toshi Tadashi [Otsu;'1,'1
]-2j Fig. 1 all 4 fins 1a Fig. 5 it' is still Fig. 6

Claims (1)

[Scope of Claims] Waveform information storage means for storing waveform information of musical tones, reading means for reading out the waveform information from the waveform information storage means, and generating and emitting musical sounds according to the waveform information read by the reading means. In an electronic musical instrument equipped with a musical tone generation and sound emitting means, when reading waveform information by the reading means,
an incrementing means for incrementing the read address; a detecting means for detecting that the read address incremented by the incrementing means has reached the final address of repeated reading; a restoring means for repeatedly returning the read address incremented by the incrementing means to the starting address for reading; and a correcting means for correcting the starting address so that the readout waveform is continuous when the reading address is returned by the restoring means. An electronic musical instrument characterized by having.