JPS6223873B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a compression/expansion device for a digital electronic musical instrument having a plurality of musical tone generation circuits. The present applicant compresses and expands musical tone information output from a digitally controlled musical tone generation circuit based on envelope information, thereby producing a low-bit D.
- We first filed a patent application for the content that enabled high-quality musical tones to be obtained with just one A converter (Japanese Patent Application 188787, 1987, ``Compression/expansion method for digital electronic musical instruments''). According to this invention, valid data is supplied to the D-A converter regardless of whether the output is a single note or a compound note, dramatically improving the dynamic range of digital electronic musical instruments. It became possible. Furthermore, according to the invention of the prior application, the number of times compression/expansion processing is switched can be reduced, thereby solving problems such as generation of noise and modulation of other musical tone signals by one musical tone signal. The present invention has been achieved by applying the above technical idea to a digital electronic musical instrument having a plurality of musical tone generation circuits, each of which can generate digital musical tone information for a plurality of tones through time-sharing processing. Synthesizing digital musical tone information obtained from the musical tone generating circuit, and synthesizing digital envelope information obtained from the plurality of musical tone generating circuits,
Based on this synthesized envelope information, the synthesized musical tone information is compressed (or expanded),
After that information is converted into an analog signal by a DA converter, the analog signal is amplified (expanded or compressed) according to the envelope information to obtain the original musical tone signal. A specific musical tone generating circuit among the plurality of musical tone generating circuits synthesizes the digital musical tone information generated by itself and the digital musical tone information transferred from other musical tone generating circuits using an internal synthesis means. , so that the digital envelope information generated by itself and the digital envelope information data transferred from other musical sound generation circuits are synthesized by other internal synthesis means,
It is an object of the present invention to provide a compression/expansion device for a digital electronic musical instrument that executes the compression/expansion processing described above, thereby making the circuit more compact and improving performance effects. Hereinafter, one embodiment of the present invention will be described in detail. Figure 1 shows the circuit block of this embodiment, where 1 consists of a microprocessor, etc.
It is the CPU. Although not shown in the figure, external operation signals such as an external switch or key switch are supplied to this CPU, and information on what kind of musical tone should be generated (specifying scale, timbre, etc.) is sent to the LSI ( large-scale integrated circuit)
Supplied to L1 and L2. The LSIs L1 and L2 each have a one-chip configuration. Furthermore, the chip select signal C of LSI L1 and L2 is sent from CPU1.
1/C2 is supplied via the respective terminal CS. Note that LSI L2 has the above chip select signal C.
1/C2 is inverted and supplied via the inverter 2. Therefore, this chip select signal C1/
If C2 is “1”, LSI L1 is selected,
If it is “0”, LSI L2 is selected. LSI L1 and L2 have exactly the same circuit configuration,
For example, each LSI L1 and L2 can generate musical tones of up to four chords by time-sharing processing. Various methods for generating musical tones have been developed in the past, and it goes without saying that any digital method can be applied. It is assumed that one musical tone consists of five overtones. Therefore, each LSI L1 and L2 has a function of simultaneously outputting 20 (=5 overtones x 4 chords) sine waves. Data from LSI L2, that is, amplitude information of musical tones and envelope information, are serially transferred to LSI L1 via lines _l1 and _l2 , respectively. That is, this line l ₁ ,
l ₂ is a bidirectional line, but each LSI L1, L
If a "1" signal is given to the master/slave terminal M/S of 2, that LSI will function as a master, and if a "0" signal is given, that LSI will function as a slave. LSI set as master LSI set as slave
The data in L2 is transferred and combined with the data generated in LSI L1. Therefore, from LSI L1, for example, 16-bit amplitude data (up to a maximum of 8 chords, in other words, data obtained by synthesizing up to 40 sine waves) is generated based on the envelope data as described later. The bits are shifted and output from terminals _D0 to _D15 . Furthermore, 2-bit data for determining the amplification factor is output from the LSI L1 via terminals S ₀ and S ₁ . The digital information output from the terminals D ₀ to _{D 15} is converted into a voltage signal by the DA converter 3, and the signal is supplied to the amplifier 4, where it is amplified and output at a set amplification factor. That will happen. Next, the detailed configuration of the main parts of LSI L1 (LSI L2 is also the same) will be explained with reference to FIG. Note that the positions of the terminals in FIG. 2 and the terminals in FIG. 1 do not correspond in some parts. Therefore, in LSI L1, amplitude information of musical tones up to four chords (addition value of envelope-controlled amplitude information up to a maximum of four chords) d ₀ to _{d 14} is generated by time-sharing processing, and transfer gates G ₁ to G given to ₁₅ . Note that a "0" signal is always applied to the transfer gate _G16 . The transfer gates _G1 - _G16 are opened by a timing signal _t15 , which will be described later, and their output signals are applied to the latches 11-26. Therefore, each amplitude value of a musical tone is obtained by performing processing to change it at every timing _t15 . These latches 11 to 26 are connected to the clock _φ1 (described later).
The reading operation is performed at the above timing signal _t15 .
When the signal becomes "1", the output signals of the transfer gates _G1 to _G16 are read as described above, but at other timings, that is, from _t0 to _t14 , the latches 12 to 12 on the upper bit side are read. The output of the full adder 26 and the addition output of the full adder 27 are read through transfer gates _G17 to _G32 , respectively. That is, the timing signal t ₁₅ is inverted and supplied as a gate signal to the transfer gates G ₁₇ to _{G 32} via the inverter 28, so that the timing signal t ₀ to G 32 is inverted and supplied to the transfer gates G 17 to G 32 .
At t ₁₄ , transfer gates G ₁₇ to _{G 32} will be opened. The full adder 27 has the output of the latch 11.
DO is applied to the B input terminal, and serial data supplied from LSI L2 input from the data input terminal DATA (connected to line _l1 ) is applied to the A input terminal via the AND gate 29. ing. If this AND gate 29 is set as a master, a "1" signal is applied to one end and the gate is opened, but if it is set as a slave, a "0" signal is applied to one end and the AND gate 29 is closed. Therefore, in this LSI L1, the output of LSI L2 is supplied to the full adder 27 via the AND gate 29. On the other hand, in LSI L2, the corresponding AND gate 29 is closed. However, since the master/slave signal inverted by the inverter 30 is supplied to the transfer gate _G33 , the transfer gate _G33 is opened and the output DO of the latch 11 is connected to the terminal.
It will be output via DATA. Note that one input terminal of the AND gate 29 and the input terminal of the transfer gate _G33 are connected to a resistor _R1 .
It is set to the ground level (“0” level) via. So, the terminal connected to line l ₁
DATA is used as an input terminal in LSI L1.
In L2, the function is set as an output terminal. Therefore, in the full adder 27 in LSI L1,
Musical tone information generated in LSI L1 and LSI L2
and the musical tone information generated within the circuit are serially added bit by bit and applied to the latch ₂₆ via the transfer gate G32. In addition, the carry output terminal of Full Adder 27
A carry signal is output from COUT and applied to latch 32 via AND gate 31. Note that this AND gate 31 includes an inverter 28
The output signal is supplied, and the timing t ₀ to _{t 14}
At , the AND gate 31 is opened. The latch 32 performs a read operation at the clock _φ1 , and its output is applied to the carry input terminal CIN of the full adder 27. In this way, the musical tone information generated by LSI L1 and the musical tone information generated by LSI L2 are added by the full adder 27, and when the resulting data is latched in the latches 11 to 26, the information is is transferred and latched in parallel to the latches 33-48 at the timing of clock _φ16 (described later). The outputs of the latches 33-48 are sent to the clock φL via transfer gates _G34 - _G49 .
The latches 49 to 64 perform the reading operation (described later).
is applied to In addition, the above transfer gate
A timing signal _t15 is supplied to the gates of _G34 - _G49 , and the contents of latches 33-48 are transferred to latches 49-64 only at timing _t15 . At other timings, transfer gates G ₅₀ -G ₆₄ connected to the output terminals of latches 49 - 64 are opened, and the voltage is applied to the input terminals of latches 50 - 64 on the upper bit side, respectively. In addition, the above transfer gate G ₅₀ ~ _{G 64}
A timing signal _t15 is inverted by an inverter 65 and supplied to each gate. Therefore, the latches 33 to 4 are set by the clock φL.
The musical tone information supplied from 8 is shifted to the upper bit side as necessary, in other words, it is compressed and output to latches 66-81. The above-mentioned latches 66 to 81 perform a reading operation using the clock _φ16 , and their outputs are sent to the above-mentioned terminals _D0 to _D15.
supply to Note that the output of latch 81 corresponding to the most significant bit, ie, the sign bit, is inverted by inverter 82 and applied to output terminal _D15 . That is, the waveform calculation process is performed by two's complement calculation in this embodiment, and the latches 66 to 81 are
The maximum level (positive) is "01...1", the zero level is "0...0", and the minimum level (negative) is "10...01", but this inverter 82 provides linear output characteristics. It will be done. That is, the maximum level is "11...1", the zero level (ground level) is "10...0", and the minimum level is "00...01". Next, the envelope data synthesis circuit will be explained. In LSI L1, envelope information for up to four chords is synthesized together with the above-mentioned musical tone amplitude information and applied to transfer gates G ₆₅ to _{G 71} . For this envelope data, the original envelope data may be added as is, but only the upper bits may be added. In this example, the addition data of envelope data up to 4 chords is 7 bits. Suppose that it is expressed as (E ₀ to _{E 6} ). Although not shown, this envelope data also includes the above-mentioned musical tone amplitude information d ₀ ~
It is also used to generate _d14 , and each tone is obtained by multiplying the amplitude data of the original waveform and the envelope data at that time. Therefore, the transfer gates G ₆₅ to G ₇₁ and transfer gate G ₇₂ are provided with a timing signal.
t ₁₅ is supplied as a gate signal, and only at timing t ₁₅ the gate is opened and envelope data is supplied to latches 83-90. Note that a "0" signal is applied to the transfer gate _G72 . These latches 83 to 90 are connected to the clock _φ2 (described later).
The reading operation is performed at the above timing signal _t15 .
When the signal becomes "1", the output signals of the transfer gates _G65 to _G72 are read as described above, but at other timings, that is, from _t0 to _t14 , the latches 84 to 84 on the upper bit side are read. The output of full adder 90 and the addition output of full adder 91 are read through transfer gates _G73 to _G80 , respectively. That is, the timing signal t ₁₅ is inverted and supplied as a gate signal to the transfer gates G ₇₃ to _{G 80} via the inverter 92, and therefore the timing signal t ₀ to G 80 is
At t ₁₄ , transfer gates G ₇₃ to G ₈₀ will be opened. The full adder 91 has the output of the latch 83.
EO is applied to the B input terminal, and the envelope data input terminal ENV (line l ₂
Serial data input from the terminal (connected to the terminal) is applied via an AND gate 93. If this AND gate 93 is set as a master, a "1" signal is applied to one end and the gate is opened, but if it is set as a slave, a "0" signal is applied to one end and the AND gate 93 is closed. Therefore, in this LSI L1, the output of LSI L2 is supplied to the full adder 91 via the AND gate 93. On the other hand, in LSI L2, the corresponding AND gate 9
3 is closed. However, since the master/slave signal inverted by the inverter 94 is supplied to the transfer gate _G81 , the transfer gate
G ₈₁ is opened, and the output EO of latch 83 is connected to terminal ENV.
It will be output via . Note that one input terminal of the AND gate 93 and the input terminal of the transfer gate _G81 are connected to each other by a resistor _R2.
It is set to the ground level (“0” level) via. Therefore, the terminal ENV connected with line l ₂
is set to function as an input terminal in LSI L1 and as an output terminal in LSI L2. Therefore LSI
The full adder 91 in L1 serially adds the envelope information generated in LSI L1 and the envelope information generated in LSI L2 bit by bit, and applies the result to latch ₉₀ via transfer gate G80. In addition, the carry output terminal of Full Adder 91
A carry signal is output from COUT and applied to latch 96 via AND gate 95.
Note that this AND gate 95 includes an inverter 9
2 output signals are supplied, and the timing t ₀ ~
At t ₁₄ , AND gate 95 is opened. The latch 96 performs a read operation at the clock _φ2 , and its output is applied to the carry input terminal CIN of the full adder 91. In this way, the envelope data generated in LSI L1 and the envelope data generated in LSI L2 are added in the full adder 91, and when the resulting data is latched in the latches 83 to 90, the upper Three bits of information are latched in parallel in latches 97-99 at the timing of clock _φ16 . The outputs of latches 97-99 are input to decoder 103 directly and via inverters 100-102. Note that this decoder 103
consists of a Noah matrix circuit, and this decoder 1
Table 1 shows the relationship between the outputs of the output lines m ₁ -m ₄ , m ₅ , m ₆ of 03 and the latches 97 - 99.

[Table] In Table 1, × indicates that it may be either “0” or “1”. The outputs of the lines _m1 to _m4 are applied to one input terminal of AND gates 104 to 107. And this AND gate 104-1
07 is supplied with the outputs of the OR gates 108, 109, 110 and the timing signal _t15 . Note that this OR gate 108 has a timing signal.
The OR gate 109 is supplied with timing signals t ₀ , t _{1 ,} t ₁₅ , and the OR gate ₁₁₀ is supplied with timing signals _{t 0 , t 15} . The outputs of the AND gates 104 to 107 are supplied to the OR gate 111 and outputted as the clock φL via the AND gate 112. Note that a clock _φ1 is supplied to one end of this AND gate 112. In this way, the clock φL output through the AND gate 112 is output as shown in Table 2.

[Table] Also, lines m ₅ and m ₆ from the decoder 103
The data output through the latches 113 and 114
is read by clock _φ16 . The outputs of the latches 113 and 114 are applied to the amplifier 4 via terminals S ₀ and S ₁ to determine the amplification factor. For example, in the case of this embodiment, the amplification factors are as shown in Table 3.

[Table] Next, the operation of this embodiment will be explained. FIG. 3 shows the clock and timing signals supplied to the electronic musical instrument of this embodiment.
Writing of numbers 1 to 26 and 32 is performed using the clock _φ1 shown in FIG. 3a, and the above-mentioned latch 8
Writing of numbers 3 to 90 and 96 is performed by clock _φ2 shown in FIG. 3b. In addition to these latches, all the latches mentioned above are read out in synchronization with the clock φR shown in FIG. 3c. Each circuit _shown in _FIG .
The synthesized data of the amplitude data and the synthesized data of the envelope data of each tone are determined by timing _t15 . Therefore, at timing t ₁₅ (see FIG. 3 f), transfer gates G ₁ to G ₁₆ and G ₆₅ to G ₇₂ of both LSIs L1 and L2 are opened, and data is applied to latches 11 to 26 and 83 to 90, respectively. be done. Therefore, the data is latched in latches 11-26 at clock _φ1 , and in latches 83-90 at clock _φ2 . Then, at the next timing _t0 to _t14 , the contents of the latches 11 to 26 are sequentially supplied to the full adder ₂₇ and the transfer gate _G33 from the lower bit in synchronization with the clock φ1. The contents of bits 90 to 90 are sequentially supplied to full adder 91 and transfer gate _G81 from the least significant bit in synchronization with clock _φ2 . Therefore, in LSI L1, transfer gates G ₃₃ and G ₈₁ are closed, and AND gate 2 is closed.
On the other hand, in LSI L2, transfer gates G ₃₃ and G ₈₁ are opened, and AND gates 29 and 93 are closed. Therefore, LSI L1 full adder 27,91
is the amplitude data and envelope data serially transferred from LSI L2, and the LSI L1
The amplitude data and envelope data generated in . On the contrary, the full adders 27 and 91 of LSI L2 simply output the data supplied from each B input terminal. FIGS. 3g and 3h show changes in the data DO output from the latch 11 and changes in the data EO output from the latch 83, respectively. In this way, in LSI L1, the data obtained by adding the data of LSI L1 and the data of LSI L2 are applied to the latches 33-48, 97-99 by the clock _φ16 shown in FIG. 3d. is read into. The amplitude value data and envelope data (upper 3 bit data) read into the latches 33-48, 97-99 are held for the next cycle from _t0 to _t15 , and during that time, the musical tone data compression processing is performed. That is, as shown in Table 2 above, latch 97
Based on the 3-bit data stored in ~99,
Clock φL is output from AND gate 112. The clock is also shown in FIG. 3i. That is, no matter what the contents of the latches 97 to 99 are, the clock φL outputs at timing _t15 and latches the outputs of the latches 33 to 48, as shown in FIG. 49 to 64 are stored. After that, the output of clock φL becomes “1”
Each time, the contents of the latches 49-64 shift toward the higher bits. In other words, as can be understood from Table 2 and Figure 3 i, if the envelope value is large, that is, if the contents of latches 99 to 97 are "1xx", no shift is performed; If the content is “01×”, it is shifted by 1 bit, if it is “001”, it is shifted by 2 bits, and if it is “000”, it is shifted by 3 bits, and then the latch 4 is shifted.
9 to 64 retain their contents. Then, at clock _φ16 , latches 66 to 81 latch the resultant data shifted in accordance with the magnitude of the envelope value. At the same time, latches 113 and 114 begin to latch the 2-bit data output from lines m ₅ and m ₆ supplied from decoder 103. In this way, LSI L1 transfers the amplitude data and envelope data from LSI L2 to LSI L1.
It is combined with the amplitude data and envelope data generated in L1 and output. That is, 2-bit data representing the amplification factor obtained from the envelope data is supplied to the amplifier 4, and compressed amplitude data is supplied to the DA converter 3, where it is converted into an analog signal and then supplied to the amplifier 4. It will be done. As a result, in the amplifier 4, the amplification factors shown in Table 3 are determined based on the data from the terminals S ₀ and S ₁ and the input signal is amplified. That is, for example, as shown in FIG. 4, if the 2-bit data that determines the amplification factor is "0, 0", in other words, if the clock φL outputs four times from _t0 to _t15 , the amplification factor is will be output as 1x. Therefore, when the level of the signal output from the DA converter 3 fluctuates as shown in FIG. 4a, the "0, 0" section shown in FIG. 4b changes to the level as shown in FIG. 4c. The signal will be output from the amplifier 4. Then, the output level gradually increases, and the above
When the bit data becomes "0, 1", in other words, when the clock φL outputs three times from _t0 to _t15 , the amplification factor is doubled. Therefore, the section "0, 1" shown in FIG. 4b is D-
The output of the A converter 3 will be amplified and output at twice the level. Similarly, each time the amplification factor changes, D-
The range of the A converter 3 begins to change, and its correction, ie, expansion, begins to occur. Conversely, it goes without saying that control is performed in exactly the same way when the volume gradually decreases. Therefore, in the case of this embodiment, two LSI L1,
The synthesized musical tone output of L2 is compressed and expanded by the sum of the envelope data, and is output as a musical tone signal. Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, the LSIs operating under the control of the CPU 201 are LSIs L3, L4, and L5.
The configuration of each LSI L3 to L5 is exactly the same, and the LSI in the first embodiment is
It is the same as L1 and L2. This LSI L3 functions to generate melody tones of up to 4 chords, and LSI L4 functions to generate melody tones or accompaniment tones of up to 4 chords by switching the control signal AUTO/MN.
L5 functions to generate one bass tone.
Although LSI L5 has the ability to generate up to four chords, it is designed to output only one bass note. Then, from CPU201 to these LSI L3~
A control signal is commonly supplied to L5 via control bus C2. Then, when the chip select signals C1 to C3 become "1", the chip in question is selected. The control signal AUTO/MN is supplied to the master/slave terminal M/S of LSI L4, and
AND gate 203 via inverter 202,
204. Then, musical tone information is sent from LSI L4 to AND gate 2 via terminal DATA.
03 and the envelope data is applied to the terminal
Applied to AND gate 204 via ENV. And the output of AND gate 203 is LSI
Connected to terminal DATA of L3, and gate 2
The output of LSI L3 is connected to the terminal ENV of LSI L3. Also, terminals DATA and ENV of LSI L4 and L5 are connected. Then, a "0" signal is supplied to the master/slave terminal M/S of LSI L5. Therefore, this LSI L5 always sends data to the LSI
It is set to forward to L4. Further, a "1" signal is always supplied to the master/slave terminal M/S of LSI L3. Therefore, this LSI L3 always uses AND gate 203,
204 , the amplitude information is compressed and output to the DA converter 205 , and the output of this DA converter 205 is Amplifier 2 is supplied with
06, 2-bit data that determines the amplification factor is output from terminals S ₀ and S ₁ . Similarly, from LSI L4, DA converter 207
Amplitude data is supplied to the LSI L4, and the output thereof is amplified by an amplification factor determined by the 2-bit data supplied from the LSI L4 in the amplifier 208 and then output. Furthermore, the LSI L3 directly connects the sample/hold circuit 209 to the sample/hold circuit 210.
A sampling clock is supplied from the terminal S/H CLK via the AND gate 211. This sample/hold circuit 209, 21
0 is provided to prevent glitches in the DA conversion output, and the sample/hold circuit 209
The sample/hold circuit 210 samples and holds the output of the amplifier 206 and outputs it as a melody sound, and the sample/hold circuit 210 samples and holds the output of the amplifier 208 and outputs it as an accompaniment sound (including bass sound).
Note that the sampling clock is supplied to the sample/hold circuit 210 only when the control signal AUTO/MN applied to the AND gate 211 is "1". Next, the operation of this embodiment will be explained. Fourth
The table shows how the functions of LSIs L3 to L5 are set depending on whether the control signal AUTO/MN is "0" or "1".

[Table] As can be understood from this Table 4, the control signal
If AUTO/MN is “0”, the data of LSI L4 is transferred to LSI L3, and from this LSI L3
It will be output as a chord melody sound. In this case, LSI L5 is set so that the CPU 201 does not generate any musical tones. Therefore, the CPU 201 allocates musical tones corresponding to, for example, the eight keys being pressed to either LSI L3 or L4 and generates them. Note that since the signal for opening the gate is not supplied to the AND gate 211, the sample/hold circuit 210 does not operate, and no accompaniment sound is output. On the other hand, if the control signal AUTO/MN is "1", the data indicating the bass sound of LSI L5 is
LSI L4 combines the data generated in LSI L4 with the data transferred from LSI L5 and outputs the result. Also,
In this case, since AND gates 203 and 204 are closed, only melody tones of up to four chords are output from LSI L3. Therefore, the musical tones corresponding to the melody keys up to 4 tones are assigned to LSI L3 for generation and output, and the musical tones corresponding to the accompaniment keys up to 4 tones are assigned to LSI L4 for generation and output, and also correspond to the bass key. The musical tone to be played or the musical tone (auto bass tone) automatically selected and specified by the operation of the accompaniment key is assigned to LSI L5 and generated and output. Note that information regarding the tone to be used to generate musical tones is stored in the LSIs L3 to L5 by the CPU 20.
Since each LSI L3 to L5 can generate musical tones according to the information, it is possible to make the tones of the melody tone, accompaniment tone, and bass tone different. Although not shown in FIG. 5, when the melody tone and the accompaniment tone including the bass tone are output as two series of musical tones, the sample/hold circuit 20
In addition to being able to independently control the volume of the 9,210 output, it is also possible to independently apply filters with different characteristics using an external tone filter. In this way, in the case of this embodiment, a 3-chip LSI
By simply providing L3 to L5, it is possible to generate up to 8 chords of melody tones of the same tone, as well as 4-chord melody tones, 4-chord accompaniment tones, and 1-tone bass tone. In the above embodiment, up to four chords can be generated by one LSI through time-sharing processing, but it goes without saying that the number of chords can be changed as appropriate. Further, the data transfer method between LSIs can be performed in parallel, in addition to the serial method described above. Furthermore, in the above embodiment, each LSI is provided with a data terminal that can be input/output and a synthesis circuit.
Has only a dedicated input or output circuit
Of course, the LSI may be configured separately. Further, in the above embodiment, data can be transferred between two chips and the data can be synthesized, but data can be transferred between even more chips. In that case, in addition to a method of increasing hardware and performing parallel synthesis, a method of increasing the processing time and performing serial synthesis may be available. Furthermore, in the embodiment described above, the musical tone generation circuit is constructed from one chip of LSI, and a plurality of chips are used in combination, so that LSIs can be mass-produced, and therefore costs can be particularly reduced. In addition, the circuit for data transfer, the circuit for compression/expansion, etc. can be modified and applied in various ways without departing from the gist of the present invention. As described in detail above, the present invention provides a plurality of musical tone generating means capable of generating digital musical tone information for a plurality of tones by time-sharing processing, and at least one specific musical tone generating means among them is configured to generate digital musical tone information for a plurality of tones by time-sharing processing. a first synthesizing means for synthesizing the digital envelope information generated by the digital envelope information generated by at least one other musical tone generating means and transferred as data; A second synthesizing means synthesizes the digital musical tone information generated by at least one musical tone generating means and transferred data, and a second synthesizing means using the synthesis envelope information obtained by the synthesis by the first synthesizing means. a digital-to-analog converter that bit-shifts the synthesized musical tone information according to the shift level set by the setting means and is connected to the specific musical tone generating means; and a control means for supplying a signal to the digital-to-analog converter connected to the specific musical tone generating means, at an amplification level based on the shift level set by the setting means. Since we have provided a compression/decompression device for a digital electronic musical instrument that amplifies the output musical tone signal of the digital-to-analog converter, the digital-to-analog converter is always given valid data, and moreover, the digital to analog converter has a small number of bits. The analog converter has a wide dynamic range and can provide high quality musical tone signals. Furthermore, since the compression/expansion processing of the synthesized musical tone information is performed as described above according to the synthesis envelope information, the number of times the compression/expansion processing is switched can be reduced and the generation of noise can be prevented. Problems caused by modulation can be solved. Furthermore, it is no longer necessary to provide a separate digital-to-analog converter for each of the plurality of musical tone generation means, which simplifies the circuit. Musical tone signals from the means can be synthesized and output, resulting in good performance effects.

[Brief explanation of the drawing]

1 to 4 show a first embodiment of the present invention, FIG. 1 is a circuit block diagram of the embodiment, FIG. 2 is a detailed view of the main part of the embodiment, and FIG. 3 is an implementation of the same embodiment. The time chart of the example, FIG. 4, is a diagram showing changes in the output volume of the same embodiment, and FIG. 5 is a circuit block diagram showing the second embodiment of the present invention. 1,201...CPU, 3,205,207...
...D-A converter, 27,91...Full adder, 9
7-99...Latch, 103...Decoder, 49
~64...Latch, L1~L5...LSI, 4,2
06,208...Amplifier.

Claims (1)

[Claims] 1. A plurality of musical tone generation means, each of which generates digital musical tone information for a plurality of tones subjected to envelope control based on digital envelope information through time-sharing processing of a plurality of channels. In a digital electronic musical instrument, the synthesized musical tone information obtained by synthesizing the generated and outputted plurality of digital musical tone information is converted into analog by a digital-to-analog converter and outputted as a musical tone signal, and the plurality of musical tones are generated. At least one specific musical tone generating means of the means is configured to transmit digital envelope information generated by the specific musical tone generating means and data generated by at least one other musical tone generating means to the specific musical tone generating means. a first synthesizing means for synthesizing the digital envelope information generated by the digital envelope information; a first synthesizing means for synthesizing the digital musical tone information generated by the specific musical tone generating means; and a first synthesizing means for synthesizing the digital musical tone information generated by the particular musical tone generating means; a second synthesis means for synthesizing the digital musical tone information data transferred to the means; and synthesis envelope information obtained by synthesis by the first synthesis means; a setting means for setting a shift level of the synthesized musical tone information; and a setting means for bit-shifting the synthesized musical tone information according to the shift level set by the setting means, and a digital-to-analog converter connected to the specific musical tone generating means. and a control means for supplying an amplification means connected to the digital-to-analog converter, the setting means controlling the output of the digital-to-analog converter at an amplification level set in accordance with the shift level. A compression/expansion device for a digital electronic musical instrument, characterized in that it amplifies a musical tone signal.