JP3180351B2 - Effect device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to perform basic effect processing with an inexpensive system, and to add (expand) a delay memory or to use a large-capacity delay memory in a multifunction system. The present invention relates to an effect device capable of executing various effect processing.

[0002]

2. Description of the Related Art Conventionally, in the field of electronic musical instruments, effects (effects) such as a reverb effect and a chorus effect have been added to a tone signal generated from a sound source. As a configuration for adding this effect, recently, a DSP (Digital Signal Processor) is often used.

[0003] Such an effect device is currently divided into a high-function device and a low-function device, and each is generally constituted by a separate system. For this reason, one DSP LSI for effect cannot cover from low-grade to high-end, and it is necessary to make separate LSIs for effect.

[0004] Also, when an effector is built into the sound source LSI of an electronic musical instrument, or when electronic musical instruments of various price ranges are made with the same sound source LSI system, a low-grade device is a built-in effector and a high-end device is an external effector. There is a drawback that the electronic musical instrument needs to be separated and the system configuration as an electronic musical instrument becomes complicated.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and it is an object of the present invention to provide an effect device which can easily cope with the construction of a system in various price ranges.

[0006]

In order to achieve the above object, the present invention provides a microprogram storage means for storing a microprogram for effect processing, and an effect processing in accordance with the microprogram stored in the microprogram storage means. Arithmetic means for sequentially performing digital signal processing arithmetic for the following, delay storing means for delay processing accessed by the arithmetic means, the arithmetic means and the delay
If the data bus of the storage means has the same length, the first
Mode, and the data of the arithmetic
If the data bus is longer than the data bus, set the second mode.
When the mode setting means and the calculating means access the delay storing means , the mode setting means sets the delay storing means in one calculation cycle of the calculating means in the first mode. Access means for accessing the delay storage means a plurality of times within one operation cycle of the operation means in the second operation mode in the second mode ;
An effect device comprising:

According to such a configuration, the computing means can execute the effect processing according to the capacity of the delay storage means. That is, for example, a high-end machine is equipped with a large-capacity delay storage means, and the arithmetic means accesses such a delay storage means at high speed (the data of the arithmetic means and the data bus of the delay storage means). For low-grade machines, small-capacity delay storage means are mounted, and the arithmetic means multiplexes and accesses such delay storage means a plurality of times within one operation cycle (operation means Is longer than the data bus of the delay storage means).

As a more specific example, the microprogram storage means stores a microprogram in which execution instructions in one sampling period are expressed by different numbers of steps, and the mode setting means includes the arithmetic means.
Is a microprogram executed within one sampling period.
If the number of ram steps is equal to or greater than a predetermined value, the first
Set to mode and execute within the above one sampling period
If the number of microprogram steps is less than the specified value
In this case, the second mode is set.

According to such a configuration, one sampling
Set the mode according to the number of steps of the execution instruction in the cycle
This makes it possible to change the capacity of the delay storage means in accordance with the setting mode in a manner corresponding to the complexity of the microprogram. Therefore, for example, in a high-end machine, high-speed and complicated digital signal processing is executed while accessing a large-capacity delay storage means to generate an effect sound. The digital signal processing can be executed while accessing the small-capacity delay storage means to generate an effect sound.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment to which the present invention is applied will be described below in detail.

<Structure> FIG. 1 shows a tone generator (sound generator LSI) having a one-chip structure.
1 shows an overall configuration of an electronic musical instrument configured by using a CPU. This C
The keyboard 2 and the switch 3 are connected to the PU 1, and key information and switch information are captured by scanning. And CP
A sound source LSI 4 is connected to U 1, and tone generation control information, tone color information, and the like are transferred from the CPU 1 to the sound source LSI 4.

As will be described later, the tone generator LSI 4 has a one-chip configuration of a waveform generating circuit and a DSP unit. As the waveform generating circuit, various sound source systems such as a PCM system, an iPD system, and an FM system can be adopted. In this embodiment, the PCM system is used.

That is, the tone generator LSI 4 sends an address signal through the terminal PAD to access the PCMROM 5 in which data representing a musical tone waveform is stored.
The M waveform data is fetched via a terminal PDT, an envelope is added thereto by an internal circuit, and then sent to an internal DSP unit for adding a desired effect to a tone waveform signal. The DSP unit accesses the delay RAM 6 and executes an effect operation. An address signal is sent from the sound source LSI 4 to the RAM 6 via the terminal DAD, and exchanges waveform data with the sound source LSI 4 via the terminal DDT.

The waveform data to which the effect has been applied from the tone generator LSI 4 is supplied to the DAC E via the terminal EOUT.
(Digital-to-analog converter) 7 and further amplified by amplifiers 8A and 8B, and then output in stereo via speakers 9A and 9B.

FIG. 2 shows an example of a specific block circuit configuration of the tone generator LSI 4. Reference numeral 11 denotes a CPU interface.
Asynchronous control data from PU1 is received at terminal IN, and control data is distributed to each circuit block from terminal OUT at a timing synchronized with the internal circuit operation of tone generator LSI4.

The waveform generating circuit 12, which is connected to the CPU interface 11 and determines the characteristics (tone pitch, tone color, volume, envelope, etc.) of the musical tone to be generated, in accordance with the data supplied from the terminal IN, outputs the above-described PCM signal. R
An address signal for accessing OM5 is supplied to terminal Add.
And sent to the terminal PAD of the sound source LSI4. Then, the waveform data supplied from the terminal PDT of the sound source LSI 4 is supplied to the inside of the waveform generation circuit 12 via the terminal Data, subjected to processing such as envelope processing, and then sent to the DSP unit 10 via the terminal Wout. In this embodiment, the waveform generating circuit 12 generates a plurality of musical tone waveform signals in a time-division manner by time-division processing, and these signals are appropriately synthesized and supplied to the DSP unit 10.

The DSP unit 10 includes a CPU interface 1
The effect processing is realized by digital signal processing in accordance with control information supplied from 1 to the terminal IN. That is, the DSP unit 10 can independently execute arbitrary effect processing on the combined waveform data of each group using the microprogram given from the CPU 1 and various coefficient data. The terminal Add of the DSP unit 10 is connected to the terminal DAD of the sound source LSI 4 to access the RAM 6 for delay, and data is exchanged between the terminal DDT of the sound source LSI 4 and the terminal D of the DSP unit 10.
Performed via “ata”.

The output terminal EWou of the DSP unit 10
From t, the tone waveform signal subjected to the effect processing is output and sent to the output terminal EOUT of the sound source LSI 4.

FIG. 3 shows a block circuit configuration of the DSP unit 10. The DSP unit 10 uses a given mode signal a for a high-end device (mode signal a = 0, called mode 1; It is a bit bus, which performs 128 steps (operation cycle) of operation within one sampling period. It is for a low-grade machine (mode 2 with mode signal a = 1, the delay RAM 6 is an 8-bit bus, and
A 64-step calculation is performed within the sampling period. 2) is selectively performed.

The counter 101 operates in response to a system clock φ at a terminal CK. The lower 7 bits of the output are sent to an input terminal I of a shifter 102 and shifted by a mode signal a given to a terminal S. Is supplied to the terminal ADR of the microprogram memory 103 as an address signal. In other words, this shifter 10
The 7-bit signal output from 2 specifies each operation cycle of digital signal processing. Specifically, the shifter 10
No. 2 performs no shift operation in mode 1, so
The lower 7 bits of the counter 101 directly specify the steps of 0 to 127. In the mode 2, the counter 101 shifts to the lower bit by 1 bit and sets “0” to the most significant bit MSB.
After all, the shifter 102 specifies the steps 0 to 63 within one sampling period.

The mode signal a is supplied from the CPU 1 via the CPU interface 11 or by applying a voltage level corresponding to a specific terminal of the tone generator LSI 4.

The upper 15 bits of the counter 101 are used as a delay RAM 6 for effects (32K × 16 bits in mode 1 and 32K × 16 bits in mode 2).
8 bits).

The microprogram memory 103 receives the output of the shifter 102 and outputs from a terminal MP 24-bit microprogram data (microinsulation) for controlling digital operations performed by the DSP 105. The mode signal a is input to the mode terminal MODE of the microprogram memory 103, and the number of steps differs between mode 1 and mode 2 (128 steps in mode 1).
The microinstruction of (step, mode 2, 64 steps) is output.

The microprogram memory 103
Is a RAM, and a microprogram having a different number of steps is
Writing can be made via the U interface 11. In that case, the delay RAM offset memory 1
11 is also a RAM, and the CPU 1 writes a set of necessary offset data. Also, various coefficients and the like can be written, but the connection configuration for that is omitted in FIG.

The DSP 105 receives the microprogram data, executes corresponding digital signal processing, generates desired effect data EWout from data EWin input via the terminal IN, and outputs the desired effect data EWout from the terminal OUT. An operation clock (system clock) is supplied to the terminal CLK of the DSP 105 via the selector 104. The selector 104 provides the inverter 11 with a logical inversion of the system clock φ and a clock φ1 (a least significant bit LSB output of the counter 101) obtained by dividing the system clock φ.
The clock bar φ1 taken at 3 is supplied to the input terminals A and B, and is selectively output from the output terminal Y by the mode signal a supplied to the terminal S. Specifically, the mode signal a
Is 0 (mode 1), the clock φ is selectively output, and when the mode signal a is 1 (mode 2), the clock bar φ1 is selectively output. Accordingly, the DSP 105 has a two-to-one relationship between the operation speed in the mode 1 and the operation speed in the mode 2, and executes the operation at a higher speed in the mode 1.

In this embodiment, the DSP 105 inputs and outputs data in 16 bits in both mode 1 and mode 2, and writes / reads data to / from the delay RAM 6.

Specifically, at the time of writing, in the 16-bit data output from the terminal DOUT of the DSP 105, the upper 8 bits directly or pass through the terminal B of the selector 106, and the lower 8 bits pass through the terminal A of the selector 106. , And to the RAM 6 via the buffer 108 (RA
M6 includes 16-bit data in mode 1, mode 2
In this case, data is supplied and stored in the form of 8-bit data). The opening and closing operation of the buffer 108 is based on micro instructions from the micro program memory 103.

The selector 106 has input terminals A and B.
A control signal is supplied to the terminal S from the AND gate 107 to control which of the data supplied to the terminal Y is output from the terminal Y. That is, the selector 106 selectively outputs the input to the terminal A when the control signal applied to the terminal S is “0”, and selectively outputs the input to the terminal B when the control signal is “1”. The AND gate 107 is supplied with the above-mentioned clock bar φ1 and the mode signal “a”, and the logical product of them is taken as the control signal. This selector 10
The specific operation of No. 6 will be further described later.

At the time of reading, data from the RAM 6 (16-bit data in mode 1; mode 2
Is converted to 16-bit data by the operation of the selector 109 and the flip-flop (FF) 110, and the data input terminal DI of the DSP 105
N.

That is, the lower 8 bits of the data supplied from the terminal Data are supplied to the DSP 105 directly or through the FF 110 via the terminal B of the selector, and the upper 8 bits are supplied to the terminal A of the selector 109 via the terminal A of the selector 109.
Provided to P105. Then, a clock φ1 is supplied to the FF 110 as a read clock. Also,
The mode signal a is supplied to the terminal S of the selector 109,
When the mode signal a is "0", data supplied to the terminal A is output from the terminal Y, and when the mode signal a is "1", data supplied from the terminal B is output from the terminal Y. The 8-bit data output from this terminal Y is
5 becomes the upper 8 bits of the 16-bit data supplied to. The operations of the selector 109 and the FF 110 will also be described later in detail.

The delay RAM 6 stores RA for delay processing.
M is used as a substitute for the shift register. The upper 15 bits of the counter 101 are used as a cyclic address, and offset data representing the input / output position of the shift register is added thereto to obtain address data. That is, the delay RAM offset memory 107
Is a shifter 10 receiving the lower 7 bits of the counter 101.
The 7-bit data from 2 is input to the input terminal ADR, and 15-bit offset data corresponding to this value is sent from the output terminal O to the A terminal of the adder 112.
Upper 15-bit data given from 1 (B terminal input)
After that, the address data (S terminal output) of 15 bits is obtained. Then, the clock φ1 which is the least significant bit output of the counter 101 is added to the least significant bit of the 15-bit data, and the data becomes 16-bit address data. The mode signal a is also given to the terminal MODE of the delay RAM offset memory 111, and different offset data is output for each mode as the DSP 105 executes different digital signal processing in mode 1 and mode 2. I do.

<Operation> Next, the operation of this embodiment will be described with particular reference to FIG.

[0033]Mode 1  First, when the mode is 1, that is, as the delay RAM 6,
And a 32K × 16 bit RAM is connected,
SP105 performs high-speed operation in accordance with system clock φ.
Will be described. At this time one sample
According to a 128-step microprogram within the
Perform the processing that was performed.

That is, in the mode 1, the mode signal a is set to "0" and the shifter 102, the microprogram memory 103, the selectors 104 and 109, the AND gate 107, and the delay RAM offset memory 11 shown in FIG.
1 is supplied.

Therefore, the microprogram memory 103
4 are supplied with address signals 0 to 127 as shown in FIG. Then, corresponding to this, the microinstruction is supplied to the DSP 105.
The DSP 105 can output 16-bit data from the terminal DOUT once per operation cycle or input from the terminal DIN.

At this time, since "0" is given to each terminal S of the selectors 106 and 109, the input of the terminal A is output via the terminal Y. Specifically, when data is output from the DSP 105, the upper 8 bits of the 16-bit data are directly supplied to the buffer 108 through the terminal A of the selector 106, and then the 16 bits are stored in the RAM 6. Stored as data. Also,
When 16-bit data is supplied from the RAM 6 to the DSP 105, the lower 8 bits are directly supplied to the DSP 105, and the upper 8 bits are supplied to the terminal A of the selector 109.
Through the DSP 105.

Note that the address of the RAM 6 is the counter 1
The cyclic output of the lower 7 bits of 01 is added to the offset data from the delay RAM offset memory 111 and supplied. At this time, the clock φ1 is added to the least significant bit LSB to become an address signal.
In this case, the upper 15 bits are actually used as the address.

[0038]Mode 2  Next, when the mode is 2, that is, as the delay RAM 6,
And a 32K × 8 bit RAM is connected (16
It is connected to the lower 8 bit lines of the bit bus. ), D
SP105 performs low-speed operation on system clock bar φ1
(Refer to the DSP 105 clock in FIG. 4).
The case will be described. At this time, within one sampling cycle
Performs processing according to a 64-step microprogram.
Run.

That is, in the mode 2, the mode signal a is set to "1" and the shifter 102, the microprogram memory 103, the selectors 104 and 109, the AND gate 107, and the delay RAM offset memory 11 shown in FIG.
1 is supplied.

Therefore, the microprogram memory 103
4, address signals 0 to 63 are supplied by the operation of the shifter 102 as shown in FIG. And the micro instruction corresponding to this is DS
It is supplied to P105. The DSP 105 can output 16-bit data from the terminal DOUT once per operation cycle or input from the terminal DIN.
However, since the connected RAM 6 relies on an 8-bit data bus, 16-bit data is multiplexed into 8-bit data, and conversely, 8-bit data is converted into 1-bit data.
It is necessary to demultiplex the data into 6-bit data.

Therefore, first, when data is stored in the RAM 6 from the DSP 105, the terminal DOUT of the DSP 105
Out of the 16-bit data, the upper 8-bit data is supplied via the terminal B of the selector 106 (because the clock bar φ1 is given to the terminal S of the selector 106), as shown in FIG. It is supplied to the RAM 6. In the latter half of one operation cycle, the lower 8 bits are supplied via the terminal A of the selector 106. And RAM6
Is given two address signals in one operation cycle (because the clock φ1 is the least significant bit of the address data), so that the 16-bit data output from the DSP 105 eventually becomes the upper eight bits, They will be stored in the order of the lower bits.

Conversely, when 16-bit data is multiplexed from the RAM 6 and supplied as two 8-bit data, the upper 8-bit data is first sent to the FF 110 at the timing of the first half of one operation cycle as shown in FIG. , That is, latched by the clock φ1. Then, the upper 8-bit data is supplied to the terminal DIN of the DSP 105 via the terminal B of the selector. The lower 8-bit data is directly supplied to the terminal D of the DSP 105 at the latter half of one operation cycle.
Supplied to IN. Accordingly, the DSP 105 converts the demultiplexed 16-bit data in FIG.
As shown in the figure, the data is taken in at the timing of the clock bar φ1.

Note that the address of the RAM 6 is the counter 1
The cyclic output of the lower 7 bits of 01 is added to the offset data from the delay RAM offset memory 111 and supplied. At this time, the clock φ1 is added to the least significant bit LSB to become an address signal, and in mode 2, the lower 15 bits are actually used as an address.

According to the embodiment described above, the delay RA
Since the read / write access of the M6 is selectively executed in a mode of 16 bits × 1 time or 8 bits × 2 times, both the high-performance effect device and the low-performance effect device use one DSP 105. realizable.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, the DSP unit 10 is provided inside the sound source LSI. However, the DSP unit may have an LSI configuration separate from the waveform generating circuit.

In the above-described embodiment, two access modes of the delay RAM 6 can be obtained. However, the delay RAM 6 may be obtained by switching to more stages. For example, once (16 bits x 1) and twice (8
It is also possible to selectively adopt three-stage multiplexed access of (bit × 2 times) and 4 times (4 bits × 4 times).

Further, in the above embodiment, one of the DSPs 105
The number of processing steps in the sampling cycle was changed in accordance with the size of the connected delay RAM,
It is not necessary. Further, the number of steps of the microprogram executed within one sampling period is not limited to 128 steps and 64 steps as in the above embodiment.

[0048]

According to the first aspect of the present invention, the effect processing according to the capacity of the delay storage means can be executed by the calculation means.
Accordingly, one signal processing circuit (such as a DSP) can be applied when implementing effect devices in various price ranges.

According to the second aspect of the present invention, the capacity of the delay storage means can be changed in a manner corresponding to the complexity of the microprogram.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an entire configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a sound source LSI in the circuit of FIG.

FIG. 3 is a circuit diagram showing a specific configuration of a DSP unit in FIG. 2;

FIG. 4 is a diagram showing a time chart of input / output processing to / from a delay RAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU, 4 ... Sound source LSI, 5 ... PCM ROM, 6 ... RAM, 10 ... DSP part, 12 ... Waveform generation circuit, 101 ... Counter, 103 ... -Microprogram memory, 105 ... DSP, 106, 109 ... selector, 111 ... delay RAM offset memory.

Claims (2)

(57) [Claims] 1. Microprogram storage means for storing a microprogram for effect processing, and arithmetic means for sequentially performing digital signal processing for effect processing in accordance with the microprogram stored in the microprogram storage means. The delay storage means for delay processing accessed by the arithmetic means, and the data bus of the arithmetic means and the delay storage means are equal.
If the length is new, set the first mode and
The data of the stage is longer than the data bus of the delay storage means.
In the case, the mode setting means for setting the second mode and the arithmetic means access the delay storage means . In the first mode , the mode setting means sets the delay mode within one arithmetic cycle of the arithmetic means . One access to storage means
And an access unit for multiplexing and accessing the delay storage unit a plurality of times within one operation cycle of the operation unit in the second mode . 2. The microprogram storage means comprises:
Executing instructions in the sampling period is storing micro programs expressed in different number of steps, the mode setting means, said computing means the 1 sampling
Number of microprogram steps executed within the switching cycle
Is greater than or equal to a predetermined value, the mode is set to the first mode,
Microprogram executed within one sampling period
If the number of steps in the program is less than the predetermined value, the second mode
The effect device according to claim 1, wherein the effect device is set to a mode.