JPH11203129A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of microprogram memory. SOLUTION: A microprogram supplying part 20 outputs a microinstruction to each processing part in every step. Access to an external RAM 14 which delays musical sound waveform data is carried out at a step that corresponds to a multiple of a prescribed integer (n)and a micro code for an external RAM access circuit 32 is supplied through a shift register which performs serial- parallel conversion of micro codes for (n) steps and outputs them. Thus, it is possible to reduce the bit number of a field for the circuit 32 to one in the microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (DSP: Digital
l Signal Processor).

[0002]

2. Description of the Related Art DSPs capable of performing high-precision and high-stability real-time signal processing such as filter operation and modulation / demodulation operation by algebraic operation of digital values are widely used for processing audio signals and video signals and processing audio information. Used in the field of In a tone generator such as an electronic musical instrument, a DSP is used as an effector for adding a predetermined effect to a generated tone. Such processing in electronic musical instruments is always a sampling cycle (DAC cycle)
A DSP suitable for such a case has been proposed by the present applicant (JP-A-5-150977).

According to the DSP proposed by the present applicant, a microprogram is described by a fixed number of steps, and all the steps of the microprogram are sequentially read out and processed in one sampling cycle. Therefore, the microprogram is always executed at a predetermined cycle, real-time signal processing is guaranteed, and the execution time of the program can be easily grasped at the program creation stage.

[0004]

In accordance with recent advances in semiconductor technology, the tone generator and the above-mentioned DSP must be integrated on a single semiconductor chip, or the tone generator, the DSP and the central processing unit (CPU) must be integrated. Are integrated. In such a case, reducing the size of the semiconductor chip is required for cost reduction,
It is desired to reduce the size of an area for storing a microprogram in a DSP.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the amount of hardware by saving the capacity of a memory for storing a microprogram and to reduce the cost in a digital signal processing device under the control of a microprogram.

[0006]

In order to achieve the above object, a digital signal processing device according to the present invention comprises a microprogram memory for storing a microprogram, and a microinstruction read from the microprogram memory for each step. Serial-to-parallel conversion means for sequentially storing a part of the fields and outputting in parallel at each predetermined step, and processing controlled by the parallelized microcode output from the serial-to-parallel conversion means at each predetermined step And a part. Further, some of the fields are fields for controlling access to an external memory.

For a predetermined field such as a field for controlling access to an external memory in the microcode, the execution of the process is performed at a predetermined time interval, and the microcode stored in each step is executed. Are parallelized using a serial / parallel conversion means, and microcodes obtained by parallelizing microcodes for a plurality of steps are supplied to the processing unit. As a result, the bit length of the microcode in each step can be reduced, and the capacity of control storage can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a digital signal processor (DSP) of the present invention, an electronic musical instrument as an example of an apparatus using the DSP will be described with reference to FIG. In FIG. 4, reference numeral 1 denotes a CPU that controls the overall operation of the electronic musical instrument, 2 denotes a timer that indicates the elapsed time during operation of the tone generator, or a timer that generates a timer interrupt at a specific interval, and 3 denotes an external MIDI device. To MIDI terminal 4
A MIDI interface circuit for receiving a MIDI message input through the MIDI instrument and outputting a MIDI message generated in the electronic musical instrument to an external MIDI device via a MIDI terminal 4 is connected to a MIDI interface circuit 5. A serial input / output circuit (serial I / O) 7 for inputting / outputting data outputs image data displayed on the panel display of the panel display and the operation unit 8 and scans a panel switch to output an operation signal. Parallel input / output circuit (Parallel I
/ O). A program memory 9 for storing a control program for controlling the operation of the CPU 1;
Reference numeral 10 denotes a work memory used by the CPU 1.

Reference numeral 11 denotes a sound source unit based on a waveform memory system, which stores a tone generator register for storing tone control data for controlling a tone generated in each tone generation channel, a frequency number parameter and a tone color parameter stored in the tone generator register. The tone signal is formed based on That is, a read address is generated for each of a plurality of tone generation channels (for example, 32 channels), and waveform sample data of each tone generation channel required for interpolation processing is read out from the waveform memory 12 based on the read address. A read-out interpolation circuit that performs interpolation processing of the waveform sample data of each sounding channel, and an EG adding unit that adds a volume envelope or the like to the waveform sample data of each sounding channel output from the reading-out interpolation circuit. . Note that the sound source section is not limited to the waveform memory type, and a sound source of another type can be used.

Reference numeral 13 denotes a DSP that mixes waveform sample data of each sounding channel to generate musical sound waveform data for each sampling period, and also applies effect processing such as chorus, reverb, variation, and the like to the musical sound waveform data. A delay memory (external RA) 14 is provided for performing a required delay by writing the musical tone waveform data and reading it after a predetermined time when an effect requiring a delay such as echo or reverb is applied.
M). Further, reference numeral 15 denotes a digital-to-analog converter (DAC) for converting musical tone waveform data output from the DSP 13 at each sampling period into an analog signal;
Is a sound system that amplifies the output of the DAC 15 and emits it as an acoustic signal. Further, reference numeral 17 denotes a CPU bus for connecting the above-mentioned units.

The operation of the electronic musical instrument configured as described above will be described. When key press information is fetched from the keyboard 6 via the serial input / output circuit 5 or when a MIDI event is generated, the CPU 1 performs channel assignment, parameter conversion, and the like according to the input performance information. The tone generator driver process is executed, and the tone generator parameters such as the converted parameters for the channels assigned by the tone generator and the sound generation start instruction (note-on) are written into the tone generator register. That is, when a note-on event is input, the CPU 1 first assigns a sounding channel so that a new tone can be generated based on the note-on event, and stores a note number, a tone color in a storage area of the channel assigned by the tone generator register. Sound source parameters such as information (memory read section) and velocity (volume information) are set. When a note-off event is input, a tone generator parameter is set in a tone generator register so that sound generation can be stopped based on the note-off event. These instructions are given by the CPU 1 executing the sound source driver processing program stored in the program memory 9.

On the other hand, the tone generator 11 executes a tone generation process. In this tone generation processing, the read interpolation circuit
Accumulate frequency information corresponding to the note number of each channel set in the tone generator register according to the time division channel timing obtained by equally dividing the sampling period,
A read address for the waveform memory 12 is created based on the accumulated value and the timbre information. Then, according to the integer part of the created read address, the waveform memory 12
, The waveform sample data required for each channel is read and stored in the buffer. As a result, the necessary number of waveform sample data for interpolating and calculating the waveform sample data according to the decimal part of the created read address is prepared in the buffer. Then, from the waveform sample data of each channel prepared in the buffer, waveform sample data interpolated according to the decimal part of the created read address is calculated.
The interpolation process is performed for each channel at the time-division channel timing.

The waveform sample data of each channel after the interpolation processing output from the read-out interpolation circuit is provided with an envelope corresponding to the volume information and the tone color information of the channel set in the tone generator register in the EG providing unit. . Further, waveform sample data of each channel to which an envelope is added is input to the DSP 13. Then, the DSP 13 mixes the waveform sample data of each channel and performs effect processing such as chorus, reverb, variation, etc., thereby generating musical sound data for each sampling cycle. If the tone data needs to be delayed during the effect processing, the DSP 13 uses the delay memory 14 as delay means by writing the tone data in a delay memory 14 provided outside thereof and reading it out after a predetermined time. ing. The tone data output from the DSP 13 at each sampling cycle is converted into an analog tone signal by the DAC 15, and the analog tone signal converted by the DAC 15 is amplified and sounded by the sound system 16.

Although not shown in FIG. 1, an analog-to-digital converter (ADC) for converting an analog signal input from an analog waveform input unit such as a microphone into digital data is provided. The voice data and the like are also input to the DSP 13,
In SP13, the sound data may be mixed with the above-mentioned tone data.

FIG. 1 is a block diagram showing an example of the internal configuration of the DSP 13. In this figure, reference numeral 20 denotes a microprogram supply unit, which has a microprogram memory (control storage) storing a microprogram therein, reads one microinstruction every clock cycle, and By supplying the microcode to the unit, a corresponding process is executed. Note that the number of steps of the microprogram stored in the microprogram memory can be arbitrarily set. Here, an example in which a microprogram consisting of 512 steps of microinstructions is stored in the microprogram memory will be described. To explain. That is, in one DAC cycle, the 51
A two-step microinstruction is executed.

A first selector 21 is a selector for selecting a tone signal input from the tone generator 11 and data on the data bus 30 and inputting them to an input / output RAM (I / ORAM) 22. 22 is an input / output RAM,
Data input through selector 21 and DAC1
5 is stored. 23 is the data bus 3
This is a temporary RAM connected to “0”, and stores an intermediate result of an operation and the like. Reference numeral 24 denotes a second selector, which receives the outputs of the input / output RAM 22 and the temporary RAM 23, selects one of the outputs, and supplies the selected output to one input of the multiplier 26.

Reference numeral 25 denotes a coefficient register and an interpolation unit.
A predetermined coefficient value used for the operation is stored, and the interpolation operation is performed when necessary. Reference numeral 26 denotes a multiplier which multiplies data input via the selector 24 with data input from the coefficient register and the interpolator 25 at high speed. Reference numeral 27 denotes a third selector, to which outputs from the input / output RAM 22, the temporary RAM 23, and the data bus 30 are input, and any one of them is selected and output to the adder 28. An adder 28 is an adder that adds the output of the selector 27 and the output of the multiplier 26. Reference numeral 29 denotes a shifter for shifting the output of the adder 28 as necessary. The output of the shifter 29 is connected to the data bus 30. Also,
An external RAM address control unit 31 controls an address when accessing the delay memory (external RAM) 14 described above, and an external RAM 32 accesses the external RAM 17 based on an address supplied from the external RAM address control unit 31. An access circuit.

In the DSP 13 configured as described above, each of the arithmetic units,
The arithmetic unit, the control unit, the gate, and the like are controlled in accordance with the microcode supplied to the control unit, the gate, and the like. The output calculation result data is calculated with the coefficient value supplied from the coefficient register and the interpolating unit 25, or is written to the external RAM 14 as necessary, read out after a predetermined time, and given a predetermined time delay. The tone signal input from the sound source unit 11 is subjected to a predetermined filter operation or a process such as reverb or chorus using a waveform delay, and the tone signal subjected to the process is converted into a DAC 15 at each sampling period. Is output to

As described above, the number of steps of the microprogram stored in the microprogram memory is set to 51.
Assuming that two steps are performed, for example, if these 512 steps are executed in a sampling cycle of 48 kHz, the time per one step is 40 nsec.
AM is required. Therefore, in order to use a slower external RAM, in the present invention, access to the external RAM is executed only in a predetermined step, for example, a step corresponding to a multiple of an integer n. Here, n can be an integer of 2 or more.

In the conventional DSP, a field for controlling access to the external RAM includes, for example, one bit for instructing writing / reading to / from the external RAM, and an index with an index for defining a mode of the write data. A field consisting of a total of 2 to 3 bits of 1 or 2 bits was specified in the option instruction. However, in the present invention, since the access to the external RAM is executed only in a predetermined step as described above, the number of bits of the field for controlling the access to the external RAM is reduced as described below. This can be reduced to one bit.

Hereinafter, this will be described with reference to a configuration example of a main part of the microprogram supply unit 20 shown in FIG. 2 and a description example of a microprogram shown in FIG. The microprogram supply unit 20 is provided with a microprogram memory as described above. This microprogram memory has a total of the 0th to 511th steps as shown in the description example of the microprogram in FIG. There are stored 512 steps of microinstructions. Each microinstruction is composed of a plurality of fields including control signals corresponding to each processing unit in the DSP 13 shown in FIG. In the example shown in FIG. 3, the first selector 21, the second selector 24, the third selector 27, the multiplier 26, the temporary RAM 23, the shifter 2
9 and only the fields corresponding to the external RAM access circuit are described.
2. Fields for the adder 28 and the like are provided. As shown in the figure, in the present invention, the field corresponding to the external RAM access circuit has a size of 1 bit.

This microprogram supply unit is provided with an address counter for counting the clock pulse Φ from 0 to 511, and is provided for each sampling period (DA
At the start of the (C cycle), counting starts from 0, and when the count value is 511, one DAC cycle ends. By the output of the address counter, the micro instruction of the step is read from the micro program memory, and the micro code of each field is applied to the corresponding processing unit.

FIG. 2 shows an example of the configuration of a circuit for supplying the microcode read for each step to the processing unit. In this figure, reference numerals 34, 35 and 36 denote unit stages of the shift register, and these 34 to 36 constitute a three-stage serial input / parallel output shift register serving as serial / parallel conversion means. The above-described clock pulse Φ is applied as a shift clock to a unit stage of each shift register, and a pulse (Φ / 3) having a cycle three times the clock pulse Φ is applied as a parallel output pulse. . That is, every time the pulse Φ is generated three times, the pulse Φ / 3 is generated once. Then, a microcode for the external RAM access unit is input to the first stage 34 of the shift register, and is sequentially shifted to a subsequent stage in each step in synchronization with the clock pulse Φ. Then, when the microcodes for the external RAM access unit for three steps indicated by the broken lines in FIG. 3 are stored in the respective stages 34 to 36 of the shift register, each pulse Φ / 3 causes The microcodes stored in the stages are read out in parallel and applied to the external RAM address control unit 31 and the external RAM access circuit 32.

Thus, the external RAM address control unit 3
1 and the external RAM access circuit 32,
External RAM based on microcode consisting of bits
14 to read or write and select an indexed option. For example,
Instructing reading / writing to the external RAM 14 by microcode of a step corresponding to a multiple of 3,
An indexed option is designated by two steps of microcode corresponding to (multiple of -1) and (multiple of -3). With this 2-bit indexed option, the form of the data to be written to the external RAM 14 can be specified. For example, if data compressed by a plurality of compression methods is read / written to / from an external RAM, the presence / absence of compression and the compression method are specified, or the exponent in the write data when reading / writing floating-point data is used. You can specify the number of bits for each part. Thus, access to the external RAM 14 is synchronized with the Φ / 3 clock, that is,
It will be executed in steps corresponding to multiples of three.

The microcode read from the microprogram memory and directed to another processing unit is provided with delay means 37 for delaying by a predetermined clock if necessary.
Through the processing unit.
In this case, for example, a microcode for instructing the multiplication unit 26 to execute a predetermined multiplication and a microcode for instructing the adder 28 to perform addition using the multiplication result are described in the same step. Sometimes, the instruction to the adder 28 is supplied with a delay until the timing at which the result of the multiplication by the multiplier 26 is output. By providing the delay means 37 in this way, a microprogram for the same processing can be described in the same step, and a microprogram can be easily created. The microcode that does not require such a delay process is supplied to the processing unit without any delay.

As described above, according to the present invention, a one-bit microcode is stored in each step of a microinstruction, and a plurality of steps of microcode are converted using a serial / parallel conversion means including a shift register. Since the data is converted into parallel microcode and supplied to the processing unit, the bit length of the microinstruction in each step can be reduced.

In the above description, the external RAM
The access to is performed in the step corresponding to a multiple of three, but is not limited to this, and may be performed in a step corresponding to an integer multiple of 2 or more. In the above-described embodiment, the field for controlling the access to the external RAM is targeted. However, the present invention is not limited to this, and any field corresponding to the process that needs to be executed for every predetermined number of steps is used. If
Exactly the same is possible. Furthermore, in the above-described embodiment, the DSP mounted on the electronic musical instrument has been described as an example. However, the present invention is not limited to this, and the present invention is similarly applied to any microprogram-controlled processing device. It is possible.

[0028]

Since the present invention is configured as described above, the instruction length of a microinstruction can be reduced, and the capacity of a microprogram memory can be reduced. Therefore, the size of the microprogram memory can be reduced, and the cost for producing an LSI can be reduced. If the same size can be used, more microprograms can be stored than before, and more microprograms can be stored. In the case of an effect DSP, various effects can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration of a DSP according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a main part of a microprogram supply unit 20 according to an embodiment of the DSP of the present invention.

FIG. 3 is a diagram illustrating a description example of a microprogram.

FIG. 4 is a block diagram illustrating a configuration example of an electronic musical instrument using a DSP.

[Explanation of symbols]

1 CPU, 2 timers, 3 MIDI input / output circuits, 4
MIDI terminal, 5 serial input / output circuit, 6 keyboards,
7 parallel input / output circuit, 8 panel display and operator, 9 program memory, 10 work RAM, 11
Sound source unit, 12 waveform memory, 13 digital signal processor (DSP), 14 delay memory (external RAM), 1
5 Digital-to-analog converter (DAC), 16 sound system, 17 CPU bus, 20 microprogram supply unit, 21, 24, 27 selector, 22 input / output RAM, 23 temporary RAM, 25 coefficient register and interpolation unit, 26 multiplication unit, 28 adder, 29 shifter, 30 data bus, 31 external RAM address controller, 32 external RAM access circuit, 37 delay circuit, 34-36 shift register

Claims (2)

[Claims] 1. A microprogram memory for storing a microprogram, and a serial / parallel for sequentially storing a part of fields of a microinstruction read from the microprogram memory for each step and outputting in parallel for each predetermined step A digital signal processing apparatus comprising: a conversion unit; and a processing unit controlled by parallelized microcode output from the serial / parallel conversion unit at each of the predetermined steps. 2. The digital signal processing device according to claim 1, wherein said partial field is a field for controlling access to an external memory.