JP2642092B2 - Digital effect device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital effect device for applying various effects to an input signal and outputting the resulting signal.

[0002]

2. Description of the Related Art Conventionally, various so-called effectors have been developed in which various effects (effects) are imparted to a musical instrument sound so as to obtain a sound considerably different from an original sound. Many use elements, and S
There were drawbacks such as a poor / N ratio. In recent years, a so-called digital effect device has been developed in which an effect is provided using a digital element without using such an analog element.

For example, as shown in Japanese Patent Application Laid-Open No. 60-10908, a so-called delay effect is provided by writing a waveform signal into a digital memory and reading out the written waveform signal after a predetermined time delay. As described in Japanese Patent Application Laid-Open No. 58-188693, an input waveform signal is written into a digital memory, and a plurality of the written waveform signals are output with different delay times, and
A signal that gives a so-called reverb effect by weighting and outputting each of these output waveform signals with different values has been proposed.

However, all of these methods only output a delayed waveform signal or perform processing for varying the level of the output waveform signal, and the output waveform is extremely monotonous.

In Japanese Patent Application Laid-Open No. 58-108583,
When reading a waveform signal written in a digital memory, the read address is changed with time according to a desired modulation effect, thereby giving a modulation effect such as so-called vibrato, chorus, or ensemble to the output signal. Has been proposed. However, also in this configuration, the output waveform signal only slightly fluctuates in phase or frequency as compared with the input waveform signal, and the form of the output waveform is considerably different from the input original waveform signal. Effects could not be added.

Further, in order to provide an effect of a so-called pitch shift effect that makes the frequency of the output waveform signal different from the frequency of the input waveform signal, the rate at which the input waveform signal is written to the digital memory is described. It has also been proposed to make the rate at which the embedded waveform signal is read out different. In such a configuration, a waveform signal having a frequency different from the frequency of the input waveform signal is simply output, and is also extremely monotonous.

[0007]

As described above, in the digital effect device proposed in the related art, only the frequency and the like of the output waveform signal differ from the input original waveform signal. By switching the frequency of the waveform signal freely, or by mixing and outputting a plurality of waveform signals of different frequencies, the output waveform form is significantly different from the input original waveform signal. Could not be given.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a waveform memory means capable of storing a waveform signal and a plurality of time-division processing channel times for the waveform memory means. A read / write means for performing read / write processing every time, and a waveform signal input at a timing of one time-division processing channel time of the read / write means is written into the waveform memory means at a desired rate. Read / write means for controlling the read / write means so as to read out the waveform signal written in the waveform memory means at a desired rate according to timing of at least two time division processing channel times of the read / write means; There is reading at the timing of at least one time-division processing channel time controlled by the writing control means. Is a rate control means for making the write rate different from the rate at the timing of another time division processing channel time, and a waveform signal read from the waveform memory means at the timing of the time division processing channel time of the read / write means. Out of the above, an output control means for controlling whether or not to output a waveform signal read at each timing.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a digital effect device according to an embodiment of the present invention will be described using an external sound signal PCM (Pulse Co., Ltd.).
ded Modulation) and digitally stored.
An apparatus constructed using an electronic musical instrument having a so-called sampling function which can be used as a sound source signal of a keyboard musical instrument will be described as an embodiment with reference to the drawings.

FIG. 1 shows a circuit configuration of the present embodiment. An input signal (IN) is appropriately amplified by an input amplifier 1, and
After being supplied to the analog addition circuit 2 and supplied to the filter 3 to remove unnecessary high frequency components appropriately, the sample
The signal is sampled at an appropriate sampling frequency by a hold circuit (S / H) 5 and supplied to an A / D converter 6. The A / D converter 6 converts an input analog signal into a corresponding digital signal, and supplies the digital signal to the tone control unit 8.

The tone generation control unit 8 includes, for example, four waveform reading / writing channels, and each of them independently has a waveform memory 7.
Waveform signals can be written or read from the

The tone control section 8 operates under the control of a CPU 9 comprising a microcomputer or the like. The details of the tone control section 8 will be described later, but four waveform read / write channels of the tone control section 8 are provided. A digital signal corresponding to up to four sounds in a time-sharing manner corresponding to
And applied to the D / A converter 10 in a time-division manner, and thereafter, the sample / hold circuit (S / H) 11
a to 11d.

The sample and hold circuits 11a to 11a
As for d, a sampling operation is performed at each time-division processing channel time in accordance with timing signals t1 to t4 described later.

The sample and hold circuit 11
The voltage signals held at a to 11d are correspondingly supplied to VCFs (voltage control filters) 12a to 12d. The VCFs 12a to 12d are supplied with voltage signals FCV1 to FCV4, which will be described later.
In accordance with CV1 to FCV4, the filtering process is performed independently.

The VCFs 12a to 12d are VC
A (voltage controlled amplifiers) 13a to 13d transmit the filtered analog waveform signals.

The gains of the VCAs 13a to 13d are independently controlled by the supplied control voltage signals ACV1 to ACV4, and the output levels or the volume envelopes of the waveform signals supplied from the VCFs 12a to 12d are determined.

The output signals of the VCAs 13a to 13d are sent to the outside as the outputs OUT1 to OUT4 of the respective channels, and are appropriately amplified and then emitted as sound signals. In addition, the VCAs 13a to 13a
The output of d is supplied to the analog addition circuit 14, mixed, and can be taken out as a mixed output OUTMIX.

The output of the VCF 12d corresponding to the above-described fourth channel and the output of the analog adding circuit 14 are supplied to an analog switch 15 which performs a switching operation in accordance with a control signal from the CPU 9 described above.

The analog switch 15 is connected to the VCF 12
The output of d and the output of the analog adding circuit 14 are selected and supplied to a VCA (voltage controlled amplifier) 16.

The VCA 16 amplifies the voltage in accordance with the supplied control voltage signal ACV0,
It will be fed back to and supplied.

Accordingly, the external sound signal supplied through the input amplifier 1 and the waveform signal obtained by reading the waveform memory 7 are mixed by the analog addition circuit 2 and supplied to the waveform memory 7 again. In this embodiment, a so-called overdubbing function can be realized. When overdubbing is not performed, the voltage control signal ACV0 for the VCA 16 is set to zero level.

Reference numeral 4 in the figure denotes a keyboard / display unit including a keyboard having performance keys and various control switches, and a liquid crystal display panel for displaying various states.
9 and the keyboard / display unit 4 exchange data.

The CPU 9 executes the above-described control signals FCV1 to FCV4 and ACV1 by software processing.
In order to generate .about.ACV4 and ACV0 (hereinafter collectively referred to as a control signal CV), a digital signal is supplied to a D / A converter group 17 to be converted into respective voltage signals.

The D / A converter group 17 controls the control signal CV
Or the number of D / A converters corresponding to the number of D / A converters may be provided, or one D / A converter may be used in a time-division manner and combined with a sample and hold circuit to control the required number of D / A converters. The signal CV may be obtained.

Next, the detailed circuit configuration of the tone generation control unit 8 is shown in FIG.
This will be described with reference to FIG. The digital signal supplied from the A / D converter 6 is supplied to the waveform memory 7 via the gate 81 and is also transmitted to the D / A converter 10 via the gate 82.

A read / write signal R / W generated from a control circuit (not shown) inside the tone generation control unit 8 is supplied to the gate 81 based on a control command generated by the CPU 9.
Is supplied to perform opening / closing control.

That is, when writing a waveform signal to the waveform memory 7, the gate 81 is opened, and when reading a waveform signal from the waveform memory 7, the gate 81 is closed.

The gate 82 is supplied with a gate signal Gate from an open / close signal generator 83 based on a control signal from a control circuit, and outputs a digital signal supplied via the gate 81, or Only when outputting the digital signal read from the waveform memory 7, the gate 82 is opened, otherwise the gate 82 is closed and its output is set to zero level.

In FIG. 2, reference numeral 84 denotes an address register composed of four stages of shift registers each having a predetermined number of bits, and a shift operation is performed by a master clock φs described later. The address register 84 stores 4
It operates as a channel address register in a time-division manner, and the contents of the final stage are supplied to the waveform memory 7 as address data, and the above-mentioned gate 81
A waveform signal input through the read / write signal R / W
Is at a low level only when the read / write signal R is written to the memory address.
When / W is at a high level, a digital signal is read from the memory address.

The contents of the address register 84 are supplied to a gate 85, and the open / close signal generator 8
3. It is supplied to the control circuit.

The address signal via the gate 85 is
The data is supplied to an adder 86, and if necessary, an addition / subtraction is performed to perform an address increment. Then, the data is fed back to an address register 84.

The adder 86 is supplied with an initial address (CA) from a control circuit via a gate 87.

That is, the load signal LD is directly supplied to the gate 85, the inverted signal is supplied to the gate 87 via the inverter 88, and if the load signal LD is at the low level, the initial address from the control circuit is output. (CA) is supplied to the adder 86 by the opening of the gate 87. On the other hand, if the load signal LD is at the high level, the gate 85 is opened and the content from the address register 84 is supplied to the adder 86. You.

The adder 86 includes a clock generation circuit 8
When the clock signal is supplied from the control circuit 9 and the digital signal is read from the waveform memory 7 in accordance with the scale frequency, the clock signal is supplied to the adder 86 at a rate corresponding to the pitch data from the control circuit. When the embodiment functions, a clock signal is always generated from the clock generation circuit 89 and supplied to the adder 86.

FIG. 3 shows a state of area division of the waveform memory 7, for example, N pieces of waveform information can be recorded in a variable length.

Next, the operation of this embodiment will be described. FIG. 4 shows the relationship between the time-division processing state of a plurality of channels of the tone generation control unit 8 and the timing signals t1 to t4 supplied to the sample-and-hold circuits 11a to 11d. Four waveform read / write channels are realized in a time-division configuration, and for each waveform read / write channel, whether to perform read (read) processing or write (write) processing is selective. , And in the state shown in FIG. 4, the channel 1 (ch
The waveform signal obtained through the filter 3, the sample-and-hold circuit 5, and the A / D converter 6 is written into the waveform memory 7 by the process 1), and the other channels 2 to 4 (ch2 4) can read a digital waveform signal in a predetermined area from the waveform memory 7.

The above-mentioned timing signals t1 to t4
Is set to a high level at times corresponding to the respective channels (ch1 to ch4), and converts the analog waveform signal output from the D / A converter 10 at each channel time to the sample / hold circuits 11a to 11a. At 11d,
Sampling is performed and then held.

Each of the waveform read / write channels of the tone generation control section 8 can independently designate an area for reading / writing. For example, the channels 2, 3,.
4, the tones 1, 2, and 3 of FIG.
The processing is controlled by 12b to 12d and VCAs 13b to 13d, and the analog adding circuit 14, switch 15, VCA 16
To the analog adder circuit 2 via an external audio signal if necessary, and then input via a sample / hold circuit 5 and an A / D converter 6 to the channel 1
Is recorded in the waveform memory 7 as the tone N again. That is, an overdubbing process can be performed.

Further, the CPU 9 sends the analog switch 15
, A switching signal is sent out, and the waveform signal read from the waveform memory 7 by the processing of the channel 4 is sampled.
Via the hold circuit 11d and the VCF 12d,
A16, the waveform signal obtained in this way is supplied to the analog addition circuit 2, and after mixing with an external sound signal in the same manner as described above, a predetermined area of the waveform memory 7 is written. You can also do so.

Next, the operation when this embodiment is used as a digital effect device will be described with reference to FIGS.

First, a waveform memory 7 for performing this operation is provided.
As shown in FIG. 6, when the use area is from address n to m as shown in FIG. 6, the control circuit in the tone generation control unit 8 sends the address register 84 shown in FIG. 2 as an initial address in channel 1 (ch1). Is n, channel 2
For (ch2), n-1, channel 3 (ch3)
In this case, n-3 is input, and in channel 4 (ch4), n-6 is input.

That is, as shown in FIG.
4 for one cycle, the load signal LD is set to the low level, and n-1 for the channel 1 and n- for the channel 2 as the initial address (CA).
2, n-4 is input for channel 3, and n-7 is input for channel 4, the adder 86 performs +1 processing,
The respective values described above are set as address data.

Then, the channel 1 is connected to the A / D converter 6
The read / write signal R / W is set to the low level so that the digital signals from the memory are sequentially written to the waveform memory 7, and the other channels 2 to 4 are stored in the waveform memory 7 by the channel memory 1 from the waveform memory 7. 7, the read / write signal R / W is set to a high level so as to perform a process of reading the digital signal written immediately before.

A gate signal Gate for opening the gate 82 is always generated from the open / close signal generator 83 at the timing of the channel 1, and the address registers 84 of the other channels 2 to 4 are shown in FIG. The gate 82 is opened only when the address n or later is designated.

As a result, the waveform memory 7 stores the peak value f (n), as shown in FIG.
As f (n + 1), f (n + 2),... are written, the data is supplied to the D / A converter 10 via the gate 82, and the sample / hold circuit 11a, V
The signal is converted into an acoustic signal via the CF 12a and the VCA 13a, and is output as sound.

In the channel 2, as shown in FIG. 5, the digital signal written in the waveform memory 7 by the operation of the channel 1 is delayed by 4 channel times, that is, 1T (T = 4 × channel time). , From the waveform memory 7, and similarly, the channel 3 is read out over the 3T delay, and the channel 4 is read out over the 6T delay.

That is, each of the channels 2 to 4 outputs a digital signal corresponding to the peak value shown in FIG. 6 with a time lag by the difference value set as the initial address (CA).
Transmitted to converter 10.

As a result, the waveform signals of the channels 2 to 4 are output through the VCFs 12b to 12d and the VCAs 13b to 13d. You can also.

Hereinafter, the channel 1 writes the waveform signal supplied via the A / D converter 6 to the waveform memory 7, which shifts the time by 1T in the channel 2, and
Shifts the time by 3T, and channel 4 shifts the time by 6T
Each of the sounds is read out from the waveform memory 7 while being shifted, and four sounds are simultaneously generated. When the address data reaches the address m of the waveform memory 7 in FIG.
When the channel 1 is re-inputted, a new waveform signal is written again from the address n of the waveform memory 7 in the channel 1, and the new waveform signal is read out in the channels 2 to 4, so that it can be used for a long time. Become like

In the above description, all four channels are operated to enable simultaneous generation of four sounds. However, fewer channels are selectively operated to apply one or more delays to the original sound. A sound may be output.

In the above description, the channels 2, 3,.
The delay time for channel 1 of 4 is 1T, 3
Although T and 6T are used, they can be specified on the keyboard / display unit 4 respectively.

As described above, in this embodiment, a plurality of waveform read / write channels are used to write a waveform signal into the waveform memory 7 while delaying it for a predetermined time and reading it out. Since the signal is synthesized with the waveform signal and output, various delay effects can be realized.

Further, for each waveform read / write channel,
Since the tone and volume are independently variably controlled using the VCFs 12a to 12d and the VCAs 13a to 13d, more effective sound can be obtained.

In the above-described embodiment, the VCF
Although the timbre and the volume are variably controlled by the 12a to 12d and the VCAs 13a to 13d, the variability of the timbre, the volume or the envelope may be controlled by using a digital filter or a digital multiplier. Further, other processing may be performed on the waveform signal.

The circuit configuration of the tone generation control unit 8 is as follows.
As in the above embodiment, a plurality of waveform reading /
In addition to the configuration of the write channel, a plurality of waveform read / write channels may be provided using separate hardware, that is, using the same circuit configuration for the number of channels.

Further, of the plurality of channels, a specific channel is a write-only channel for writing a waveform signal to the waveform memory 7, and the other channels are read-only channels for reading a waveform signal from the waveform memory 7. It may be. The "waveform read / write channel" in the present invention means either one of read and write, or a channel capable of performing both operations.

In the above embodiment, the present invention is applied to an electronic musical instrument having a sampling function. However, the present invention can of course be implemented as a digital effect device having a dedicated circuit configuration. That is.

[0058]

As described above, according to the present invention, an input waveform signal is written into a waveform memory at one time-division processing channel time, and the written waveform signal is subjected to a plurality of time-division processing. Each of the plurality of read waveform signals is read out at a different rate at the timing of the channel time, and only a desired one of the plurality of read out waveform signals is output. In addition to outputting a signal, the frequency of the output waveform signal can be freely switched, or any of a plurality of different frequency waveform signals can be selected and output. Therefore, for example, when the digital effect device according to the present invention is applied to an electronic musical instrument or the like, it is possible to freely select and generate musical tones having a plurality of pitches completely different from the input musical tones, which is musically preferable. This produces an effect that various musical sounds can be generated.

[Brief description of the drawings]

FIG. 1 is an overall circuit configuration diagram of a digital effect device according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a sound generation control unit 8 in FIG.

FIG. 3 is a diagram illustrating a divided use state of a waveform memory 7 in FIG. 1;

FIG. 4 is an explanatory diagram of a basic operation of the present embodiment.

FIG. 5 is a time chart when operated as a digital effect device.

6 is an explanatory diagram of the operation state of FIG.

[Explanation of symbols]

 Reference Signs List 6 A / D converter 7 Waveform memory 8 Sound generation controller 9 CPU 10 D / A converter 12a to 12d VCF 13a to 13d VCA 81, 82, 85, 87 Gate 84 Address register 86 Adder

Claims (1)

(57) [Claims] 1. A waveform memory means capable of storing a waveform signal, a read / write means for performing read / write processing on the waveform memory means for each of a plurality of time division processing channel times, and one of the read / write means. A waveform signal input at a timing of two time-division processing channel times is written into the waveform memory means at a desired rate, and the waveform signal written into the waveform memory means is read by at least two of the read / write means. A read / write means for controlling the read / write means so as to read at a desired rate according to the timing of the division processing channel time; and at least one read / write control means controlled by the read / write control means
Rate control means for making the reading or writing rate at the timing of one time division processing channel time different from the rate at the timing of another time division processing channel time; and the time division processing channel time of the reading and writing means from the waveform memory means. Output control means for controlling whether or not to output a waveform signal read at each timing among the waveform signals read at the timing described in (1).