JPH028319B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention efficiently combines melody sounds and accompaniment sounds.
Furthermore, the present invention relates to a digital electronic musical instrument that can be produced with a simple configuration. [Prior art and its problems] In recent years, electronic musical instruments that generate musical tones using digital methods have been put into practical use. This type of digital electronic musical instrument is disclosed in, for example, Japanese Patent Application Laid-Open No. 55-89894, Japanese Patent Publication No. 52-30844, and Japanese Patent Application Laid-open No. 53310/1989. By the way, in this type of digital electronic musical instrument, it has been considered in the past to share and selectively use the musical tone generation means of multiple channels for melody sounds and accompaniment sounds (for example, in the above-mentioned Japanese Patent Laid-Open Publication No.
See the description of the prior art in Publication No. 53-53310. ) However, after converting the musical sound information (digital signal) output from such musical sound generating means into an analog signal, it is possible to perform different processing, such as filter processing and volume control processing, for melody sounds and accompaniment sounds. However, the structure is still insufficient to achieve this goal, and there is room for improvement. [Object of the Invention] This invention has been made in view of the above points, and is an object that enables melody sounds and accompaniment sounds to be generated efficiently with a compact circuit configuration.
Moreover, it is an object of the present invention to provide a digital electronic musical instrument in which appropriate signal processing can be performed separately on melody sounds and accompaniment sounds after they are converted into analog signals. [Summary of the Invention] That is, in order to achieve the above object, the present invention provides a melody sound/accompaniment sound generation means that can selectively generate digital musical sound information representing a melody sound and digital musical sound information representing an accompaniment sound. Furthermore, when generating digital musical sound information representing a melody sound from this melody sound/accompaniment sound generating means, the digital musical sound information is data-transferred to a melody sound generating means that exclusively generates melody sounds, and the melody sound generating means After digitally synthesizing the digital musical tone information representing the melody tone generated by the melody tone, the digital musical tone information is supplied to the first digital-to-analog converter to generate an analog signal, and the digital musical tone information representing the accompaniment tone is generated from the melody tone/accompaniment tone generating means. When doing so, the key point is to supply it to a second digital-to-analog converter connected to itself to convert it into an analog signal. [Example] Hereinafter, an example of the present invention will be described in detail. FIG. 1 shows a circuit block of this embodiment. In the figure, 201 is a CPU consisting of a microprocessor or the like. Although not shown, external operation signals such as an external switch or key switch are supplied to the CPU 201, and information indicating what kind of musical tone should be generated (specifying scale, timbre, etc.)
is supplied to LSIs (Large Scale Integrated Circuits) L3, L4, and L5 via the control bus C2. this
LSIs L3, L4, and L5 each have a one-chip configuration. Furthermore, from the CPU 201, LSI L3, L4,
Chip select signals C1, C2, and C3 of L5 are supplied through respective terminals CS. Therefore, if each of the chip select signals C1, C2, C3 is "1", the corresponding LSI L3, L4, L5 is selected, and if it is "0", the corresponding LSI is not selected. LSIs L3, L4, and L5 have exactly the same circuit configuration. For example, each LSI L3, L4, and L5 has 4
It is now possible to generate musical tones up to the pitch by time-sharing processing. Note that various methods of musical tone generation have been developed in the past, and it goes without saying that any digital method can be applied.
For example, it is assumed that the LSIs L3, L4, and L5 of this embodiment have a circuit configuration based on a sine wave synthesis method, and are composed of five overtones of one musical tone. Therefore, each LSI
L3, L4, and L5 are each 20 at the same time (=5 overtones x 4
It has a function to synthesize and output sine waves of musical tones. Each of the LSIs L3, L4, and L5 has a function of serially transmitting musical tone amplitude information and envelope information via signal transmission lines. That is, if a "1" signal is given to the master/slave terminal M/S of each LSI L3, L4, L5, that LSI will function as a master, and if a "0" signal is given, that LSI will function as a slave. The data from the LSI set as the slave is transferred to the LSI set as the master, and is combined with the data generated by the LSI set as the master. Therefore, from the LSI set as the master, for example, 16-bit amplitude data (up to 8 tones, in other words, data obtained by synthesizing up to 40 sine waves) is converted into an envelope as described later. A predetermined bit shift is made based on the data and the terminal _D0
Output from ~ _D15 . Furthermore, 2-bit data for determining the amplification factor is output from each LSI L3 and L4 via terminals _S0 and _S1 . In the case of this embodiment, this LSI L3 is 4
Performs the function of generating melody sounds up to the sound,
LSI L4 functions to generate up to four melody tones or accompaniment tones by switching the control signal AUTO/MN, and LSI L5 functions to generate one bass tone. Although the LSI L5 has the ability to generate up to four tones, it is designed to output only one bass tone. The control signal AUTO/MN is supplied to the master/slave terminal M/S of LSI L4, and is also supplied to the AND gate 20 via the inverter 202.
3,204. Then, musical tone information is applied from LSI L4 to the AND gate 203 via the terminal DATA, and envelope data is applied to the terminal
Applied to AND gate 204 via ENV.
And the output of AND gate 203 is LSI L3
is connected to the terminal DATA of the AND gate 204
The output of is connected to terminal ENV of LSI L5. Also, terminals DATA and ENV of LSI L4 and L5 are connected. Then, a "0" signal is supplied to the master/slave terminal M/S of LSI L5. Therefore, this LSI, L5, always sends data.
It is set to be transferred to LSI L4. Further, a "1" signal is always supplied to the master/slave terminal M/S of LSI L3. Therefore, this LSI L3 always uses AND gate 203,
204 , the amplitude information is compressed and output to the D-A converter 205 , and the output of this D-A converter 205 is Amplifier 2 is supplied with
06, 2-bit data that determines the amplification factor is output from terminals S ₀ and S ₁ . Similarly, from LSI L4, DA converter 207
Amplitude data is supplied to the LSI L4, and the output thereof is amplified by an amplification factor determined by the 2-bit data supplied from the LSI L4 in the amplifier 208 and then output. Furthermore, the LSI L3 directly connects the sample/hold circuit 209 to the sample/hold circuit 210.
is supplied from the sampling clock terminal S/HCLK via the AND gate 211.
These sample/hold circuits 209 and 210 are D
- The sample/hold circuit 209 is provided to prevent glitches in the A conversion output, and the sample/hold circuit 209 samples and holds the output of the amplifier 206 and outputs it as a melody sound.
sample-holds the output of the amplifier 208 and outputs it as an accompaniment sound (including bass sound). In addition,
A sampling clock is supplied to this sample/hold circuit 210 only when the control signal AUTO/MN applied to the AND gate 211 is "1". Next, the detailed configuration of the main parts of LSI L3 will be explained with reference to FIG. Note that the positions of the terminals in FIG. 2 and the terminals in FIG. 1 do not correspond in some parts. Further, the other LSIs L4 and L5 have exactly the same configuration. Therefore, in LSI L3, amplitude information of up to four tones (addition value of up to four tones of envelope-controlled amplitude information) _d0 to _d14 is generated by time-sharing processing and sent to transfer gates G1 to G15. Given. Note that a "0" signal is always applied to the transfer gate _G16 . The transfer gates _G1 - _G16 are opened by a timing signal _t15 , which will be described later, and their output signals are applied to the latches 11-26. Therefore, each amplitude value of a musical tone is obtained by performing processing to change it at every timing _t15 . These latches 11 to 26 perform a read operation using the clock φ ₁ (described later), and when the timing signal t ₁₅ becomes a “1” signal, they read the output signals of the transfer gates G ₁ to _{G 16} as described above. However, at other timings, that is, from _t0 to _t14 , the outputs of the latches 12 to 26 on the upper bit side and the addition output of the full adder 27 are read through transfer gates _G17 to _G32, respectively. That is, the timing signal _t15 is inverted and supplied as a gate signal to the transfer gates _G17 to _G32 via the inverter 28, so that the timing signal _t0 is supplied to the transfer gates G17 to G32.
At ~t ₁₄ , transfer gates G ₁₇ ~ _{G 32} will be opened. The full adder 27 has the output of the latch 11.
DO is applied to the B input terminal, and serial data supplied from the slave LSI input from the data input terminal DATA is applied to the A input terminal via the AND gate 29. If the AND gate 29 is set as a master, a "1" signal is applied to one end and the gate is opened, but if it is set as a slave, a "0" signal is applied to one end and the AND gate 29 is opened. Therefore, this master
In LSI, the slave is connected via AND gate 29.
The output of the LSI is supplied to the full adder 27. On the other hand, in the slave LSI, the corresponding AND gate 29 is closed. However, inverter 30
Since the master/slave signal inverted at is supplied to the transfer gate _G33 , the transfer gate _G33 is opened and the output DO of the latch 11 is outputted via the terminal DATA. Note that one input terminal of the AND gate 29 and the input terminal of the transfer gate _G33 are connected to a resistor _R1 .
It is set to the ground level (“0” level) via. Thus, the terminal DATA is set to function as an input terminal in the master LSI and as an output terminal in the slave LSI. Therefore, in the full adder 27 in the master LSI, musical tone information generated in the master LSI and
The musical tone information generated within the slave LSI is serially added bit by bit, and the transfer gate is
G ₃₂ to latch 26. In addition, the carry output terminal of Full Adder 27
A carry signal is output from COUT and applied to latch 32 via AND gate 31. Note that the output signal of the inverter 28 is supplied to this AND gate 31, and the AND gate 31 is opened at timings _t0 to _t14 . Then, the latch 32 performs a reading operation at clock _φ1 ,
Its output is the carry input terminal of the full adder 27
It will be applied to CIN. In this way, the musical tone information generated by the master LSI and the musical tone information generated by the slave LSI are added by the full adder 27, and the resulting data is latched in the latches 11 to 26.
The information is transferred and latched in parallel to the latches 33-48 at the timing of clock _φ16 (described later). The outputs of the latches 33-48 are sent to the clock φL via transfer gates _G34 - _G49 .
The latches 49 to 64 perform the reading operation (described later).
is applied to In addition, the above transfer gate
A timing signal _t15 is supplied to the gates of _G34 - _G49 , and the contents of latches 33-48 are transferred to latches 49-64 only at timing _t15 . At other timings, transfer gates _G50 to G64 connected to the output terminals of latches 49 to 63 are opened, and the voltage is applied to the input terminals of latches 50 to ₆₄ on the upper bit side, respectively. . In addition, the above transfer gate
A timing signal _t15 is inverted by an inverter 65 and supplied to each gate of _G50 to _G64 . Therefore, the latches 33 to 4 are set by the clock φL.
The musical tone information supplied from 8 is shifted to the upper bit side as necessary, in other words, it is compressed and output to latches 66-81. The above-mentioned latches 66 to 81 perform a reading operation using the clock _φ16 , and their outputs are sent to the above-mentioned terminals _D0 to _D15.
supply to Note that the output of latch 81 corresponding to the most significant bit, ie, the sign bit, is inverted by inverter 82 and applied to output terminal _D15 . That is, the waveform calculation process is performed by two's complement calculation in this embodiment, and the latches 66 to 81 are
The maximum level (positive) is "01...1", the zero level is "0...0", and the minimum level (negative) is "10...01", but this inverter 82 provides linear output characteristics. It will be done. That is, the maximum level is "11...1", the zero level (ground level) is "10...0", and the minimum level is "00...01". Next, the envelope data synthesis circuit will be explained. In the master LSI, envelope information for up to four notes is synthesized at the same time as the above-mentioned musical tone amplitude information, and the transfer gate G ₆₅ ~ _{G 71}
is applied to For this envelope data, the original envelope data may be added as is, but only the upper bits may be added. In this embodiment, the addition data of envelope data of up to 4 notes is 7 bits. ( _E0 ~ _E6 )
Suppose that it is expressed as . Although not shown, this envelope data is also used to generate the amplitude information d ₀ to _{d 14} of the musical tones described above, and each musical tone is generated using the amplitude data of the original waveform and the amplitude information at that time. It is obtained by multiplying the envelope data. However, the above transfer gate G ₆₅ ~ _{G 71}
A timing signal _t15 is supplied as a gate signal to the transfer gate _G72 , and only at timing _t15 , the gate is opened and envelope data is supplied to the latches 83-90.
Note that a "0" signal is applied to the transfer gate _G72 . These latches 83 to 90 perform a read operation using the clock φ ₂ (described later), and when the timing signal t ₁₅ becomes a “1” signal, the output signals of the transfer gates G ₆₅ to _{G 7} B are read as described above. It loads, but
At other timings, that is, from _t0 to _t14 , the outputs of the latches 84 to 90 on the upper bit side and the addition output of the full adder 91 are read through transfer gates _G73 to _G80 , respectively. That is, the timing signal t ₁₅ is inverted and supplied as a gate signal to the transfer gates G ₇₃ to _{G 80} via the inverter 92, and therefore the timing signal t ₀ to G 80 is
At t ₁₄ , transfer gates G ₇₃ to G ₈₀ will be opened. The full adder 91 has the output of the latch 83.
EO is applied to the B input terminal, and serial data input from the envelope data input terminal ENV is applied to the A input terminal via an AND gate 93. If this AND gate 93 is set as a master, a "1" signal is applied to one end and the gate is opened, but if it is set as a slave, a "0" signal is applied to one end and the AND gate 93 is closed. Therefore, in the master LSI, the output of the slave LSI is supplied to the full adder 91 via the AND gate 93. On the other hand, in the slave LSI, the corresponding AND gate 93 is closed. However, since the master/slave signal inverted by the inverter 94 is supplied to the transfer gate _G81 , the transfer gate _G81 is opened and the output EO of the latch 83 is connected to the terminal.
It will be output via ENV. Note that one input terminal of this AND gate 93 and the input/output terminal of transfer gate G ₈₁ are connected to a resistor.
It is set to ground level (“0” level) via _R2 . Therefore, the terminal ENV is set to function as an input terminal in the master LSI and as an output terminal in the slave LSI. Therefore, the full adder 91 in the master LSI serially adds the envelope information generated in the master LSI and the envelope information generated in the slave LSI bit by bit, and adds the envelope information bit by bit to the latch ₉ via the transfer gate G80.
Apply to 0. In addition, the carry output terminal of Full Adder 91
A carry signal is output from COUT and applied to latch 96 via AND gate 95.
Note that this AND gate 95 includes an inverter 9
2 output signals are supplied, and the timing t ₀ ~
At t ₁₄ , AND gate 95 is opened. and,
The latch 96 performs a read operation at the clock φ ₂ and its output is applied to the carry input terminal CIN of the full adder 91. In this way, the envelope data generated by the master LSI and the envelope data generated by the slave LSI are transferred to the full adder 91.
The resulting data is added to the latches 83-9.
When latched to 0, the information of the upper 3 bits is latched in parallel in latches 97 to 99 at the timing of clock _φ16 . The outputs of latches 97-99 are input to decoder 103 directly and via inverters 100-102. Note that this decoder 103
consists of a Noah matrix circuit, and this decoder 1
03 output lines m ₁ to _{m 4} , m ₅ , m ₆ outputs,
The relationship with latches 97-99 is as shown in Table 1.

[Table] In Table 1, × is “0” or “1”
This indicates that it may be either of the following.
The outputs of the lines m ₁ to _{m 4} are applied to one input terminal of AND gates 104 to 109. The AND gates 104 to 107 are supplied with the outputs of the OR gates 108, 109, and 110 and the timing signal _t15 . Note that this OR gate 108 has timing signals t ₀ , t ₁ , t ₂ ,
t ₁₅ is supplied, the OR gate 109 is supplied with timing signals t ₀ , t ₁ , t ₁₅ , and the OR gate 110 is supplied with timing signals t 0 , t 1 , t 15 .
are supplied with timing signals t ₀ and t ₁₅ . The outputs of the AND gates 104 to 107 are supplied to the OR gate 111, and the AND gates 112
It will be output as clock φL via .
Note that one end of this AND gate 112 is supplied with a clock φ ₁ . In this way, the clock φL output through the AND gate 112 is output as shown in Table 2.

[Table] Also, lines m ₅ and m ₆ from the decoder 103
The data output through the latches 113 and 114
is read by clock _φ16 . The outputs of the latches 113 and 114 are applied to the amplifier 4 via terminals S ₀ and S ₁ to determine the amplification factor. For example, in the case of this embodiment, the amplification factors are as shown in Table 3.

[Table] Next, the operation of this embodiment will be explained. First, each
The operation of the LSI will be explained first. FIG. 3 shows the clock and timing signals etc. supplied to the electronic musical instrument of this embodiment.
The writing of 6 and 32 is performed by the clock _φ1 shown in FIG. 3a, and the above-mentioned latches 83 to
The writing of 90 and 96 is performed by clock _φ2 shown in FIG. 3b. In addition to these latches, all the latches mentioned above are read out in synchronization with the clock φR shown in FIG. 3c. Each circuit _shown in _FIG .
(see Figure e) as a basic cycle, and the amplitude data, composite data, and composite data of envelope data of each tone are determined by timing _t15 . Therefore, at timing t ₁₅ (see FIG. 3 f), transfer gates G ₁ to _{G 16} and G ₆₅ to _{G 72} of both the master LSI and slave LSI are opened,
Respective data is applied to latches 11-26, 83-90. Therefore, the data is latched in latches 11-26 at clock _.phi.1 and in latches 83-90 at clock _.phi.2 . Then, at the next timing _t0 to _t14 , the contents of the latches 11 to 26 are synchronized with the clock _φ1 .
The bits are sequentially supplied to the full adder 27 and the transfer gate _G33 starting from the lower bit, and the contents of the latches 83 to 90 are synchronized with the clock _φ2 .
The bits are sequentially supplied to the full adder 91 and the transfer gate _G81 starting from the lower bit. Therefore, in the master LSI, transfer gates G ₃₃ and G ₈₁ are closed and AND gates 29 and 93 are opened, while the slave LSI
, transfer gates G ₃₃ and G ₈₁ are opened, and AND gates 29 and 93 are closed. Therefore, the master LSI full adder 27,9
1 adds the amplitude data and envelope data serially transferred from the slave LSI to the amplitude data and envelope data generated by the master LSI. In the slave LSI full adder 27,91,
It simply outputs the data supplied from each B input terminal. FIGS. 3g and 3h show changes in the data DO output from the latch 11 and changes in the data EO output from the latch 83, respectively. In this way, in the master LSI, the master
The resultant data obtained by adding the data of the LSI and the data of the slave LSI is applied to the latches 33-48, _97-9 by the clock φ16 shown in FIG. 3d.
9. The amplitude value data and envelope data (upper 3 bit data) read into the latches 33-48, 97-99 are held for the next cycle from _t0 to _t15 , and during that time, the musical tone data compression processing is performed. That is, as shown in Table 2 above, latch 97
Based on the 3-bit data stored in ~99,
Clock φL is output from AND gate 112. The clock is also shown in FIG. 3i. That is, no matter what value the contents of the latches 97 to 99 have, the clock φL outputs at timing _t15 and the outputs of the latches 33 to 48 are latched, as shown in FIG. 49 to 64 are stored. After that, the output of clock φL becomes “1”
Each time, the contents of the latches 49-64 shift toward the higher bits. In other words, as can be understood from Table 2 and Figure 3 i, if the envelope value is large, that is, if the contents of latches 99 to 97 are "1xx", no shift is performed;
If the content is “01×”, shift by 1 bit,
Also, if it is "001", it is shifted by 2 bits, and if it is "000", it is shifted by 3 bits, and then the latch is set to 49.
~64 retains its contents. Then, at clock _φ16 , latches 66 to 81 latch the resultant data shifted in accordance with the magnitude of the envelope value. At the same time, latches 113 and 114 begin to latch the 2-bit data output from lines m ₅ and m ₆ supplied from decoder 103. In this way, the master LSI converts the amplitude data and envelope data from the slave LSI into the amplitude data and envelope data generated by the master LSI.
Combined with envelope data and output. That is, 2-bit data representing the amplification factor obtained from the envelope data is supplied to the subsequent amplifier, and compressed amplitude data is supplied to the D-A converter, converted to an analog signal, and then supplied to the amplifier. It will be done. Now, in the case of this embodiment, from the CPU 201,
Control signal AUTO/MN is given as shown in Table 4. That is, this Table 4 shows the control signal AUTO/MN.
Depending on whether is “0” or “1”, LSI
It shows how the functions of L3 to L5 are set.

〔Effect of the invention〕

As explained above, the present invention enables data transfer between the melody sound generation means and the melody sound/accompaniment sound generation means, and digital musical sound information representing the melody sound is digitally synthesized by the melody sound generation means. After that, the digital musical tone information representing the accompaniment tone is converted into an analog signal by the first digital-to-analog converter connected thereto, and the digital musical tone information representing the accompaniment tone is converted into an analog signal by the second digital-to-analog converter connected to the melody tone/accompaniment tone generating means. Since the melody sound/accompaniment sound generation means is used both when generating melody sounds and when generating accompaniment sounds, it is efficient, and moreover, the melody sound signal is always the first one. Since the accompaniment sound signals are output from the first digital-to-analog converter and the accompaniment sound signals are output from the second digital-to-analog converter, analog processing at the subsequent stage can be easily performed and is more appropriate.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention; FIG. 1 is a circuit block diagram of the embodiment, FIG. 2 is a detailed view of the main parts of the embodiment, FIG. 3 is a time chart of the embodiment, and FIG.
The figure is a diagram showing changes in the output volume of the same embodiment. 201...CPU, 205,207...D-A
Converter, 206, 208...Amplifier, 27, 91
...Full Adder, 97-99...Ratsuchi, 103
...Decoder, 49-64...Latch, L3-L
5...LSI.

Claims (1)

[Scope of Claims] 1. A melody sound generating means capable of generating digital musical sound information representing a melody sound, and a second circuit connected to the melody sound generating means and converting the provided digital musical sound information representing the melody sound into an analog signal. 1, a digital-to-analog converter, a melody sound/accompaniment sound generating means capable of selectively generating digital musical sound information representing a melody sound and digital musical sound information representing an accompaniment sound, and connected to the melody sound/accompaniment sound generating means. is,
a second digital-to-analog converter that converts the generated digital musical tone information representing the accompanist into an analog signal when the melody sound/accompaniment sound generation means generates the accompaniment sound; and the melody sound/accompaniment sound generation means When generating a melody sound, the means transfers digital musical sound information representing the generated melody sound to the melody sound generating means, and synthesizes it with digital musical sound information representing the melody sound generated by the melody sound generating means. and a means for supplying the first digital-to-analog converter to the first digital-to-analog converter. 2 The melody sound generating means and the melody sound/
2. The digital electronic musical instrument according to claim 1, wherein the accompaniment sound generation means is capable of generating a plurality of digital musical tone information by time-sharing operation. 3 The melody sound generating means and the melody sound/
3. The digital electronic musical instrument according to claim 1, wherein each of the accompaniment sound generating means is formed of a one-chip semiconductor integrated circuit.