JPS62269998A - Digital electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] ['! of the invention] -2 Technical Field] The present invention relates to a digital electronic musical instrument that has a number of stages of musical tone generating means and is configured to digitally synthesize multi-bit digital musical sound waveform information obtained from each musical tone generating means.

[Prior art and its problems]

In recent years, digital methods have been used to generate musical tones (
Advanced electronic musical instruments are now being put into practical use. However, such electronic musical instruments have some musical tone generation circuits (each musical tone generation circuit generates one musical tone, and some generates multiple musical tones from one time-minute-1 process). In this case, in order to synthesize these outputs, digital-to-analog conversion is often performed and then analog mixing is performed (see, for example, Japanese Patent Laid-Open No. 55-89894). However, since this type of system requires multiple D-A converters, the hardware increases, and as a result, the cost increases.
R. It had the disadvantage of being unsuitable for manufacturing child musical instruments.

There are also types that digitally synthesize 1'n digital musical sound waveforms (for example, Japanese Patent Publication No. 52-30844).
However, in order to synthesize multi-bit digital musical sound waveform information, the number of signal transmission lines equal to the number of bits is required, and a φ-bit parallel divider is required, resulting in a large circuit scale. There was a problem with it becoming.

[Purpose of the invention]

This invention (well, it was made in view of the above point), after digitally synthesizing multi-bit digital musical sound waveform information output from a plurality of musical tone generating means in an additive configuration,
It is an object of the present invention to provide a digital electronic musical instrument in which an analog musical tone signal is obtained from the synthesized digital musical sound waveform t'f4 signal using a digital-to-analog converter.

[Key points of the invention]

That is, in order to achieve the above-mentioned object, the present invention has a musical tone generating means on the transmitting side that divides the digital musical sound waveform m signal into 41 pieces each having a predetermined number of bits, and sequentially generates the d signal on the receiving side to generate a musical tone. the reception side musical tone generation means includes a reception means for receiving the divided signals transmitted from the transmission side musical tone generation means; Multi-bit upper dd from divided signal
The main point is that it is digital.

〔Example〕

Hereinafter, one practical example of the present invention will be described in detail. FIG. 1 shows a circuit block of this embodiment, and 1 in the figure is a CPtJ consisting of a microprocessor or the like.

Although not shown in the diagram, this CPtJ 1 is supplied with an external operation signal such as an external switch or a round switch, and information on what kind of musical tone should be generated (specifying the 'Vr scale, tone color, etc.) is sent to the CPtJ 1. Through my hands, L
Supplies to SI (large scale integrated circuit) LX and L2. This L
SI Ll.

Each of L2 has a one-chip configuration. History 1, from CPtJx, chip select signal CI of LSI Ll, L2
/C2 via respective electrons C8.

Note that LSI L2 has the above chip select (+!
The chip select signal CI/C2 is inverted and supplied via the inverter 2.
If is 1#, LSI Ll is selected, and if @0'', LSI L,2 is selected.

I, SI i, 1. L2 has exactly the same circuit configuration,
For example, each LSI LL and L2 is capable of generating up to four musical tones by time-sharing processing. fi oh,
Various methods of musical tone generation have been developed in the past, and it goes without saying that any digital method can be applied; for example, the LSI 1 of this embodiment,
1, 1, and 2 have a sine wave synthesis circuit configuration,
Assume that one musical tone consists of five overtones. Therefore, each L
SI Ll, I, 2 are each 20 (=5 times - fX
It has a function to synthesize and output a sine wave of 4f).

The data m, the amplitude information of the musical tone, and the envelope information from the LSI L2 are serially transferred to the LSI L1 via lines tx and L2, respectively. In other words, although these lines As and Ax are bidirectional lines, if a 1" signal is applied to the master/slave terminal M/81 of each LSI LL and L2, that LSI will function as a master and will output "0". If you give the number a, it will be used as a slave, and in this case, it is not set as the master.
8I Lll, i, SI set to slave
The data of L2 is transferred and combined with the data generated by LSI LL+trowel.

Therefore, from the LSI Ll, for example, 16-bit transmission data (up to a maximum of 8 tones, in other words, a maximum of 40
The data obtained by synthesizing the sine waves of fl, 1) is
As will be described later, the signal is shifted by a predetermined bit based on the envelope data and output from the terminal DG-%-DiM.

Furthermore, 2-bit data that determines the amplification factor is output from the LSI Ll via terminals So and Ss.

The digital information output from the terminal Do-wDts is converted into a voltage (No. 1) by the D-A converter 3, and the signal is supplied to the amplifier 4, where it is converted to a voltage (No. 1) at a set amplification factor. The width will be output.

Therefore, in this example, LSI L2 is the musical tone generating means on the transmitting side, and LSI LL is the musical tone generating means on the receiving side.

Next, I will explain in detail the tricks of the LSI (LSI L2 is exactly the same) with reference to Figure 2.

Note that the positions of the terminals in FIG. 2 and the terminals of the first gigo do not correspond in some parts.

Therefore, in LSI Ll, amplitude information of musical tones up to 4 tones (envelope-controlled amplitude information addition up to 4 tones 1α) dO%d14 is generated by time-sharing processing, and transformer 7 Agate Gl~ Given to Gts.

Note that @O' (No. 1 is always applied to the transfer gate) G16.The transfer gates G1 to Gig are opened at timing<d sealing S, which will be described later, and their output signals are applied to the latches 11 to 26. Therefore, each amplitude value of the musical tone is obtained by processing so as to change the timing≠→every mouth 5.

These latches 11 to 26 perform a reading operation using the clock φ1 (described later), and the timing IPA number 5 is S'''1.
(At the time of No. 1, the output signal of the transfer game Ox-waxs is read as described above, but at other timings, that is, from t0 to 4), the output signal of the latches 12 to 26 on the upper bit side is read. and full adder 27
IJU calculation outputs Transformer 7 Agate 017~G3
Read via 2. That is, this transfer game) 0
17 to G32 have gates (timing (i4) as No. 1)
No. 1S is inverted and supplied via the inverter 28, and therefore, at timing to-414, transfer gates 017-G$2 are opened.

To the full adder 27 (Ma, the output DO of the latch 11 is B
S of the data input terminal DA'rA (line tl and Ha) is applied to the input terminal, and the input terminal has the S
Serial data input from LSI L2 is inputted via AND gate 29.

If this AND gate 29 is set as a master, a 1" signal is applied to one end and the gate is opened, but if it is set as a slave, an O" signal is applied to the shoulder and the gate is closed. . Therefore, in this LSI Ll, the AND gate 29
The outputs of LSIs 1 and 2 are supplied to the full adder 271 via the full adder 271.

On the other hand, in LSI L2, the corresponding AND gate 29
is closed. However, the master/slave signal inverted by the inverter 30i is transferred to the transfer gate G33.
The transfer gate Gss is opened to supply the
The output DO of the latch 11 is outputted via the terminal DATA.

Note that one input terminal of the AND gate 29 and the input terminal of the transformer 7 agate G33 are set to the ground level ("0" level) via a resistor l(.1).

Therefore, the terminal 1) ATA connected to tl is L
The function is set as an input terminal in SI LX, and as an output terminal in LSIL2.

Therefore, in the full adder 27 in LSI L,1, L
Musical tone t# information generated in SI LL and LSIL2
The musical tone information generated within is added bit by bit serially and applied to the latch 26 via the transfer gate 0s26.

In addition, the carry output terminals Cot and IT of the full adder 27
A carry signal is output from , and applied to the latch 32 via the AND gate 31 . Note that this AND gate 311 is supplied with the output ID of the inverter 28, and at timing 0 to 4, the AND gate 31
is developed. The latch 32 performs a read operation at the clock φ1, and its output is applied to the carry input terminal CIN of the full adder 27.

In this way, the musical tone f generated by LSI Ll
i1m and the musical tone information generated by LSI L2 are added by the full adder 27, and when the resulting data is latched into the latches 11 to 26, the fil@ is sent to the latches 33 to 48 by the clock φ16 (described later). It is transferred in parallel and latched at the timing of .

The outputs of the latches 33 to 48 are then sent to the clock φL (described later) via transfer gates 034 to 04g.
The signal is applied to latches 49 to 64 that perform a read operation.

Note that timings 10 to 5 are supplied to the transfer gates 034 to 049, and only at timing 5, the contents of latches 33 to 48 are transferred to latches 49 to 64. At other timings, the transformers 7 (Gso to G64) connected to the outputs of the latches 49 to 63 are opened, and the voltage is applied to the input terminals of the latches 50 to 64 on the upper bit side, respectively. Become. In addition, the above transfer gate Qso~(
) 114 is supplied with a timing signal (m j15 inverted by an inverter 65).
The supplied FT# report must be shifted to +ljl (depending on the 9?1 value), in other words compressed, and output to the lunches 66-81.

The latches 66 to 81 are clocked by the clock φ! A read operation is performed at 6, and the output thereof is supplied to the terminal DoxDxs mentioned above. Note that the output of the latch 81 corresponding to the most significant bit part, ie, the sign bit, is inverted by the inverter 82 and applied to the output terminal D15. That is, the forming calculation process is performed by two's complement calculation in this embodiment, and the latches 66 to 81 (well, the maximum level (positive) is "01...IJ
So, the zero level is "0...0" and the minimum level (negative) is [
10...OiJ, and this inverter 821 provides a linear output characteristic. That is,
The maximum level is [11...IJ, the Z# level (ground level) is "lO...O", and the minimum level is "OO...
...01".

Next, the envelope data synthesis circuit will be explained. In LSI Ll, envelope 1-# information up to a maximum of 4f is synthesized simultaneously with the above-mentioned musical tone amplitude information.
Transformer 7 Agate 065~GEL marked) JU.

Note that this envelope data may be the original envelope data as it is as lπr'IKI, but it may also be done by adding only the upper bits. It is assumed that it is expressed in 7 bits (EO to E6). Although not shown, this envelope data is also used to generate the above-mentioned musical tone amplitude information dO to dz, and each musical tone is generated using the amplitude data of the original waveform and its amplitude data. It is obtained by multiplying the actual envelope data.

Therefore, the timing (No. 4 ()
15 is supplied as a gate signal, and timing j
15, the gate is opened and envelope data is supplied to latches 83-90.

Note that a signal multiplied by il"o' is applied to transformer 7Age) (hz).

These launches 83 to 90 perform a read operation at the clock φ2 (after %), and when the timing signal t15 becomes a 1'' signal, the transformer 7 agate 06
The output signals of 5 to G72 are read, but at other timings, that is, 10 to j14, the outputs of the latches 84 to 90 on the upper pin +- side and the addition output of the full adder 91 are largely transferred. ~Read through Qgo.Thus, this transfer gate G73~Ggo
The timing signal t15 is inverted and supplied as the gate number through the inverter 92. Therefore, at timings 10 to 4, transfer gates 0 and 3 to
Gs.

It is one thing to develop.

The output EO of the latch 83 is applied to one B input terminal of the full adder 91, and the human input field receives either serial data manually input from the envelope data input terminal hiNV (connected to line L2) or the AND gate. 93
It is marked through.

If the AND gate 93 is set as a master, a signal ``1''<d is applied to one end and opened, but if it is set as a slave, a signal ``01'' is applied 770 to one end and the gate is closed. Therefore, in this LSI Ll, the output of LSI L2 is sent to the full adder 91 via the AND gate 93.
supplied to

On the other hand, in LSI L2, the corresponding AND gate 93 is closed. However, since the master/sle number 118 inverted by the inverter 94 is supplied to the transformer 7 agate G81, the transformer 7 agate (J81) is opened and the output EO of the latch 83 is outputted via the terminal ENV◇ Note that one input terminal of the AND gate 93 and the input/output terminal of the transfer gate (Glml) are set to the ground level (0'' level) via the resistor H,2.

Therefore, the terminal ENV connected to line L2 is
In LSI Ll, L, SI L2 are used as input terminals.
In this case, the function is set as an output terminal, so the LSI
The full adder 91 in Ll serially combines the envelope information generated in LSILl and the envelope information generated in LSIL2 bit by bit, and marks the latch 90 via transformer 7age) G80. .

Further, a carry signal is output from the carry output terminal C0UT of the full adder 91 and applied to the latch 96 via the AND gate 95. Note that the output E of the inverter 92 is supplied to the AND gate 95, and the AND gate 95 is opened at timings LO to 4. The latch 96 performs a read operation at the clock φ2, and its output is applied to the carry signal CIN of the full adder 91.

In this way, the envelope data generated in LSI L1 and the envelope data generated in LSI L2 are latched in parallel by the full adder 91 at times 97 to 99 at the timing of clock φ16.

The outputs of latches 97-99 are input to decoder 103 directly and via inverters 100-102. Note that this decoder 103 consists of an /Amatrix circuit, and the output lines m1 to m4 of this decoder 103
．． The relationship between the outputs of ms and ms and the latches 97 to 99 is as shown in Table 1.

@Table 1 Note that in Table 1, X indicates that it may be either "0" or "1".
◇The AND gates 104 to 1071 are applied to one input terminal of the OR gates 108 and 109.
, 110 and a timing signal port S.

Note that this OR gate 108 has timing (4Jii
jto, z.

12. The output S is fed to the OR gate 109 and the timing signal 10. t1. 115 is supplied, and timing signals to and txs are supplied to the OR game 110. And this AND gate 104-107
The output of is supplied to OR gate 111, and AND gate 1
12 as the clock φL. Note that one bubble of this AND gate 112 has a clock φ.
! is supplied.

In this way, the clock φL output through the AND gate 112 is output as shown in Table 2.

Table 2 also shows lines ms, m11, from the decoder 103,
The data outputted through the latches 113 and 114 are read into the latches 113 and 114 by the clock φ16. And this latch 1
The outputs of terminals 80.13 and 114 are connected to terminals 80. The signal is applied to the amplifier 4 via Sl to determine the amplification factor.

For example, in the case of this embodiment, the amplification factor is as shown in Table 3.

Table 3 (Table 3) Next, the operation of this embodiment will be explained. FIG. 3 shows the clock and timing signals supplied to the electronic musical instrument of this embodiment, and the writing to the latches 11 to 26.32 described above is performed using the clock φ1 shown in FIG. 3(a). ,
Furthermore, writing to the latches 83 to 90.96 described above is performed using the clock φ2 shown in FIG. 3, 5). Then,
In addition to these latches, all of the latches mentioned above are shown in Figure 3 (
Successive output is performed one period after the clock φR shown in C).

Each circuit shown in Fig. 2 is to-wtxs (straw 3
(see figure (e))) is the basic cycle.
The m ff of each musical tone, the composite data of the 4 data, and the composite data of the envelope data have been determined by timing 115.

Therefore, at timing us (see FJ3 diagram (f)) 1, both LSI Ll and L2 are transformer 7Age h G 1 to G16, G6S-wG? 2, the notators are applied to the latches 11-26, 83-90i, respectively. Therefore, latches 11 to 26 have a clock φ
1, the data is latched into latches 83 to 90 at clock φ2.

Then, at the next timing jo~, the contents of the latches 11-26 are sequentially transferred to the full adder 27 and transfer gate G3 from the lower bit in synchronization with the clock φl.
3, and the contents of latches 83 to 90 are synchronized with clock φ2, starting from the lower bits.
J-order full adder 91 and transfer gate c) all
This will be supplied.

Therefore, in LSI Ll, the transfer game C)33 and Os1 are closed, and the anthogame
) 29.93 is opened, while in LSI L2f, transfer gates ) Gss and (J++x are opened, and ant gate) 29.93 is closed.

Therefore, the full adder of LSI Ll is 27.91+-!
, m1 is transferred serially from LSI L2
llIn data and envelope data, and LSILl
Calculate the m If, l data and envelope data generated by Ll.

The full adder 27.91 of LSI L2 simply outputs the data supplied from each B input terminal.

FIGS. 3(g) and (h) show changes in the data Do output from the latch 11 and data E output from the latch 83.
The graphs show the changes in O. Strain like this, L
In SU Ll, the data obtained by calculating the data of L, SI I, 1 and the data of LSI L2 are transferred to latches 33-48, 97-99 by clock φ16 shown in FIG. 3, 1dl. Read.

Then, the rounding rule value data read into the latches 33-48.97-99 and the envelope data (upper 3 bit data) are the following lo~[1! The data is held for a period of tMf1, during which the musical tone data is compressed.

That is, as shown in Table 2 above, the clock φL is output from the AND gate 112 based on the 3-bit data stored in the latches 97-99. The clock is also shown in FIG. 3 (ft). That is, no matter what the contents of the latches 97 to 99 are, FIG.
As shown in 1) to 1-4), the clock φL is output at timing ITS, and the outputs of the latches 33 to 48 are stored in the latches 49 to 64.

Thereafter, each time the output of the clock φL becomes ``1'', the contents of the latches 49 to 64 are shifted to the upper bit side. In other words, as can be understood from Table 42 and FIG. 3(i), if the envelope value is large, that is, if the contents of latches 99 to 97 are "1XX", no shift is performed; If the content is ro I XJ, then 1
After a bit shift, a 2-bit shift if it is [0OIJ, a 3-bit shift if the history is "000", the latches 49-64 hold their contents.

Then, at clock φ18, the resultant data shifted according to the size of the envelope value is latched into the latch 66.
~81 latches. At the same time, the latches 113 and 114 latch the 2-bit data supplied from the decoder 103 and output from the regular lines ms and mg.

In LSI Ll, the m1illA data from LSIL2, the envelope data file, 1.8
It is generated in I Ll, combined with 6 k #+1 data and envelope data, and output. That is, the 2-bit data representing the increase rate obtained from the envelope data is supplied to the NJ width transducer 41, and the amplitude data, which has been reduced by 1, is supplied to the DA frequency transducer 3, which converts the analog signal to After that, it is given to the above-mentioned triangular brocade 4.

As a result, in the amplification step 54, the amplification factor I'l shown in Table 3 is determined based on the data from the terminals SO, S, and the signal Δ is amplified. If the 2-bit data that determines the amplification factor is ro and OJ, then the clock φL will be
When t0 to 1151 and 4 shots and 6 shots are fired, the amplification rate is 1 times and output. Therefore, Fig. 4 (
a) As shown in Fig. 4(b), when the level of the signal output from the -A converter 3) changes,
In the OJ section, the signal at the level shown in FIG. 4(c) increases to III? 1'? It will be output from 54.

Then, the output level gradually increases, and when the above 2-bit data becomes 0.IJ, in other words, if the clock φL outputs three times from O to t15, the amplification factor is 2.
It will be output as double.

Therefore, the section ro and IJ shown in FIG. 4(b)1 is L
)-A conversion %3 output will be output at twice the level.

Thereafter, in the same way, each time the search rate changes, the range of the 1J-A converter 3 is changed four times, and the range is corrected, that is, expanded once.

Of course, the same control is carried out even when the debt becomes small.

Therefore, in the case of this actual flow example, there are two LSI Ll.

The synthesized musical tone output of L2 is compressed and expanded by the envelope data bottle and output as a musical tone signal.

Next, another embodiment of the present invention will be described with reference to FIG.

In this embodiment, the LSIs operating under the control of the CPU 201 are L8 I L3. L4. The configuration of each LSI L3 to L5 is exactly the same, and shift 1) is also the same as the LSI in the first embodiment 1.
It is the same as Ll, L2.

This LSI L3 functions to generate a 4fTt melody tone, and LSI L4 functions to generate up to 4 tones of melody tone or accompaniment tone by switching the fi control signal AUTO/MN.
functions to generate one base layer.

Note that the l, SI L5 has the ability to generate up to four sounds, but it is designed to produce only one bass sound.

A control signal is commonly supplied from the CPU 201 to these LSIL3 to L5 via the control bus C2. And Chip Select No. 18 C1~
If C3 becomes 11, the corresponding chip will be selected.

The control signal AUTO/MN is supplied to the master/slave terminal M/S of the LSI L4, and also to the AND gates 203 and 204 via the inverter 202. Musical tone information is applied from the LSIL 4 to the AND gate 203 via the terminal DA'rA, and envelope data is applied to the AND gate 204 via the terminal ENv. And anime game) 20
The output of 3 is connected to the terminal DATA of LSI L3,
The output of the AND gate 204 is LSI L3 (71,4
Connected to child ENV.

Also, LSI L4. L5 terminal 1) ATA.

ENV is connected. The master/slave terminal M/Sζ of the LSI L, s is supplied with the @0' ID signal. Therefore, this LSI L5 always has data 8.
It is set to be transferred to L8I L,i.

In addition, the master/slave terminal M/S of LSI L3
is always supplied with the @12 signal. Therefore, this LSI
L3 always synthesizes the signals given via AND gates 203 and 204 (sometimes a 1'01 signal), compresses the amplitude information, and sends it to L)-A converter 205.
At the same time, 2-bit data that determines the amplification factor is output from terminals So and St to the amplifier 206 to which the output of the L)-A converter 205 is supplied.

Similarly, amplitude data is supplied from LSI L4 to the D-A converter 207, and its output is converted to the 1st corner ratio determined by the 2-bit data supplied from LSIs 1 and 4 at the amplifier 208. #I1 width is then output.

Furthermore, the LSI La 1 directly sends a sample/hole once to the sample/hold circuit 209! Sampling clock power 1 is input to l3210 via AND gate 211.
(It will be supplied from the 74th child S/HCI, K.

These sample/hold circuits 209 and 210 are provided to prevent glitches in the D-A conversion output.The sample/hold circuit 209 samples and holds the output of the amplifier 206 and outputs it as a melody sound. A hold circuit 210 samples and holds the output of the amplifier 208 and outputs it as accompaniment sound (including bass sound).

Note that the sampling clock is supplied to the sample/hold circuit 210 only when the control signal A U i "O/M N given to the AND gate 211 is "1#".

Next one, this '31. The operation of the embodiment will be explained. Fourth
In the table, 1lliII J signal A U 'rO/M
This shows how the ↑toran of LSI L3 to L5 is set depending on the value of N KA''O' TE (F) LUKA ``1''.

Table 4 As can be understood from Table 4, the control signals At, I
If TO/MN is 'O', the data of LSI L4 will be transferred to LSI L3, and this LSIL3 will output it as an 8-tone melody sound. The CPU 20
From 1, for example, the musical tones corresponding to the 8 keys being pressed are L.
It is generated by assigning it to either SI L3 or L4. In addition, in AND gate 211,
Since the signal for opening the gate is not supplied, the sample/hold circuit 210 does not generate any sound, and no accompaniment sound is output.

In this case, LSI L3 is the musical tone generating means on the receiving side, and LSI L4 is the musical tone generator on the transmitting side.

On the other hand, 1tilJ aJ (14'r A U T○/
M N 71) 1 ” B, ts n, LSI L
The data indicating the base of 5 + f8 is transferred to LSIL4,
Data generated by LSI L41 and LSI L
It will be combined with the data transferred from 5 and output. Also, in this case, the AND gates 203, 204
Since LSI L3 is closed, only up to four melody tones are output. Therefore, musical tones corresponding to melody keys up to 4 tones are assigned to LSI L3 and generated and output, musical tones corresponding to keys up to 4 tones are assigned to LSI L4 and generated and output, and tones are assigned to LSI L4 to be generated and output. The musical tone (auto bass f) that is automatically selected and specified by the corresponding musical tone or key # key is LSI
It will be generated and output using L5i. Therefore, in this case, L8IL4 is the receiving side musical tone generating means, and LSI L5 is the transmitting side musical tone generating means.

Note that the LSIs L3 to L5 are supplied with 7p information from the CPLI 201 to generate musical tones with any timbre, and each LSI L3 to L5 is capable of generating musical tones according to that information. One thing is that you can make the tones of the notes, accompaniment sounds, and bass sounds different.

Although it is not shown in Figure 5, the melody sound and
There are two series of accompaniment sounds including bass sounds! When output as a signal, the sound can be independently controlled and suppressed for the output of the sample/hold circuits 209 and 210, and it is also possible to independently apply filters with different characteristics using external tone filters. .

In this way, the 4-chip, 3-chip LSIL 3 of this embodiment
By simply providing ~L5, it is possible to generate melody tones of the same tone up to a maximum of 8f, as well as 4-tone melody tones, 4f+ accompaniment tones, and 1-tone bass.

In the above embodiment, musical tones up to 4 f on one LSI were rarely generated by the time/minute processing, but it is of course possible to change the number of tones as appropriate.
In addition to the above embodiment in which data is transferred serially, it is also possible to transfer data between I and I in parallel.

Historically, in the above embodiment, each LSI is provided with a data terminal capable of input/output and a synthesis circuit, but it is also possible to separately configure an LSI having only a dedicated input circuit or output circuit. Of course.

Further, in the above embodiment, data is transferred between two chips and the data synthesis process is made possible in one chip, but it is also possible to make it possible to transfer data between many chips. In addition, in the above embodiment, the musical tone generation circuit is
Is it composed of chip LSI? -Since several chips are used in combination, LSIs can be mass-produced, and costs can be particularly reduced.

Furthermore, in the above embodiment, depending on the envelope data,
Although musical tone data (stripe width data) is compressed and expanded, it is not always possible to do so by reducing the number of bits of the waveform width data or by increasing the number of bits manually processed by the D-A converter. Of course, it is not necessary to perform the compression/expansion processing described above.

It goes without saying that various other modifications may be made to the method of data transfer between the tone generating circuits, the circuit materials, or the axis without departing from the gist of the present invention.

〔Effect of the invention〕

As described in detail above, the present invention separates multi-bit digital musical waveform information from the transmitting musical tone generating means into signals for each predetermined number of bits and transmits the divided signals to the receiving musical tone generating means. The musical tone generating means obtains the multi-bit digital musical sound waveform information from the transferred signal, synthesizes it with the multi-bit digital musical tone information generated by itself, and performs digital-to-analog conversion, so that the signal transmission line The advantage is that the circuit configuration is simple, and the bottom circuit is simple.

[Brief explanation of drawings]

1 to 4 show an example of the first embodiment of the present invention, and FIG. 1 (also a circuit block diagram of the same embodiment, 232
1 is a detailed view of the main parts of the same embodiment, FIG. 3 is a time chart of the same embodiment, FIG. 4 is a diagram showing changes in the d-power sound award of the same embodiment, and FIG. 5 is a diagram of the glue of the present invention ↓ 2 is a circuit block diagram showing a second embodiment; FIG. 1.201...CPU 3.205,207...D-A converter4. 206.
208...Increase 1il)ll device 27.91...Full adder 97-99...Latch 103...Decoder 49-64...Latch L1-L5...LaI3 Patent amount - Kajio Calculation Iso Stock company), cation (XI) 'O5l, (X2) "i 几(×4
) Figure 4

Claims (1)

[Claims] (1) A transmitting side musical tone generating means capable of generating multi-bit digital musical sound waveform information and transmitting the digital musical sound waveform information to the outside; Receiving side musical tone generating means capable of receiving and synthesizing digital musical sound waveform information transmitted from the transmitting side musical tone generating means with respect to the waveform information, and outputting the synthesized digital musical tone waveform information; a digital-to-analog converter connected to the generating means and converting the synthesized digital waveform information into digital-to-analog to obtain an analog tone signal; comprising a transmitting means for dividing information into signals of a predetermined number of bits and sequentially transmitting the signals to the receiving musical tone generating means, the receiving musical tone generating means transmitting the signals from the transmitting musical tone generating means. receiving means for receiving the divided signals received by the receiving means; and receiving means for obtaining the multi-bit digital musical sound waveform information from the divided signals received by the receiving means, and generating the multi-bit digital musical sound waveform information generated by itself. A digital electronic musical instrument characterized by having musical sound waveform information and means for synthesizing it.