JPS5936756B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument equipped with a variable frame key code generation circuit that shortens the scanning time of a closed key code.

Conventionally, in a device that has a large number of key switches, such as the keyboard of an electronic musical instrument, when information associated with the opening and closing of a switch is transferred to the required circuit, the amount of wiring would be enormous if you tried to connect each switch directly to the circuit. It is uneconomical.

Furthermore, if a semiconductor integrated circuit or the like is to be used, the number of pins will be too large, making it difficult to use as it is. Currently, in view of this point, all switches are scanned for a predetermined period of time, and pulses are generated at the time points corresponding to the turned-on key switches in the time sequence according to the scan, and a pulse is generated between a large number of switchers and the required circuits. A method is being considered to save on the number of connections.

For example, a key code multiplexing method is generally used that scans each key switch in a time-division manner and sends information about turned-on switches as a TDM (time division modulation) signal or a PCM (pulse code modulation) signal. However, since the time required to scan all the key switches is fixed, a fixed scanning time is required even when only a few keys are turned on, resulting in waste.
The number of key switches that are turned on at the same time when playing a normal keyboard instrument is 11 keys, taking both hands and feet into consideration.

Now, if we consider one octave as one octave, it is impossible to press more than two octaves with one hand, and from this, five octaves is the maximum number that can be occupied at the same time. Therefore, the keyboard switches are divided into a plurality of blocks and scanned, and if even one switch is turned on, scanning is stopped at that point to detect the on switch. Since blocks without on switches are passed through, it is possible to shorten the time required for one scan to obtain information on turned on switches. SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic musical instrument having a key code generation circuit that reduces the time required to scan all key switches.

In order to achieve the above object, the electronic musical instrument of the present invention divides a plurality of switches each having a contact point to be closed into blocks.
means for sequentially scanning a plurality of blocks with a clock; and priority selection for sequentially selecting and outputting the closing information of the sweeteners in each block according to a predetermined priority order, starting from the information with the highest priority each time the second clock is input. a circuit, means for inhibiting the first clock and temporarily stopping the block scanning according to an operation signal when the priority selection circuit is performing a priority selection operation; and information on the output of the priority selection circuit and block head scanning; means for converting into binary code key data, and means for detecting the end of block scanning for all the blocks at one time, and skipping the key switches that are not closed in one scanning block and converting the time slots and closed key switches of the total number of blocks. The present invention is characterized in that it comprises a key code generation circuit comprising means for outputting a variable frame signal whose one frame time is determined by the sum of a number of times and a time cut.

The present invention will be described in detail below with reference to examples. First, an outline of an embodiment of a novel electronic musical instrument to which the present invention is applied will be explained, and then details of an embodiment of a key code generation circuit, which is the main part of the present invention, will be explained.

An electronic musical instrument to which the present invention is applied does not use the conventional method of synthesizing pure sine waves, but uses a method of synthesizing square waves weighted by coefficients, and by combining this with a digital filter with appropriate coefficients. A desired musical tone can be realized with a small number of constituent waveforms.

To give an overview of its principle and structure, musical tones can be generated using a periodic waveform h (
t), it is expressed by an expansion formula of a Fourier series.

Here, if we take up to the 30th overtone and sample it every τ time, it is expressed as.

If this is to be time-divided and the waveforms of up to 30 harmonics are calculated in synchronization with the musical tone, and eight tones are to be produced simultaneously, a 2 kHz musical tone requires a minimum clock of 28.8 MHz. For this reason, it is possible to lower the frequency to about 7.2 MHz by suppressing harmonics in the high frequency range, but the circuit to realize this is still complicated and it is still difficult to integrate the circuit. Therefore, although it is basically equivalent to a sine wave synthesis method, we thought of using a square wave synthesis method instead of a pure sine wave and utilizing harmonic distortion.

In other words, to create a low-order sine wave, apply a strong filter to the square wave, and to create a medium-order sine wave, apply a weak filter to generate harmonic distortion.
By approximately supplementing a high-order sine wave, it is attempted to synthesize a square wave with 1/2 or less of the conventional sine wave with up to 30 harmonics. SQU square wave
(NT), AISQU(ωT),
A2SQU(ωT) ,・・・・・・,ANSQU(
If a weighted waveform ωT) is generated and a filter is applied to each of them, the lower the order, the stronger the filter, the output waveform will be extracted.

For example, if you try to synthesize square waves up to N=10, 1
Waveforms up to the 10th harmonic are almost completely reproduced. Next, the harmonics output due to harmonic distortion are 12, 15, 18,
..., 30 overtones and many overtones are generated, and if the factors that determine the timbre of a musical tone are up to about 10 overtones, the desired musical sound waveform can be approximately realized. That is, whereas conventional sine wave synthesis required synthesis of up to 30 harmonics, it is now sufficient to synthesize up to 1/3 of the 10th harmonic. This requires a clock frequency of about 2.4 MHz. In order to further reduce this frequency, K, H,...
・It is clear that it can be lowered. FIG. 1 is an explanatory diagram showing the configuration of an embodiment of an electronic musical instrument of the present invention based on the above-mentioned principle. In the figure, 1 is a keyboard, and a key switch with a 61-key make contact switches 1 octave and 12 keys to 1.
It is divided into six blocks. That is, they are arranged in a matrix of 12 rows and 6 columns. Each key information is scanned for each block by the key code generation circuit 2, and for a block in which a key is turned on, block scanning is temporarily stopped until the key information in that block is sent out. Furthermore, the key information in the block is also selected and output in sequence according to the priority order specified for the keys that are turned on, and the required time slots are limited to the number of turned-on key switches and the number of blocks; for example, when five keys are pressed, If so, one scan time slot is 5+6=1
There is only 1. This key-on information is output as a binary encoded key code corresponding to each key switch, and is given to the key code data assigner 3 together with a frame signal indicating the end of one scan. The key code data assigner 3 has a maximum of eight channels for simultaneous sound generation, and performs high-speed time division operation in which one time slot of the key code data is divided into eight. Furthermore, all control operations of the key code data assigner 3 are performed at the time of frame signals, and include envelope control signals such as content presence/absence signal (BWS), release signal (RS), fast release signal (FRS), envelope end signal (EES), etc. is given to the envelope generation circuit 4, and key code data KCD, which is frequency information, is given to the N-order square wave generation circuit 7. The envelope generating circuit 4 is composed of a cyclic digital filter, and outputs desired envelope waveform data by controlling an input signal and a filter constant that determines filter characteristics, and inputs the data to a multiplier 9. Square wave generation circuit 7 has key code KC
By accumulating the angular velocity information read out by D, a square wave signal SQU(N) with a period T/10, which is 1/10 from the square wave signal with a basic period T, is generated in a time-division manner within one channel time slot. . On the other hand, the square wave level memory section 6 that determines the sound calculates the square wave level specified by the tablet switch/drawbar switch 5, and reads out the level coefficient value AN from the square wave level memory section 6 in synchronization with the above square wave signal. It will be done. This level coefficient value AN is an N-order square wave ANSQUOS! which is inverted gated and weighted by the square wave signal SQU(N). ) is input to the digital filter unit 8 in a time-division manner. This digital filter section 8 is composed of a cyclic digital filter, and the reading of filter constants that determine filter characteristics is read out and controlled according to each scale and each order, and the input signal ANSQU (N) is filtered respectively, and the FNCANSQU (N)] is output in a time-division manner and input to the multiplier 9. In this multiplier 9, an envelope is added independently to each channel and each order. The output of the multiplier 9 is an accumulator (ACC
) 10 for each order, and further for each order, the waveform h(t) for each sample is input to the D/A converter 11, and a musical tone is output via the acoustic system 12. Ru. FIG. 2 shows the basic timing waveform of the electronic musical instrument shown in FIG.

φo is a master clock and has a frequency of 2.4 MHz. φ
101 to φ110 are time slots for generating square waves.
It is time-divided into 0 time slots, and 1 time slot is 1/2400 ms (millisecond). (1) 21~
φ28 is time-divided into 8 channels corresponding to the time-division key code data TKCD output from the key code data assigner 3, and one time slot is 1/240 ms.
It is. Further, the operating speed of the key code generation circuit 2 is a time slot of 1/30 ms for one key, and all the circuits perform time-division operation at this timing. Figure 3 is the second
A clock generation circuit included in the square wave generation circuit 7 of FIG. 1 is shown for generating the basic timing waveform shown in the figure. The master clock oscillator 7-1 is a 2.4 MHz clock φ. is output and input to decimal counter J and input to decoder 6.
-2 outputs timing clocks φ101 to φ110. Next, the output pulse φ1 of the counter J to Q is input to the octal counter J to R, and the decoder J to S outputs timing clocks φ21 to φ28, and the counter J to R outputs the pulse φ.
2 is output and used for each function. FIG. 4 is a detailed explanatory diagram of an embodiment of the surcode generating circuit which is a feature of the present invention in the electronic musical instrument shown in FIG.

In the figure, the key switch matrix 1 is composed of 61 make contact switches, and is divided into six octave blocks, with one block being 12 blocks per octave. The clock .phi.23 is applied to a modulo hexadecimal counter 2-1 via NORl, and the output of the counter 2-1 is input to a decoder 2-2 to scan the key switch matrix 1 for each block. The key data ND output from the key switch matrix is input to the priority selection circuit 2-3. If any key switch is turned on, the key data ND is sequentially outputted one by one by the aforementioned clock φ21 in accordance with a predetermined priority order, inputted into the note code memory 2-4, and note code data NCD is sequentially output. While the selection is being output, the priority selection circuit 2-3 outputs the signal PSS,
Input "'1"" to the NOR circuit NORl and counter 2-1
Pause the operation. When all the turned-on key information is output, the signal PSS becomes "0", and the aforementioned clock φ23 is input to the counter 2-1 via NORI to scan the next block. In this way, the key switches are sequentially scanned while the block scan is temporarily stopped. Further, the output of the counter 2-1 is input to the latch circuit 2-5, and is latched by the clock φ21, so that the timing with the note code data NCD output from the note code memory 2-4 is determined. This output is input to gate 2-6 and the signal PSS
, and octave code data 0CD is output. Note code data NCD and octave code data 0CD will be collectively referred to as key code data KCD. Next, the octave chord is “'110” (1
The frame detection circuit 2-T detects when the signal PSS outputted from the priority selection circuit 2-3 becomes "0" and outputs the frame signal FS.
The figure shows a detailed circuit example of the key switch matrix 1 of the embodiment shown in FIG.

The two sets of bus lines 0DI to 0D6 and ND, to NDl2 are each grounded via a resistor.

Also, at the intersection of the two sets of bus lines, 61 of the key switches 0, N, ~06N12 are connected via diodes.
pieces are connected. Bass line 0D indicating octave
~0D6 are sequentially scanned, the bus lines NDI to NDl of the key switch whose octave block is turned on are scanned sequentially.
Outputs “1” to either of 2. This output is given to the priority selection circuit 2-3. FIG. 6 shows a detailed circuit example of the priority selection circuit 2-3 in the embodiment of FIG. 4.

The input note code data signals NDI to ND, output from the key switch matrix 1 in each block are input to AND circuits Al-Al2, respectively. Initially, if the input signals NDI and NDl2 are "1", and the Q outputs of flip-flops DF, -DFl2 are "o", the OR circuits 0R13 to 0R24 all output "o", The inverted output “1” is the AND circuit A1 to Al2
is being entered. Next, the input signal NDI becomes "o", the u-AND circuit A1 outputs "0", and the OR circuit 0RI becomes "0".
'' is output, and the inverted output "1" is input to the AND circuit A2.The input signal ND2 becomes "1", and the AND circuit A
2 inputs “1” to the OR circuit 0R2, and the OR circuit 0R
2 to 0 RII all output “1”, and the inverted input ““0”
' is input to the AND circuits A3 to Al2, and the input signal ND
3~ND,2 is prohibited in AND circuits A3~Al2, and only A2 among AND circuits A1~A1ze is
” and others output “”o” and the flip-flop D
It is input to FI-DF,2. Next, only the flip-flop DF2 outputs "1" by the clock φ21.
This output inhibits the gates of AND circuits A2 and Al via OR circuits 0R14 and 0R13. As a result, the OR circuits 0R2 to 0RII output "o", and the AND circuit A
3~Open Al2. Therefore, the input signal NDl2 is then applied to the flip-flop DFl2 via the AND circuit A,2, and only the flip-flop DF,, operates to output "1" by the next clock φ2.
This output is input to the AND circuits A1 to Al2 via the OR circuits 0R24 to 0R13 as inverted outputs ″0'ι, and inhibits the input signals ND, ~NDl2.Therefore, the next clock φ21 causes the flip-flops DF, ~DF, 2 is '''
Output o''. During the above operation, the output signal PSS of the OR circuit 0R3 outputs "1" while the selection signal is being output, and outputs "o" when all outputs are completed. In this way, those input signals NDI-ND2 that are "1" are sequentially selected and output according to a predetermined priority order.The time slots required for this purpose are only two time slots in the above example. The output signal of this priority selection circuit 2-3 is given as an address signal of the note code memory 2-4.
FIG. T shows a detailed circuit example of the frame detection circuit in the embodiment of FIG. 4. When the output 3-bit count value of the modulo hexadecimal counter 2-1 reaches "110," it is latched by the timing adjustment ratchet circuit 2-5, and "1" is output from the AND circuits A and 3. In addition, the signal PS
When S becomes “0”, the AND circuit Al4 outputs “1”.
' is output. This output is referred to as a frame signal FS.
FIG. 8 is a timing diagram showing the operation of the key code generation circuit of FIG. 4.

Now switch 02N1, 02N5, 02N10, 04N
3,04N5,06N8 (7) 0 after 6 keys are turned on
Consider the case where 4N3 and 06N8 are turned off. Counter 2-1 in FIG. 4 is counted by clock φ23 in FIG. 4b.

When the counter 2-1 reaches the second octave of the key switch matrix 1 as shown in FIG. Note codes (NC) in Figure d are sequentially selected and output with priority. At this time, the signal PS.S becomes 1'''' and is input to NOR1, inhibiting the clock φ23 shown in FIG. Note code (NC) stored in note code memory 2-4 from priority selection circuit 2-3
is indicated by the binary code h in the figure. In this case, the octave code (0C) shown in FIG. 3E is obtained by timing the output of the counter 2-1 with the clock .phi.,1, and the two-octave block becomes a long time slot, which is indicated by the binary code shown in FIG. Key code data KC consisting of this NC and 0C
When the output of D is completed, the signal PSS becomes 1'', and the clock φ23 is inputted to the counter 2-1 again to scan the next octave block.In this way, when one scan is completed, that is, at the 6th octave, the PSS signal is output. When the value becomes ゜O'', the frame detection circuit 2-7 outputs a frame signal FS consisting of one time slot. In the next frame signal, as shown in the figure, the second key is turned off, the second octave remains unchanged, the fourth octave becomes the first key, and the sixth octave disappears, leaving a total of four keys. Therefore, when 6 keys are pressed, the time slots in one frame are 6 + 6 = 12, and when 4 keys are pressed, there are 4 + 6 = 10 time slots, and so on, depending on the number of keys pressed. A so-called variable frame method is constructed in which the frame rate changes. In this case, the key code data KCD consisting of NC (50C) is gated by the PSS signal and is output only at the required time slot.As explained above, according to the present invention, a plurality of The switch is divided into a plurality of octave blocks, a first clock sequentially scans the plurality of blocks, and a second clock sequentially selects and outputs the closing information in each block according to a predetermined priority order,
While this priority selection signal PSS is present, the first clock is inhibited and block scanning is temporarily stopped.

A frame signal pulse consists of one time slot, and one frame time constitutes a variable frame consisting of time slots equal to the number of blocks and the number of closed key switches. In addition, while the previous proposal used one clock and a ring counter as a means for temporarily stopping block scanning, the present invention uses two clocks, a counter, and a latch circuit provided from the latter stage to simplify the configuration and , these are synchronized and adapted to the later stages of electronic musical instruments. In any case, the time required for one scan can be significantly reduced compared to the time required to scan all the key switches in the conventional TDM or PCM system. Furthermore, wiring can be reduced, and the problem of the number of pins in a semiconductor integrated circuit can therefore be eliminated, allowing for easy integration.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration explanatory diagram of an embodiment of an electronic musical instrument of the present invention;
2 and 3 are basic timing waveforms used in the electronic musical instrument shown in FIG. 1 and their generation circuits, FIG. 4 is an explanatory diagram of an embodiment of the key code generation circuit shown in FIG. 1, and FIGS. 4 is a detailed circuit example of the main part of the embodiment, and FIG. 8 is an operation waveform diagram of the embodiment of FIG. 4, in which 1 is a key switch matrix, 2 is a key code generation circuit, 2- 1 is a counter, 2-2
is a decoder, 2-3 is a priority selection circuit, 2-4 is a note code memory, 2-5 is a latch circuit, 2-6 is a gate circuit, 2-7 is a frame detection circuit, 3 is a key code data assigner, 4 5 is the envelope generation circuit, 5 is the tablet
A drawbar switch, 6 a square wave level memory section, 7 a square wave generation circuit, 8 a digital filter section, 9 a multiplier, 10 an accumulator, 11 a D/A converter, and 12 an audio system.

Claims (1)

[Claims] 1 Means for dividing a plurality of switches having contacts to be closed into blocks and sequentially scanning the plurality of blocks with a first clock, and selecting closing information of the switches in each block from high priority information according to a predetermined priority order. A priority selection circuit that sequentially selects and outputs a second clock every time it is input, and when the priority selection circuit is performing a priority selection operation, the first clock is inhibited by the operation signal and the block scanning is temporarily stopped. means for converting the output of the priority selection circuit and block scanning information into binary code key data;
Detecting the end of block scanning for all blocks in one scanning block and skipping unclosed key switches in one scanning block, one frame time is determined by the sum of the time slots for the total number of blocks and the time slots for the number of closed key switches. An electronic musical instrument comprising a key code generation circuit comprising means for outputting a determined variable frame signal.