JPH05134673A - Electronic musical instrument - Google Patents

Abstract

PURPOSE:To polyphonically generate different musical tones at every compass, and to generate a musical tone being similar to natural instrument by storing waveform information at every compass, and reading out different waveform information by a time division at every compass to which a depressed key belongs. CONSTITUTION:Octave codes from channels 21, 22 are inputted by a time division to an octave selecting circuit 23 through gate circuits 31, 32 and decoded, given into a memory circuit 20, and a memory area of waveform data of the corresponding compass is designated by a time division. Also, sound name codes from the channels 21, 22 are inputted to sound name selecting circuits 41, 42 and a clock signal of a frequency corresponding to the sound name code is outputted, and it is inputted to address counters 61, 62 through waveform forming circuits 51, 52 and counted, and it is applied by a time division to the memory circuit 20 and plural waveform data are read out in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument for reading out waveform information of a tone range corresponding to a key depression signal and processing it to obtain a tone waveform having a frequency corresponding to a key.

[0002]

2. Description of the Related Art Recently, in a tone generator of an electronic musical instrument, one cycle of a required musical tone waveform is stored in advance in a waveform memory circuit, and the waveform stored in the waveform memory circuit has a repetition cycle proportional to the scale frequency. A method has been proposed in which a musical tone waveform of each scale frequency is obtained by reading with a sound source clock signal.

According to this method, when it is attempted to faithfully reproduce a complicated musical tone waveform, especially a natural musical instrument sound, the memory capacity of the waveform memory circuit becomes large. Conventional 1 key 1
When the above-described sound source device is configured by the generator system, the device itself becomes large and complicated. Therefore, in order to simplify the former, the present applicant has proposed a new method in Japanese Patent Application No. 49-105861 (Japanese Patent Publication No. 55-2640) and Japanese Patent Application No. 49-139935 (Japanese Patent Publication No. 53-5544). In these methods, the required tone waveform is linearly approximated by
One cycle is complicatedly divided into unequal intervals (49-105861) or equal intervals (49-139935), and the slope and amplitude change of the waveform and time information (49-10586) in each section are divided.
The data of 1) may be stored in the memory. For this reason, the memory capacity can be reduced step by step, and since the number of quantization steps can be increased with a small memory capacity, there is an advantage that quantization noise can be reduced.

Although the sound source devices shown in Japanese Patent Application No. 49-105861 and Japanese Patent Application No. 49-139935 described above are advantageous for reproducing a natural musical instrument sound almost faithfully, they want to play a plurality of sounds at the same time. In order to achieve the peculiar wishes of electronic musical instruments, it is necessary to further provide a plurality of the above-mentioned waveform memory circuits, resulting in an enormous number of devices.

Therefore, Japanese Patent Application No. 50-796 relating to the present applicant
No. 73 (JP-A-52-3421, JP-B-57-551)
No. 75) made a new proposal. That is, according to this method, one cycle of a desired tone waveform is divided into a plurality of pieces, information of the slope and amplitude change of the waveform in each divided section is stored in memory, and the reading means information is read in a time-division manner. Waveforms having different frequencies can be simultaneously obtained based on one piece of waveform formation information. In this way, it is possible to generate a plurality of sounds simultaneously without increasing the memory capacity.

Further, according to Japanese Patent Application No. 50-96035 (Japanese Patent Application Laid-Open No. 52-45322, Japanese Patent Publication No. 57-38920), which is also proposed by the present applicant, a key-depression transmitted by an encoded digital signal, An improvement proposal was made for a key assigner that distributes a key release signal to a sound source circuit that requires it. On the other hand, in the case of a natural musical instrument sound, the musical tone waveform generated thereby has a frequency spectrum included depending on the musical range, that is, the waveform differs depending on the musical range, and it is possible to simply approximate it with one musical tone waveform. There is a problem that is difficult.

An object of the present invention is to provide an electronic musical instrument provided with a sound source device capable of faithfully reproducing a natural musical instrument sound in consideration of the fact that the frequency waveform of the musical tone waveform changes depending on the tone range.

[0008]

In order to achieve the above object, the electronic musical instrument of the present invention stores waveform information with a different number of words for each musical range, and outputs a plurality of address signals according to key note names. In addition, one to a plurality of memory means of the plurality of memory means are designated in a time division manner according to the tone range to which the pressed key belongs, and the waveform information is designated by the designation of the memory means and the address signal from the address signal generating means. Is read out in a time division manner.

Therefore, since the musical tone waveform can be formed polyphonically corresponding to each musical range, a more natural musical instrument sound can be reproduced.

[0010]

1 is an explanatory view showing the configuration of an electronic musical instrument using a key assigner having two channels to which the present invention is applied. I won't go into details about this key assigner,
It is desirable to apply a key assigner such as Japanese Patent Application No. 50-96035 (Japanese Patent Laid-Open No. 52-45322) filed by the same applicant as the present application.

In FIG. 1, the key signal of the keyboard 1 is assigned to two channels. The key information from channels 2 ₁ and 2 ₂ has a note name code of line L1-1 and an octave code of L2-.
1, the key release information is indicated by the line L3-1. The last key depression / release information is information indicating whether or not the key assigner has captured the key depression by the keyboard operation.

Of the sequence pulses T1 and T2 generated by the sequence pulse generator 18, the sequence pulse generator 18 is operated by the clock from the time division clock generator 17.
The data time-division by the gate circuit 3 ₁ octave code from channels 2 ₁ applied to the gate circuit 3 ₁ ordering pulse T1 via line L7-1, it gives the octave selection circuit 23 via the octave bus line L3.

The octave selection circuit 23 is composed of a decoder circuit, and operates the memory of the number of words corresponding to the musical range shown in the memory circuit 20 described below. In the memory circuit 20, one cycle of waveform data is prepared for each octave in the number of words corresponding to the octave. That is, the memory address of each range in which the number of words is changed is designated by the output from the sound source device 26 ₁ , as shown in FIG. The number of bits of the supply line from the sound source device in this case is also shown.

In order to fully understand the sound source device applied to the present application, reference is made to the aforementioned Japanese Patent Application No. 50-79673 (Japanese Patent Laid-Open No. 52-3421). The present invention discloses a technique in which an electronic musical instrument capable of simultaneously producing a plurality of sounds does not have a waveform data memory for each sounding channel but uses the waveform data memory in a time-division manner and commonly used for each channel. As a waveform forming method, a technique is disclosed in which one cycle of a tone waveform to be processed is divided into a plurality of sections, and information about the slope and amplitude change of the waveform in each divided section is stored in memory to obtain a desired tone waveform.

The sound source device 26 ₁ of FIG. 1 in the present application is disclosed in Japanese Patent Application No. 50-79673 (Japanese Patent Application Laid-Open No. 52-3421).
No.) is applied. Accordingly, the sound source device 26 first latch circuit 8 ₁ in ₁ of the present FIG 1, the gate circuit 9 ₁ configuration, the pitch name selection circuit 4 _1, the waveform forming circuit 5 _1,
Since the address counter 6 ₁ and the second latch circuit 7 ₁ operate asynchronously with the time division timing by the sequential pulse generator 18, the data from the address counter 6 ₁ is stored in the gate circuit 9 ₁ by the time division timing. The waveform data that is supplied to the circuit 20 and read from the memory circuit 20 is latched in the first latch circuit 8 ₁ at time division timing, and the latched data is supplied to the second latch circuit 8 ₁ at the operation timing of the waveform forming circuit 5 ₁ . The configuration is such that it is latched by the latch circuit 7 ₁ and waveform data is supplied to the waveform forming circuit 5 ₁ .

Further, the waveform forming circuit 5 ₁ of the present application, as shown in Japanese Patent Application Sho 50-7963 (JP 52-3421), it is desirable that the configuration at the rate multiplier and the up-down counter .. Further, the address counter ₆₁ of the present application, counts the pulses output per one operation cycle aforementioned rate multiplier operates, is preferably a multi-bit counter, the memory circuit 20 by the address counter ₆₁ To generate an address for reading.

The waveform data read from the memory circuit 20 by this address is, for example, 1-bit waveform slope information for determining rise and fall of the waveform slope, and an amplitude consisting of a plurality of bits for determining the degree of slope. It consists of change information. The information on the amplitude change is obtained from the difference between the sample points when the musical tone waveform is sampled at a plurality of sample points.

[0018] The information in this amplitude variation rate is supplied to the multiplier, the pulse train of the clock signal from the sound name selection circuit 4 ₁ supplied to the other input of the rate multiplier to, controlling the pulse density .. In other words, the amplitude change information is converted into pulse density.

The up / down counter determines whether to count up or down according to the slope information of the waveform, and tilts substantially linearly by counting the pulse train of the pulse density controlled by the rate multiplier. Create a waveform. When the address indicated by the address counter 6 ₁ is advanced, the waveform data stored in the memory circuit 20 is sequentially read out in accordance therewith, and the above operation is repeated to form a linear tone waveform.

[0020] Returning to description, pitch name code L1-1 is given by the channel 2 ₁ to tone name selection circuit 4 _1, selects the pitch name clock corresponding to the pitch name code of the clock frequency from the master oscillator 14 .. Assuming that the master generator 14 has a range of 61 keys C2 to C7 in FIG. 5, m × n ×
12 corresponding to the frequencies of (C7 to C6 # scale frequency)
Twelve clocks corresponding to the scale are generated. Where m
Is the number of memory words corresponding to the highest pitch range (C7 to C6 #) as shown in FIG. 5, and n is the next waveform forming circuit 5 ₁
In other words, the number of clocks in one operation cycle of the rate multiplier described above is selected, and the clock selected by the note name selection circuit 4 ₁ is divided by n by the waveform forming circuit 5 ₁ , and the address counter 6 ₁ receives the clock. Given.

Since the address counter 6 ₁ has m = 4, that is, the number of memory words in the highest tone range is 4 words from FIG. 5, and C2 of the lowest octave is 32 m words, 4 × 32 = 128, which is a 128-base number. It suffices if it is configured by counting, and counting is performed by the clock from the waveform forming circuit 5 ₁ divided by n described above. It gives the address of the address counter ₆₁ to the gate circuit 9 _1. At this time division clock T1, the address counter 6 ₁
Address is time-divided and is given to the above-mentioned memory circuit 20 through the address bus line L5 together with signals of other channels.

The address counter 6 synchronizing pulse generating circuit 10 ₁ that branches an output of _1, the address counter 6 ₁
For example, when the value of the address counter 6 ₁ is 0 for each cycle, one pulse is generated and supplied as a synchronizing signal to the synchronizing circuit 24 described later. This synchronizing signal is used for ensuring the initial operation of waveform formation, and in the sound source system such as Japanese Patent Application No. 50-79673 (Japanese Patent Application Laid-Open No. 52-3421) applied to the present application, when the waveform is formed, It is necessary to form a waveform from the beginning of a set of waveform data corresponding to a desired musical tone waveform.

For example, when the performer switches the tone color tablet while pressing a key, the address counter 6 ₁ does not always indicate the head address of the memory and is not specified. Similarly, the value of the up / down counter is also undefined.

In this case, the operation of the waveform forming circuit 5 ₁ is such that the waveform data of the address indicated by the address counter 6 _{1 of the} memory corresponding to the new tone color tablet is read and new waveform data is added to the value remaining in the up / down counter. Since the pulse counting by is started, the zero cross point of the previous waveform may not match the zero cross point of the new waveform. This causes the waveform to cause DC fluctuations,
In extreme cases, the waveform will overflow.

In order to prevent this, when the tone color tablet is switched, the waveform data in the memory is not immediately changed, but the waveform data is set to the next new value in accordance with the point that the waveform value always becomes zero. It is sufficient to switch to waveform data of a different tone color tablet. In other words, this problem can be solved by receiving the tone color tablet signal in synchronization with the start point of one cycle of the formed musical tone waveform. Therefore, since one cycle of the address counter 6 ₁ corresponds to the cycle of the tone waveform, it is preferable to start the waveform formation according to the generation of the synchronizing signal.

Further, the complement circuit 19 stores the half cycle of the waveform in the memory circuit 20 and repeatedly reads the waveform data of the half cycle to perform the same operation as the case of storing the data of one cycle. The complement circuit 19 may be used if necessary.

In this way, the memory address is designated according to the address counter 6 ₁ . That is, the octave code causes the octave selection circuit 23 to select which memory portion in the memory circuit 20 should operate. That is, since the memory designation of the number of words corresponding to the musical range shown in FIG. 5 is made by the octave selection circuit 23, the memory portion of the number of words corresponding to the octave is time-division clocked by the address from the address bus line L5. It is read at the timing of T1.
In this case, the relationship between the memory portion in the memory circuit 20 and the number of bits supplied from the address counter 6 ₁ increases as the octave sequentially decreases as shown in FIG.

Explaining FIG. 5 in more detail, the range C
The memory part corresponding to 2 is supplied with X, ie all bits of the address counter 6 ₁ , eg all 7 bits. Regarding the memory section corresponding to the range C2 # to C3,
The supply bits from line L5 and the memory section are combined so as to supply the 6 bits of the address count 6 ₁ excluding the most significant bit. Similarly, with respect to the memory parts corresponding to the tone ranges C3 # to C4, the supply bits from the line L5 are connected to the memory parts so that 5 bits except the most significant 2 bits of the address counter 61 are supplied. Similarly, the memory bits for each range and the bits supplied from the line L5 are combined.

Here, the address counter 6 ₁ operates at the same counting speed even if the octave is different as long as the key name of the key is the same. In the case of the tone range C2, when the count of the address counter 6 ₁ operates from 0 to 127, one cycle of the tone waveform of C2 is formed. Next range C
For 2 # -C3, the address counter ₆₁ is tone waveform one cycle of this frequency range is formed when operating 0 to 63. When the address counter 6 ₁ carries out the operations of 64-127, the same operation as the above-mentioned operations of 0-63 is carried out because the most significant bit of the address counter 6 ₁ is not supplied to the memory portion corresponding to this range. ..

Therefore, one cycle of the musical tone waveform in the range C2 # to C3 is formed in half the time when one cycle of the musical tone waveform in the case of C2 is formed. Since the number of words in each memory portion is halved each time the octave goes up, it is possible to obtain a musical tone of a frequency corresponding to a key depression with a desired number of words according to each octave.

Returning to the explanation of the operation, the time division timing T1
The waveform data read out from the memory or the color 20 is supplied to the adder circuit 22 via the gate circuit 21. When the gate circuit 21 is the key in the channel 2 ₁ is captured, the output signals from the synchronizing circuit 24 at the timing of the division clock T1 when the corresponding is supplied to the gate circuit 21, the waveform data from the memory circuit 20 Output.
For convenience of description of the synchronization circuit 24, the synchronization circuit 24 will be described with reference to FIG.
The above configuration is provided for each channel. In the case of FIG. 4, only one channel is shown, and other channels have similar configurations, but they are not shown. This detailed operation will be described later, but it is composed of a synchronizing circuit 24 ₂ and a gate circuit 24 ₁ .

The above-mentioned synchronizing circuit 24 ₁ is a tone color tablet 25 (in the case of FIG. 4, signals of two tone color tablets S25B and G25C are shown, but normally, it corresponds to the number of tone colors that can be generated). how the on-off signals of the tone tablet switches tone to indicate whether to generate, receive from the line L2-1 of the key depression and key release information from the channel 2 ₁ from. Further, the synchronizing signal from the synchronizing pulse generating circuit 10 ₁ corresponding to the channel 2 ₁ is given to the synchronizing circuit 24 ₂ via the line L6-1. The synchronizing circuit 24 ₂ is composed of a D-type flip-flop, and when the key is assigned to the channel 2 ₁ , the clearing is released by the key release information from the line L 3-1. Tone tablet 2
The ON / OFF signal of 5 is given to the D terminal of the D flip-flop, and when the synchronizing signal from the line L6-1 is given to the clock terminal, "1" is written in the flip-flop, The output "1" is given to the gate circuit 24 ₁ .

In the case of FIG. 4, the AND gates 24 _2-3 and 24 _2-4 are used to implement the coupler, and the tone color tablet 25 is used.
And the D flip-flops 24 _2-5 and 24 _2-6 , but normally this AND gate is not necessary. In the case of FIG. 4, the synchronizing pulses input to the clock terminals CK of the D flip-flops 24 _2-5 , 24 _2-6 are L6-1-G, L
It is 6-1-S, but L6-1 can be commonly input. The gate circuit 24 ₁ includes a sequential pulse generator 18
From the line L7-1 to the channel 2 _{1 and the} time-division clock T2 from the line L7-1 to the channel 2 ₂ respectively, and the time-division clock T1 corresponding to the assigned channel 2 ₁ is supplied. The output 1 of the D flip-flop described above is applied to the gate circuit 21 via the gate circuit 24 ₁ at the timing of. Synchronization circuit 24 ₂ and gate circuit 24 ₁ for channel 2 ₂
Although not shown, the outputs of the gate circuits 24 ₁ corresponding to the channels 2 ₁ and 2 ₂ may be ORed and supplied to the gate circuit 21.

Its peripheral circuits, including the memory circuit 20, are illustrated in more detail in FIG. That is, as shown in FIG. 2, the memory circuit 20 is composed of a plurality of memories arranged in a matrix, and the horizontal axis indicates the number of octaves,
Data divided into different timbres is stored on the vertical axis. The gate circuit 21 is also provided with a plurality of gate circuits corresponding to the tones. The case of FIG. 2 is an example in the case of three tone color tablets.

The three control lines for controlling the gate circuit 21 are supplied from the gate circuit 24 _{1 in the} synchronizing circuit 24. In this case, since the synchronizing circuit 24 controls three tones, the D flip-flop is used. 3 circuits and gate circuit 24
_{In 1} , the configuration requires three AND circuits.
The adder circuit 22 is configured to add the outputs of the plurality of gate circuits. The relationship of the vertical axes of the plurality of memories is the relationship of different tone colors, and corresponds to each tone color tablet in the tone color tablet 25. Therefore, corresponding to the operation of the tone tablet 25,
Each block of the gate circuit 21 is controlled to control selection of waveform data to be added.

Returning to FIG. 1, the waveform data output from the memory circuit 20 passes through the data bus line L4 added by the adder circuit 22, and the corresponding time-divided waveform data is transferred to the first latch circuit 8. Given to ₁ . That is, since the latch circuit 8 ₁ latches at the rear end of the pulse T1 which is the same as the time division pulse of the gate circuit 9 ₁ ,
The data corresponding to this channel is latched. That is, if the frequency of the cycle in which the time-division pulse from the sequential pulse generator 18 makes one cycle is sufficiently higher than the frequency at which the state of the address counter 6 ₁ in the sound source device 26 ₁ changes (twice or more), The address of the address counter 6 ₁ can be surely supplied to the memory circuit 20 without being skipped, and the waveform data read from the memory circuit 20 can be supplied to the first latch circuit 8 ₁ .

This waveform data is re-latched in the second latch circuit 7 ₁ again in synchronization with the tone waveform by the clock output from the waveform forming circuit 5 ₁ , and this waveform data is given to the waveform forming circuit 5 ₁ . Be done. This waveform forming circuit 5 ₁
At, the waveform data stored in the memory circuit 20 corresponding to the count value of the address counter 6 ₁ is sequentially read. This waveform data is the data of the slope and amplitude change of the waveform in each divided section obtained by dividing a desired musical tone waveform, and the desired musical tone waveform is obtained based on this data.

The digital tone waveform formed by the waveform forming circuit 5 ₁ is supplied to the multiplying circuit 11 ₁ , the envelope waveform A1 is added to this, and DA conversion is performed by the DA converter 12 _{1 to} obtain an analog tone tone waveform. It is supplied to the multiplexer 13 ₁ . In the analog multiplexer 13 ₁ , the octave code L 2-1 supplied from the channel 2 ₁ distributes the octave code L 2-1 to the filter circuit 15 including a plurality of filters having cutoff frequencies corresponding to the respective sound ranges, and guides it to the sound system 16.

The configuration and operation of the first channel including the sound source device 26 ₁ including the channel 2 ₁ , the gate circuit 3 ₁ and the waveform forming circuit 5 ₁ and the memory circuit 20 common to each channel have been described above. , Channel 2 ₂ ,
The configuration and operation of the second channel including the tone generator 26 ₂ including the gate circuit 3 ₂ and the waveform forming circuit 5 ₂ and the memory circuit 20 common to each channel are the same as those of the first channel. Are indicated by subscripts 1 and 2.

In the above, the key assigner has two channels,
It is possible to time-division the address signal from the sound source device of each channel, read the waveform data from the common memory circuit 20, and freely set the waveform data having a different frequency spectrum depending on the sound range. As a result, it is possible to realize a sound that is closer to a natural musical tone as compared with a conventional electronic musical instrument that forms musical tones with the same waveform over the entire range.

FIG. 3 is an explanatory diagram relating to the coupler technique of the present invention. According to this embodiment, the sounds corresponding to the swell (upper keyboard) and the grade (lower keyboard) can be generated one or both at the same time. However, in the case of the embodiment of FIG. 3, channel 2 ₁ can be assigned keys for both swell and grade ranges, so a signal is required to identify whether a certain key is swell or grade. Therefore, a modification in which this identification signal is added to the keyboard name code is the above-mentioned Japanese Patent Application No. 50-96035 (JP-A-53-53).
According to No. 45322), this is a modification that can be easily understood by those skilled in the art. That is, the sound source device 26 ₁ in the first channel in FIG. 1 as a key range partitioning, divided into two series of swell and grade. Therefore, the swell and grade series note name selection circuits 4S, 4G are connected in parallel from the master oscillator 14.
Is connected to the tone generator circuits 26S and 26G, and the note name selection circuit 4
A tone name code is input to the S and 4G from the channel 2 ₁ via the line L1-1, and is output from the tone generator circuits 26S and 26G to the multiplication circuits 11S and 11G having two series of tone waveforms.

Similarly, from the tone generator circuits 26S and 26G,
A line corresponding to the line L5 of the gate circuit 9 shown in FIG.
Waveform data is read out through 2G through a line corresponding to the output line L4 of the adder circuit 22 in FIG. Further, an octave code is input to the octave selection circuits 23S and 23G for controlling the memory circuits 20S and 20G, respectively, through a line corresponding to the line L8 of the gate circuit 3 ₁ in FIG. In addition, the synchronization circuit 2 in the dotted line frame synchronization circuit 24
A synchronizing signal is input to 4 ₂ from the tone generator circuits 26S and 26G through lines corresponding to the line L6-1 of the synchronizing pulse generating circuit 10 ₁ of FIG. Synchronization circuit 24 ₂
Output signal of the gate circuit 24 ₁ is supplied to the gate circuit 24 _1, and the output signal of the gate circuit 21 S
Output in parallel to 21G.

In such a configuration, the synchronizing circuit 24 ₂
On the other hand, when the coupler switch (GRtoSW) existing in the tone color tablet 25 is pressed, the coupler information is transferred to the synchronization circuit 2
Is input to the 4 _2, even if only it until grade (GR) sequence was operating sound by key name code from key assigner, to operate the corresponding waveform forming circuit 2
It is possible to select and generate a tone waveform of a series.

FIG. 4 shows a synchronizing circuit 2 having the above-mentioned function.
A detailed circuit example of 4 ₂ and the gate circuit 24 ₁ is shown, and one corresponding to the channel 1 is shown. Therefore, a similar configuration is prepared for channel 2. In the same figure, a synchronizing circuit 24 ₂ receives signals from the tone color tablet 25 (coupler) switch (GRtoSW) 25
It is input to the swell (SW) of B and the grade terminal of 25C. Swell (SW) or grade the coupler switch input of the inverting input and the terminal 25 b by the inverter 24 _{2 1} line Y giving key name code (GR), OR
Tablet input S of terminal 25B through gate 24 _2-2
It is put into an AND gate 24 _2-3 together with 25 and its output is inputted to the D terminal of the first D-type flip-flop 24 _2-5 .

On the other hand, the input of line Y and the input of terminal C G25
_Are input to the AND gate 24 _2-4 , and the output is input to the second D
Input to the D terminal of the flip-flop 24 _2-6 . A synchronizing signal is supplied to the CK terminals of these D flip-flops 24 _2-5 and 24 _{2-6 from} the two series of tone generator circuits 26S and 26G through lines L6-1-S and L6-1-G. To be done. The clear terminals of the D-type flip-flops 24 _2-5 and 24 _2-6 are connected to the line L3-1. Q outputs of these flip-flops are AND circuits 24 _1-1 of the gate circuits 24 _1, is input to the 24 _1-2, time division clock T1 via line L7-1 of the order pulse generator 18 is input .. Each output of the gate circuit 24 ₁ is the gate circuit 2
It is output to 1S and 21G.

To explain the operation of the above configuration, the tone color tab
The coupler switch (GRtoSW) in the let 25 is pressed.
Then, the signal is input to the terminal 25a. Channel
Le 2₁If the swell (SW) was captured in the
The keyboard name code “0” is given from the IN Y. Here
In case of well, keyboard name code is "0", in case of grade
The keyboard name code is "1". This keyboard name code "0"
Is the inverter 24_2-1OR gate 24_2-2Output of
To "1". "1" at terminal 25B, that is, swell
A on condition that the (SW) tone tablet is on
ND gate 24 _2-3Output becomes "1". Therefore the first
D flip-flop 24_2-5"1" is given to the D terminal of
available. Synchronous signal from the sound source circuit 26S to the line L6-1-S
Signal adds "1" to the CK terminal, "1" from the Q terminal
Is output.

[0047] Further time via the line L7-1 from the sequential pulse generator 18 to the AND gate 24 _1-1 divided clock T
1 is given. The output of AND gate 24 _1-1 given to the gate circuit 21S, the waveform data corresponding to Swell keyboard from the memory circuit 20S swell (SW) is output. Therefore, when the swell is captured, the coupler switch operation is ignored. In the case where the channel 2 ₁ Grade (GR) is captured, the AND gate _{24 24} is given key name code "1" from the line Y "1" is input. If the terminal 25c has "1", that is, the grade (GR) tone color tablet is turned on ("1"), the output of the AND gate 24 _2-4 is set to "1".
Therefore, the Q terminal of the second D flip-flop 24 _2-6 becomes "1" and the "1" is input to the AND gate 24 ₁ .

Further, the time-division clock T1 is applied from the sequential pulse generator 18 to the other input of the AND gate 24 _1-2 through the line L7-1, and the output of the AND gate 24 ₁ is applied to the gate circuit 21G. As a result, waveform data corresponding to the grade keyboard is output from the grade (GR) memory circuit 20G. Here, when the coupler switch is turned on, "1" is given to the terminal 25a, and therefore, when "0" is given to the terminal Y, the swell (SW) is read in the same manner as the swell waveform data is read out.
The memory circuit 20S outputs the waveform data corresponding to the swell at the same time as the grade.

A signal from the key assigner is input to the clear terminals of the D flip-flops 24 _2-5 and 24 _2-6 .
This signal is key release information, and when the key assigner does not capture the key depression by the keyboard operation, the D flip-flops 24 _2-5 and 24 _2-6 are cleared. Therefore, the output of AND gate 24 _1-1 becomes "0", the gate circuit 21S,
Since the signal "0" is given to 21G, it is easily understood that the reading of the waveform data is prohibited when the key is not depressed.

In the above embodiment, Japanese Patent Application No. 50-7 is used.
According to Japanese Patent No. 9673 (Japanese Patent Laid-Open No. 52-3421), one cycle of a desired tone waveform is divided into a plurality of sections, and a memory circuit 20 for storing information on the slope and amplitude change of the waveform in each divided section, and a rate multi. Although the combination of the plan and the waveform forming circuit 5 _{1 including the} up / down count is used,
Instead of this configuration, for example, Japanese Patent Application Laid-Open No. 50-1
No. 31513 “Music waveform storage / reading method”, that is, a configuration in which sampling information of various waveforms is stored and a read waveform is formed at a predetermined timing may be used.

[0051]

As described above, according to the present invention,
By storing waveform data for each tone range, a plurality of waveforms can be generated in parallel according to the tone range of the pressed key, and by generating a tone including a frequency spectrum that differs depending on the tone range, a tone similar to a natural musical instrument can be generated. Further, since the number of words of the waveform data is reduced in correspondence with the musical range, the memory capacity can be reduced, which is advantageous in that it is economical.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of an electronic musical instrument having a 2-channel key assigner to which the present invention is applied.

FIG. 2 is a detailed view of a main part of FIG.

FIG. 3 is a detailed view of an essential part of another embodiment of the present invention.

FIG. 4 is a detailed view of a main part of the embodiment.

FIG. 5 is a diagram showing the number of words in each range and a supply bit of a line L5.

[Explanation of symbols]

1 ... Keyboard, 2 ... Key assigner, 2 ₁ , 2 ₂ ... Channel, 3 ₁ , 3 ₂ ... Gate circuit, 4 ₁ , 4 ₂ , 4S, 4G
... Sound name selection circuit, 5 ₁ , 5 ₂ ... Waveform formation circuit, 6 ₁ , 6
₂ ... Address counter, 7 ₁ , 7 ₂ , 8 ₁ , 8 ₂ ... Latch circuit, 9 ₁ , 9 ₂ ... Gate circuit, 10 ₁ , 10 ₂ ... Synchronous pulse generating circuit, 11 ₁ , 11 ₂ , 11 S, 11 G ...
Multiplying _{circuit, 12 1, 12 2 ... D} -A converter, 13 _1, 1
3 ₂ ... Anagro multiplexer, 14 ... Master oscillator,
15 ... Filter circuit, 16 ... Sound system, 17 ...
Time division clock generation circuit, 18 ... Sequential pulse generator, 1
9, 19S, 19G ... Complement circuit, 20, 20S, 20G
... Memory circuit 21,21S, 21G ... Gate circuit, 2
2, 22S, 22G ... Adder circuit, 23, 23S, 23G
... octave selection circuit, 24 ... gate circuit, 24 ₁ ... synchronization circuit, 25 ... timbre tablet, 26 ₁ , 26 ₂ ... sound source device, 26S, 26G ... sound source circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadaaki Ezawa 74-24 Nishi-Iba-cho, Hamamatsu City, Shizuoka Prefecture (72) Inventor Hironori Watanabe 21796 Shinohara-cho, Hamamatsu City, Shizuoka Prefecture (72) Inventor Tatsunori Kondo Shinohara, Hamamatsu-shi, Shizuoka Prefecture Town 21796 (72) Inventor Toshio Kugizawa Shinohara Town, Hamamatsu City, Shizuoka Prefecture 21796 (72) Inventor Yutaka Washiyama 626-3 Hyota, Fujieda City, Shizuoka Prefecture

Claims (1)

[Claims] 1. A plurality of memory means for storing waveform information with a different number of words for each tone range, an address signal generating means for outputting a plurality of address signals according to a plurality of pressed key note names, and the plurality of pressed keys. Memory designation means for time-divisionally designating one or more memory means of the plurality of memory means according to each of the tone ranges to which the memory range belongs, and a memory designation signal from the memory designation means and an address signal from the address signal generation means. An electronic musical instrument comprising: a reading unit that reads out waveform information from the memory unit in a time division manner.