JPH0213799B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital filter device for an electronic musical instrument, and more particularly to control of supply of filter coefficients to a filter circuit. The characteristics of the digital filter are controlled according to the value of the filter coefficient given thereto. Therefore, when using a digital filter as a tone color circuit of an electronic musical instrument, it is necessary to appropriately provide filter coefficients according to the desired tone color. Therefore, the present invention provides filter coefficients appropriately according to the selected timbre, allows the characteristics of the filter to be freely controlled according to the desired timbre, and allows one digital filter to control multiple timbres. In order to be able to simultaneously execute corresponding different filter operations, this digital filter is configured to perform filter operations on a plurality of channels in a time-sharing manner, and it is also possible to easily allocate timbres to each channel. It is an object of the present invention to provide a digital filter device for an electronic musical instrument that can perform the following functions. In order to achieve this object, a digital filter device for an electronic musical instrument according to the present invention includes a digital filter that inputs digital musical tone signals of a plurality of channels and performs a filter calculation operation in a time-sharing manner, and a digital filter device that is used in the calculation in this digital filter. a filter coefficient storage means for storing in advance a plurality of sets of filter coefficients to be filtered; a timbre selection means for selecting a desired timbre; and a timbre identified in correspondence with each timbre selectable by the timbre selection means. a timbre including a memory storing timbre parameters including a timbre code to be assigned and a channel code indicating a channel to which the timbre is to be assigned, the timbre parameter corresponding to the timbre selected by the timbre selection means being read from the memory and outputted; a parameter supply means; a tone storage means for storing the tone code included in the tone parameter outputted from the tone color parameter supply means at an address corresponding to the channel code; readout control means for sequentially reading out each channel in accordance with the time-division timing of each channel; the readout control means reads out the corresponding filter coefficient set according to the timbre code of each channel read out in a time-division manner; It is characterized in that the signal is outputted from the storage means in a time-divisional manner and supplied to the digital filter. According to the present invention having such a configuration, the timbre parameters including the timbre code and the channel code indicating the channel to which the timbre is to be assigned are stored in the memory for each timbre, and the timbre parameters are stored in the memory for each timbre. A timbre parameter, that is, a timbre code and a channel code indicating a channel to which the timbre is to be assigned are read out. Then, the tone code is stored in the tone storage means using the channel code as an address, so in the assignment process, the destination of the newly selected tone is determined after searching which tone is currently assigned to which channel. By storing the timbre code in the timbre storage means using the channel code as an address, the allocation process is immediately executed. Therefore, according to the present invention, with a simple configuration, the digital filter can be used in a time-division manner for a plurality of tones, and the process of assigning tones to each channel can be easily performed. This effect is achieved. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In FIG. 1, the keyboard section 9 includes a plurality of keyboards (for example, an upper keyboard, a lower keyboard, and a pedal keyboard) and a key switch circuit including a key switch corresponding to each key of these keyboards. Key assigner 10 is
It includes a circuit for detecting whether each key switch of the keyboard section 9 is turned on or off, and a circuit for assigning a key corresponding to the turned-on key switch, that is, a pressed key, to one of a plurality of musical sound generation channels. Information indicating the key assigned to each musical tone generation channel (key code KC) and information indicating whether the key is kept pressed or released (key-on signal KON) are sent from the key assigner 10 to the musical tone signal generation section 11. given to. Musical tone signal generator 1
1 generates a musical tone signal corresponding to a key pressed on the keyboard section 9 according to the output of the key assigner 10, and divides the generated musical tone signal into a plurality of series according to the type of keyboard, timbre, etc. Output in parallel. Specifically, in order to be able to generate musical tone signals corresponding to one or more keys at the same time, the musical tone signal generation section 11 has a number of tone generation channels for sound sources corresponding to the maximum number of keys that can be generated simultaneously for each key. The musical tone generation channels for these sound sources are provided in duplicate over multiple series, and the musical tone signals of each series are outputted in parallel in a digital format. The timbre selection device 12 includes a large number of switches for selecting timbres and various effects for each keyboard. A predetermined output among the outputs of the tone selection device 12
TP1 is given to the musical tone signal generator 11,
It controls musical tone signal generation operations in the generating section 11 (applying timbre to the musical tone signal to be generated, setting an amplitude envelope according to the timbre, selecting a sound source waveform, etc.). Among the musical tone signals generated by the musical tone signal generating section 11, there are some tones to which a predetermined timbre has been applied within the generating section 11 in accordance with the timbre selection by the timbre selection device 12; There are some that are not, and timbre control is applied to them by the digital filter section 14 at the subsequent stage. For example, a tone that always has the same spectral distribution regardless of the pitch (a so-called moving formant tone) is generated by the musical tone signal generator 11, and a fixed formant tone is generated by the digital filter section 14. Even for moving formant tones, such as the low-frequency characteristics of brass systems or the complex characteristics of string systems, it is preferable to perform spectral correction by further applying fixed formant filter control. The digital filter unit 14 is also used for these tones. The digital musical tone signals for each series outputted from the musical tone signal generating section 11 are given to a musical tone signal distribution, accumulation and serial conversion control circuit 13. This control circuit 13 is supplied with a predetermined output TP2 among the outputs of the timbre selection device 12. The control circuit 13 divides the musical tone signals into those that can be accumulated and those that should be passed through the digital filter unit 14 from each series according to the tone parameter TP2 given from the tone selection device 12, and allows accumulation. The device accumulates (mixes) these musical tone signals and outputs them to line 15, and then outputs them to the digital filter section 14.
The parallel digital musical tone signals for each series are temporally serialized, and the serial digital musical tone signals are time-division multiplexed between predetermined series and output to a common signal line. Note that the predetermined series to be time-division multiplexed are series that differ in keyboard type or tone color. As will be explained in detail later, in this embodiment, multiple sound sources or musical tone generation sequences (hereinafter referred to as sub-sequences) are prepared for one timbre to be achieved, and time-division multiplexing is performed between these sub-sequences. We are learning not to do this. Therefore, the control circuit 13 outputs serial digital musical tone signals time-division multiplexed between predetermined series in parallel for each sub-sequence, and is applied to the digital filter section 14 via the line 16. By temporally serializing a multi-bit digital musical tone signal and then applying it to the digital filter section 14, the arithmetic circuit inside the filter section 14 can be made into a serial arithmetic circuit, and the structure of the filter section 14 can be reduced. Contribute. Moreover, time-division multiplexing of multiple series of digital musical tone signals and combining them into a common line eliminates the waste of having to provide a digital filter for each series, contributing to a reduction in the configuration of the digital filter section 14. but,
It is not necessarily necessary to perform serialization and time-division multiplexing, but multiple-bit digital musical tone signals can be processed in parallel by the digital filter section 14.
You may also enter it in The table below shows an example of each series and an example of how they are distributed in the control circuit 13. "single/double"
The column indicates whether the series is a single-tone generation series or a multiple-tone generation series. Of course, in the case of a multiple-tone series, a signal obtained by adding and mixing digital musical tone signals of a plurality of tones is output from the musical tone signal generating section 11 as a musical tone signal for one series. The symbols ch1, ch2, ch3, and ch4 shown in the "Distribution" column are filter channels, and are the identification signals of each series when explaining the time-division processing of musical tone signals of each series by the digital filter section 14. used as still,
The filter channels ch1 to ch4 mentioned here are:
This channel is completely different from the musical tone generation channel to which each pressed key is assigned by the key assigner 10, and represents a series in which different filter processing is performed.

【table】 For each series shown in the series column of Table 1
select one or more of multiple types of tones, respectively.
It is possible to do so. The aforementioned sub-series
into four series led to the digital filter section 14.
They are set individually. That is, for example,
In "Keyboard Special Type", predetermined multiple types
It is possible to select one or more of the tones.
Yes, the musical tone signal (sound source) corresponding to the selected tone
signals) are generated in multiple subsequences, respectively.
It's summery. The musical tone signal on line 15 is fed to mixing circuit 17.
The serial tone signal on line 16 is digital.
The signal is applied to the mixing circuit 17 via the filter section 14.
It will be done. The mixing circuit 17 is a digital filter section 14
filter-controlled musical tone signal and filter-controlled
Mixing with the musical tone signal of line 15 that was not performed.
(digital addition).
Since the controlled musical tone signal is serialized,
For this purpose, these serial musical tone signals are
After converting to real, I started doing the above mixing.
ing. Digital output from mixing circuit 17
The musical tone signal is converted by the digital/analog converter 18.
converted to analog signal and sent to sound system 19
Given. The digital filter section 14 has filter characteristics.
A polar film that can effectively control the characteristics of the peaks in the
Enables the characteristics of the valley part of the filter characteristics.
It includes a zero filter that can be controlled to
It is possible to switch the connection combination of filters.
is configured to realize complex filter characteristics.
The sea urchin is sleeping. Of the outputs of the tone selection device 12
A predetermined output TP3 is sent to the digital filter section 14.
is given, and each filter type is
Filter characteristics for each channel channel 1 to 4 (e.g.
filter coefficients) are now set respectively.
Ru. Furthermore, in the digital filter section 14,
is the file of the input musical tone signal of each sub-sequence.
Parameter the tone of what should pass through the router and what should not pass through.
It is designed to be distributed according to meter TP3. For setting filter characteristics, the filter section 14
Inside the filter coefficient internal ROM (ROM is readable).
(the same applies hereafter) is included.
The predetermined filter coefficients are retrieved from this internal ROM.
Depending on the tone selection information (tone parameter TP3)
so that it is read out and used by the filter unit 14.
It's summery. This filter coefficient is separate from the internal ROM.
A filter coefficient external storage device 20 is provided.
Ru. This external storage device 20 is a semiconductor storage device.
You can also use removable storage such as magnetic cards.
It may also include a storage medium. External storage device 20?
The filter coefficient KO read from the digital filter
The signal is supplied to the filter section 14. digital filter
In relation to section 14, filter coefficient changeover switch 21
is provided. This switch 21 is a digitizer
In the filter section 14, internal ROM or external
Select which storage device 20 to use
switch 21 in the filter section 14.
Either one is selected depending on the output signal KS of
Execute filter control according to the filter coefficient of
Ru. The filter coefficients stored in the external storage device 20
An example is a time-varying filter coefficient.
There is. In order to change the filter coefficients over time,
A large storage capacity is required for this purpose;
This is because an external storage device is suitable. this external
The storage device 20 stores key keys from the key assigner 10.
tone signal KON and tone parameters from tone selection device 12
Meter TP4 is now being supplied,
During key press and after key release according to key-on signal KON
Controls changes in filter coefficients over time
and change the change characteristics of this filter coefficient to the timbre parameter.
Control according to meter TP4. Note that the control circuit 13 controls the musical tone for the line 16.
Corresponding to the reference timing of serial signal transmission
It is designed to output synchronous pulse SYNC.
This synchronization pulse SYNC is generated by the digital filter section.
14 and external storage 20, line 1
The filter coefficient is set in synchronization with the serial musical tone signal of 6.
To serialize (read serially),
and the serial calculation time in the filter section 14.
It is used for synchronized control of processing. Multi-sequence sound source, i.e. musical tone signal with sub-sequences
An example of the generator 11 and musical tone signals connected to it
Signal distribution, accumulation and serial conversion control circuit 13
An example is shown in FIG. The musical tone signal generating section 11 is
Changing the type of keyboard or the nature of the sound to be generated
Includes multiple series of tone generators 22 to 26.
Among them, the digital filter section 14 is
Series that may be used (tone generator
23 to 26) each have three subseries (this
#1, #2, #3)
Each includes a tone generator. pedal key
Board tone generator 22, upper keyboard solo tone
Generator 23, upper keyboard custom tone generator
Enerator 25 is a single tone tone generator.
, upper keyboard double-tone tone generator 24 and lower keyboard
The keyboard multitone tone generator 26 is a multitone tone generator 26.
It is an engine generator. Key Assigner 10 (1st
The key information (key code KC, key
– ON signal KON, etc.) is connected to each tone generator 2.
2 to 26 are input. This key information is the keyboard information.
Contains a tone generator corresponding to that keyboard information.
The key information (KC, KON
etc.) are used. Multitone tone generator
24 and 26 are assigned to each musical tone generation channel.
Multiple key information KC, KON corresponding to the multiple key information KC, KON
It is possible to generate musical tone signals. upper keyboard
For single tone tone generators 23 and 25, the upper key
If multiple pieces of keyboard key information KC and KON are given at the same time.
and select one (highest or lowest note).
to generate the musical tone signal. Each tone generator 22 to 26 generates
One of the multiple types of tones for the musical tone signal to be played.
It is possible to selectively provide one or more.
For this purpose, various sounds corresponding to the selected tone are created.
Color parameter TP1 is the tone selection device 12 (Fig. 1)
to each of the tone generators 22 to 26, respectively.
This tone parameter
Frequency components or sound source waveforms according to TP1, and
amplitude envelope, number of feet, and volume,
and various other musical tone elements.
Generated at a pitch corresponding to the pressed key. However, the fixed
Tonal elements based on constant formants are not added here.
In the digital filter section 14 at the subsequent stage,
Granted. It is possible to use the digital filter section 14.
To the functional series (tone generators 23 to 26)
The sub-series #1 to #3 provided respectively are as follows:
Regarding the musical tones to be generated in each series 23 to 26
It has become a multi-series sound source. For example, upper keyboard solo
1 that is about to be generated by the system tone generator 23
One musical tone signal has three sub-sequences.
Tone generator corresponding to #1, #2, #3
The final addition of the musical tone signals generated in
Obtained by. Therefore, each subsequence #1,
The musical tone signals generated in #2 and #3 are partial tone signals.
It is also possible to do so. However, the type of tone
All sub-series tone generators depending on the
There may be some that do not use, for example, one
Using only the tone generator of sub-series #1
Alternatively, the musical tone signal may be generated using the same method. This way
Una multi-sequence sound source, that is, multiple sub-sequences #1~
#3 is a partial tone signal that constitutes one musical tone signal.
A part is selectively controlled by the digital filter section 14.
This is advantageous if it is possible to do so. Regarding this point
This will be explained in more detail later. Each tone generator 22 to 26 generates a musical tone signal.
It is generated in digital form, and its musical sound
Generation methods include frequency modulation calculation method and high frequency combining.
Any other method such as generation method, waveform memory read method, etc.
You can use the formula The multiple tone tone generators 24 and 26 generate multiple
Digital musical tone signals corresponding to the number of keys pressed are output respectively.
Powered. Each tone generator 24, 26
The areas provided corresponding to sub-series #1 to #3 are
Accumulators 27 and 28 support multiple pressing keys.
The musical tone signals for each sub-sequence are accumulated. Musical tone signal distribution, accumulation and serial conversion control
In the circuit 13, gates 29, 30, 31, 3
2 is for each series given from the musical tone signal generator 11.
This is for distributing musical tone signals and for tone selection.
The tone parameter TP2 given from the device 12
controlled accordingly. Gate 29 is upper keyboard double tone system
of the first sub-sequence #1 of the tone generator 24
Accumulator 2 corresponding to tone generator
Select the output musical tone signal of No. 7 and output it to the accumulator 33.
It is intended to be given to See Table 1 above.
Then, the output of this gate 29 is the upper keyboard flute.
Corresponds to the musical tone signal of the UFL system. In other words, the tone selection
Select device 12 selects some kind of upper keyboard flute type UFL.
If a tone is selected, the upper keyboard multitone tone tone
Corresponds to the first sub-series #1 of the energizers 24
On top of that, there is a tone generator that allows you to play the flute type on the keyboard.
Generates a musical sound signal of tone color and outputs it at gate 29.
side of the filter 33 (through the digital filter section 14)
group). Gate 30 is a lower keyboard multitone tone generator.
The data corresponding to the first sub-sequence #1 among the data 26
Accumulator that accumulates the output of the engine generator.
28 output musical tone signals are selected and the accumulator 3
It is for giving to 3. See Table 1 above.
Then, the output of this gate 30 is the lower keyboard orchestra.
Corresponds to the musical tone signal of Tora-based LOR. In other words, the sound
Use the color selection device 12 to select the lower keyboard orchestral LOR.
If some tone is selected, the lower keyboard double-tone type
First sub-sequence of tone generator 26
The lower keyboard with the tone generator corresponding to #1.
Generates a musical tone signal with an orchestral tone and gates it.
30, it is distributed to the accumulator 33 side. Gate 31 is an upper keyboard special USP musical tone.
Distribute the signal to the digital filter section 14 side
Gate 32 is for the lower keyboard special system.
The LSP musical tone signal is transferred to the digital filter section 14 side.
This is for the purpose of allocating to. Tone selection device 12
to select some upper keyboard special USP tone.
If selected, the upper keyboard multitone tone generator
Each sub-series #1 to #3 of the data 24 corresponds to the tone.
generate musical tone signals respectively, and drive the accumulator 27.
Each of those sub-sequences #1 to #3 given via
The musical tone signal is passed through the gate 31 to the multiplexer.
34 side (digital filter section 14 side)
Separate. Lower keyboard special LSP tone is selected.
Similarly, if
Each sub-series #1 to #3 of the data 26 corresponds to the corresponding tone.
generate musical tone signals respectively, and pass them through the gate 32.
They are distributed to the multiplexer 34 side. In addition, the upper keyboard multitone tone generator 24
1 sub-series #1 for upper keyboard flute type UFL.
When using the tone generator 2
4 other sub series #2 and #3 as upper keyboard special
It can also be used for system USP, and its
In the case of
Select the corresponding musical tone signal and send it to the multiplexer 34.
give. Lower keyboard double tone tone generator 26
The first sub-series #1 is the lower keyboard orchestral system.
Similarly when using for LOR, other services
For the lower keyboard special type LSP,
It can be used for Also, Tonji
Enerators 24 and 26 are special USP,
Dedicated to LSP, upper keyboard flute type UFL and lower keyboard.
Dedicated tone generator for keyboard orchestral LOR
Further data may be provided. The accumulator 33 starts from the gates 29 and 30.
The given upper keyboard flute type UFL and non-keyboard OFL
- Kestra LOR musical tone signal and tone generator
Pedal keyboard type PKB music generated by Rater 22
The output signal is
is applied to the mixing circuit 17 (FIG. 1) via line 15.
available. The upper keyboard sound generated by the tone generator 23
Russian USL musical tone signal, tone generator 24
The upper keyboard speci given through gate 31 from
Yaru-based USP musical tone signal, tone generator 2
Upper keyboard custom UCS music message generated in 5
from the tone generator 26 to the gate 32
The ease of the lower keyboard special LSP given through
The sound signal is sent to the multiplexer 34 and the parallel
Daiji via real converter 35 and line 16
The signal is applied to the tar filter section 14 (FIG. 1). Ma
The multiplexer 34 includes each series USL, USP, UCS,
Filter channel ch1 to ch of LSP musical tone signal
This is for time division multiplexing in accordance with 4.
Is the control signal for the timing signal generator 36
given. Each series USL, USP, UCS, LSP
The musical tone signals of
Separately time division multiplexed. Each sub-series #1 to #3
The parallel signal output from the multiplexer 34 in response to
Row-like digital musical tone signals correspond to each sub-sequence
to the parallel-to-serial converter 35 provided as
are input respectively. This converter 35 converts each sub-sequence
Digital musical tone signals #1 to #3 are serialized in time.
al musical tone signal S₁,S₂,S₃to convert respectively to
The control signal for this is the timing signal generation.
It is given from the generator 36. Also, the timing signal
The generator 36 outputs the synchronization pulse SYNC mentioned above.
Ru. FIG. 3 shows an example of the digital filter section 14 in a large scale.
This is shown using a basic block diagram. No.
The output from the parallel-to-serial converter 35 in Figure 2 is
Serial numbers corresponding to each sub-series #1 to #3
Digital musical tone signal S₁,S₂,S₃is the filter input
The signal is input to the control circuit 37. Filter input control circuit
Path 37 represents each musical tone signal S.₁,S₂,S₃Of which digital data
What should be input to the filter main circuit 38?
Distribute those without and according to tone parameter TP3
This is for the purpose of Digital filter main cycle
The musical tone signal (S₁,S₂,S₃out of
(1 or more) between the same filter channels
The filter is added and mixed and sent from the input control circuit 37 to the filter.
It is input to the main circuit 38. Digital filter main
The remaining musical tone signals that do not pass through the circuit 38 are sent to the output control circuit.
from the digital filter section 14 via path 39.
Output. The output control circuit 39 is a digital
The musical tone signal that has passed through the filter main circuit 38 and the
Depending on the timbre parameter TP3 with no timbre signal
output line S corresponding to each sub-series₁O,S₂O,
S₃It is distributed to O. The timing signal generation circuit 40 is a digital
Controls the filter calculation operation in the filter main circuit 38.
Synchronous pulses for various timing signals to control
generated based on SYNC and digitizes these signals.
It is supplied to the tar filter main circuit 38. Filter person
The number supply circuit 41 is the digital filter main circuit 38
This is to supply the filter coefficient K for
Yes, and includes the filter coefficient internal ROM mentioned above.
from the corresponding ROM according to the tone parameter TP3.
Read and supply predetermined filter coefficients. Ma
In addition, the filter coefficient supply circuit 41 has filter coefficients.
Filter coefficient given from external storage device 20
KO signal and filter coefficient changeover switch 21 output
The force signal KS is input.
Read in internal ROM according to switch output signal KS
filter coefficients or given from external storage device 20.
One of the obtained filter coefficients KO is converted into a digital filter.
It is supplied to the filter main circuit 38. Also, the filter
The number supply circuit 41 has a synchronous pulse SYNC and a timing
The output signal of the programming signal generation circuit 40 is applied.
The filter is synchronized with the filter calculation timing.
It is designed to supply coefficients. Digital filter main circuit 38 is polar filter 4
2 and zero filter 43, both filters
The terminals 42 and 43 are connected in series. Extreme foil
What is the peak of the filter characteristics (amplitude frequency characteristics)?
Mainly polarization (polarization) can be controlled, and zero-fi
The filter mainly refers to the valley part (zero point) of the filter characteristics.
It is something that can be controlled. In this way, polar filter 4
2 and the zero filter 43, the filter
The peaks and valleys of the characteristics are each independently
Can be controlled and complex characteristics relatively easily
This is advantageous because it can be realized. Generally, a polar filter is used to filter the current digital signal
Digital signal output for input and past n samples
For each force, coefficient Ki (where i = 1, 2,...n)
The sum of weighted data is returned to the input side.
It has a closed loop with infinite impa
IIR filter (hereinafter referred to as IIR filter)
It is expressed by Also, the zero filter is currently
and digital signal input for past n samples
for each by the coefficient Ki (where i=1, 2,...n).
It outputs the sum of the weighted values.
Therefore, a finite impulse response filter (FIR filter)
irta). Lateis type filter as a type of IIR filter
This latex filter is suitable for speech synthesis.
It is known as a filter. Moreover, this
Compared to other types, the Lattice filter has a multiplier
The number of hardware can be reduced, and the hardware can be made smaller.
This has the advantage of reducing the bits of the filter coefficients.
Fewer filters required and desired filter characteristics
There is an established method for setting coefficients for
There are some advantages. Therefore, in this embodiment, the pole film is
A preferred example of a filter is a latteis type filter.
shall be used. Pole filter in digital filter main circuit 38
The router 42 is constructed with a latex filter.
An example is shown in FIG. This polar filter 42 has 12 stages
It consists of lattice-type filters, each stage of which has a
The filter units are indicated by the symbols L1 to L12.
vinegar. The polar filter 42 in FIG.
The structure is designed with consideration to the calculation time delay. same
Digital system configured with calculation time delay in mind
Zero filter 43 in filter main circuit 38
An example is shown in FIG. This zero filter 43 is 2
Next zero filter (2 sampling time delay)
zero filter) and simply FIR
If we have a configuration in which two stages of filters are connected in cascade,
Although it is good, the calculation time delay and other factors
In consideration of the above, it is assumed that the configuration is as shown in FIG. Before explaining FIGS. 4 and 5, this polar film
The digits input to the filter 42 and zero filter 43
The data format of the musical tone signal will be explained. one
As an example, one musical tone signal is a 24-bit digital signal.
control circuit 1 in Fig. 2.
3 through line 16 to the digital file of FIG.
Serial of each sub-series given to filter unit 14
musical tone signal S₁,S₂,S₃is 24 ties per signal.
Serialized in time using Muslot
and the serial for these 24 time slots.
Musical sound signals are time-division multiplexed through 4 filter channels.
has been done. Therefore, the serial tone of each sub-series
signal S₁,S₂,S₃1 sample of musical waveform amplitude at
The ring period is 24 x 4 = 96 time slots.
Ru. Sequential time slots within this one sampling period
The ones shown with numbers 1 to 96 are numbered.
This is Figure 6a. Figure 6b is for each time slot.
corresponding serial musical tone signal S₁,S₂,S₃data content of
This is what is shown. The timing shown in Figure 6 a and b
The serial tone signal S of each sub-series is₁,S₂，
S₃common to As shown in Figure 6b, Syria
musical sound signal S₁,S₂,S₃In the first time slot
Filter change from 0 to 24th time slot
Le ch1 (upper keyboard solo USL) serial music message
No. data, files in the 25th to 48th time slots
Tatyannel ch2 (upper keyboard special USP)
serial musical tone signal data, 49th to 72nd times
Filter channel ch3 (upper keyboard) in the slot.
Serial musical tone signal data of STAM system UCS),
Filter channel from 73rd to 96th time slot
Serial music of ch4 (lower keyboard special LSP)
Sound signal data are respectively assigned. 24 ties
In each musical tone signal data for each muslot, the first
time slots (1st, 25th, 49th, 73rd tie)
The least significant bit (LSB) is assigned to
The slower the time slot, the heavier the time slot becomes.
The 23rd time slot (23rd,
47th, 71st, 95th time slot)
The MSB is allocated and the last timeslot (first
24th, 48th, 72nd, 96th time slot)
Bit SB is assigned. Returning to Fig. 4, the first stage filter unit L1
To explain, reference number 61 is used as a subtractor.
62, 63 are adders, 64 is an adder that functions as
Multipliers 65, 66, and 67 are delay circuits. slow
Numbers shown in blocks of extension circuits 65-67
32D means a delay of 32 time slots.
It shows. FS−IN is the forward input terminal for musical tone signals.
FS-OUT is the forward output terminal for musical tone signals, BS
−IN is reverse input terminal, BS−OUT is reverse output terminal
A child. Other units L2 to L12 are also unit
It has the same configuration as unit L1, and each unit L1 to
The forward output terminal FS-OUT of L11 is connected to the next stage unit.
To forward input terminal FS-IN of units L2 to L12
Connected, reverse output of each unit L2 to L12
The terminal BS-OUT is connected to the previous unit L1 to L.
It is connected to the reverse input terminal BS-IN of No. 11. Adder of filter unit L1 (function:
In the subtracter) 61, the forward input terminal FS-IN
The musical tone signal input from the reverse input terminal BS−IN
and the next stage unit L2 via the delay circuit 66.
subtracted from the musical tone signal fed back.
The output of this adder 61 is input to a multiplier 64,
filter coefficient K₁is multiplied. This coefficient K₁accompanying
The letter 1 is the coefficient corresponding to the first stage unit L1.
to show that The output of the multiplier 64 is sent to the adder 62.
through the terminal FS-IN and the delay circuit 65.
is added to the input musical tone signal given by here
The reason for providing the delay circuit 65 is that the multiplier 64
This is to accommodate the calculation time delay. sand
That is, in this example, the calculation time delay of the multiplier 64 is
Designed for 32 time slots,
In order to accommodate this delay, the delay circuit 65 uses 32
This provides a delay equal to the imslot. adder
The output of 62 is sent to the next stage via the output terminal FS-OUT.
is input to unit L2. By the way, the output of the adder 61 and the next stage unit
This adder 61 from L2 via a delay circuit 66
There is one sample between the signal fed back to
There must be a time delay corresponding to the ring period.
However, this is satisfied as follows.
Ru. From the multiplier 68 of the next stage unit L2 to the adder
69, the musical tone signal enters unit L1 in the reverse direction.
input to the output terminal BS-IN, which is input to the delay circuit 66.
It is input to the adder 61 via. obey
The output signal of the adder 61 is then processed by the multiplier 64 using 32 signals.
The imslot is delayed, and then the next stage multiplier 6
8 is delayed by 32 time slots, and further delay circuit 6
6 was delayed by 32 time slots, resulting in a total of 96 ties.
A feedback signal is sent to the adder 61 with a muslot delay.
You will get hit. As mentioned above, Serial Raku
sound signal S₁~S₃1 sampling period is 96 times
Since it is a slot, the necessary delay time as above
This means that time is secured. Adder that provides a signal to the reverse output terminal BS−OUT
63 (69 in L2) is the multiplier 64 (in L2
68) and delay circuits 66 and 67 (L2
70, 71)
Feedback signal from L2 (L3 in L2)
This is for adding the numbers. Delay circuit 66
The output of the multiplier 64 corresponding to the output of the delay circuit 6
32 time slots later than the output timing of 6.
ing. Set a time delay that is commensurate with this delay.
A delay circuit 67 is provided for this purpose. In addition, the final stage unit L12 outputs its own musical tone.
It is designed to feed back signals. So
Therefore, the multiplier of the next stage unit as mentioned above is
Can't expect a time delay for 32 time slots?
Then, the forward output terminal FS-OUT of unit L12
Feedback the output signal to the reverse input terminal BS−IN
Set a time delay of 32 time slots on the loop to
Assume that a delay circuit 72 is provided for determining the timing. In addition, in the following, the first stage filter unit L1
Forward input terminal FS−IN and reverse output terminal BS−
FS to identify OUT_iand B.S._pUse the sign
The forward output terminal of the last filter unit L12
Specify the output terminal FS-OUT and reverse input terminal BS-IN.
FS to_pand B.S._iUse the code . In the zero filter 43 shown in FIG.
The zero filter includes multipliers 73, 74 and adder 7.
5, 76 and delay circuits 77, 78, 79
It is configured. The first stage of this secondary zero filter
is a multiplier 73 to which an input musical tone signal is applied;
The output signal of multiplier 73 is delayed by 64 time slots.
delay circuit 77 and the output signal of this delay circuit 77.
and an adder 75 for adding the input musical tone signal and the input musical tone signal.
Become. The multiplier 73 has a filter corresponding to the first stage zero filter.
corresponding filter coefficient K₁₃is given. Multiplier 7
The calculation time delay in 3 and 74 is 32 times as mentioned above.
Suppose it is imslot. Therefore, multiplier 73
The delay time in the delay circuit 77 is 96 times in total.
It is a slot and has exactly one sampling period.
Ru. Therefore, the adder 75 calculates the current sampling time
musical tone signal and the musical tone signal one sampling time before
filter coefficient K₁₃The signal multiplied by
Ru. The second stage zero filter receives the input musical tone signal.
128 time slot delay circuit 78 and this
A filter coefficient K is applied to the output signal of the delay circuit 78.₁₄of
A multiplier 74 to be multiplied and an output signal of this multiplier 74.
a delay circuit 79 for delaying the signal by 32 time slots;
The output signal of this delay circuit 79 and the output of adder 75
and an adder 76 for adding the signals. circuit 7
The total delay time due to 8, 74, 79 is 192 ties.
It is exactly 2 sampling periods.
Ru. Therefore, in the adder 76, at the time of 2 samplings
Filter coefficient K is applied to the previous musical tone signal.₁₄signal multiplied by
and the output signal of the adder 75 are added. wife
In adders 75 and 76, the current sample
musical tone signal of the sampling time and its one sampling time
Filter coefficient K to previous musical tone signal₁₃signal multiplied by
and the musical tone signal from two sampling times before.
ruther coefficient K₁₄The sum of the signals multiplied by
Ru. In this way, the adder 76 outputs the secondary zero filter.
The output signal of the controller can be obtained. The output signal of the adder 76 is sent to the delay circuit 80 for 64 times.
The signal is delayed by muslot and input to the multiplier 81.
The multiplier 81 controls the output gain of the zero filter 43.
It is provided for gain control.
coefficient K₁₅is entered. The aforementioned coefficient K₁₃,K₁₄
is involved in setting the filter characteristics of the zero filter 43.
However, this coefficient K₁₅is involved in setting the filter characteristics.
one that sets the overall gain of the zero filter without
It is. The calculation time delay in the multiplier 81 is as described above.
as well as 32 time slots and 64 time slots.
The delay circuit 80 that delays the
Signal delay time in control circuits 80 and 81
Synchronized to 1 sampling period (96 time slots)
It was established to make Note that the first stage circuits 73, 7 of the zero filter 43
7, 75 and second stage circuits 78, 74, 79, 7
6 and each of the gain control circuits 80 and 81.
The insertion points of delay circuits 77, 78, 79, and 80 are as follows.
Not limited to the locations shown in the diagram, the key is to take one sample at the first stage.
sampling time, 2 sampling times in the second stage, gain control
A delay of one sampling time is set in the control section.
All you have to do is lie down. For example, the input of the multiplier 73
A delay circuit 77 is provided on the power side, and delay circuits 78 and 79
, and a delay circuit is placed on the output side of the multiplier 81.
A passage 80 may also be provided. However, as described later
In this example, each filter coefficient K₁~
K₁₅is a digitized data format that is serial in time.
filter main circuit 38.
and each multiplier 64, 68,...82, 73, 7
4 and 81 perform serial calculations with predetermined time relationships.
It's starting to look like this. Therefore, each multiplier 64,
Signals for 68,...82, 73, 74, 81
Input timing must be properly controlled, and
For this purpose, a delay circuit 7 is installed at the location shown in FIG.
7, 78, 79, and 80 are provided. Pole filter 42 and zero filter in FIGS. 4 and 5
between the input signal and the output signal in the filter 43
The time delay is determined by a 12-stage filter in the polar filter 42.
32 time slots in each of units L1 to L12
Total 384 time slots due to delays
There are 4 sampling periods, and 43 zero filters.
In this case, there are 3 sampling periods. Filters of the polar filter 42 and zero filter 43
coefficient K₁~K₁₅is the filter coefficient supply circuit 41
(Figure 3). This filter coefficient K₁
~K₁₅are predetermined multipliers 64, 68,...82, 7
3, 74, and 81 are now given in parallel.
However, in this example, the filter coefficient
From the supply circuit 41 to the digital filter main circuit 38
The filter coefficient K given to is each filter coefficient
K₁~K₁₅becomes a temporal serialization of
There is. Form of serialized filter coefficients K
The mat is illustrated in FIG. As an example,
One filter coefficient is 8-bit digital data.
and 15 filter coefficients K₁~K₁₅all bits of
The number of bits is 120 bits. Therefore, one tone (one frame)
Filter coefficient K for the filter channel₁~K₁₅of
The number of time slots required for serialization is 120.
These are sent out in 4 filter channels in a time-division manner.
The number of time slots required to do this is 120 x 4 =
480". When this filter coefficient K is serial
1 cycle time of divided transmission (480 time slots)
is the 5 sampling period (480
÷96=5). Referring to Figure 7a, the filter for one channel is
The filter coefficient serial data K is the zero filter 43
(K₁₅,K₁₄,K₁₃
) and then the subsequent stage of the polar filter 42.
(K₁₂,K₁₁…K₂,K₁of
(in order). And 8
Serial data of individual filter coefficients per bit
In this case, the upper bits start with sign bit SB.
The bits are sent in order starting from the top (MSB is the most significant bit).
(LSB indicates the least significant bit). digital
Inside the filter main circuit 38, the filter coefficient series
Shift Aldata K sequentially and select individual files.
ruther coefficient K₁~K₁₅Convert from serial to parallel,
Predetermined multipliers 64, 68,...82, 73, 74,
81 (Figures 4 and 5)
There is. per channel as shown in Figure 7a.
The data K serialized in the format is further shown in Figure b.
Each filter channel ch1 to ch4 as shown in
(in the order of ch1, ch2, ch3, ch4) hours and minutes between
It is multiplexed. Figure 8 shows the digital data in Figures 1 and 3.
This shows a more detailed embodiment of the filter section 14.
be. For details, Figure 8 is shown in Figures 1 and 3.
used as the digital filter section 14
One integrated circuit capable of digital
Internal configuration of filter circuit device (chip) DFC
FIG. Digit in Figure 1
The filter section 14 has a daisy filter as shown in FIG.
A structure using only one filter circuit device DFC.
or by combining multiple DFC devices.
may be configured. In Figure 8, the
The same reference numerals are given to the parts corresponding to each circuit 37 to 43.
It is numbered. That is, one digital
The filter circuit device DFC can be broadly classified as shown in Figure 3.
Similarly, the filter input control circuit 37, digital
filter main circuit 38, output control circuit 39, tie
timing signal generation circuit 40 and filter coefficient supply circuit
41, and the digital filter main circuit.
38 is a polar filter consisting of a 12-stage latex filter.
filter 42 (see Figure 4) and second-order zero filter 4
3 (see Figure 5). Musical sound signal input terminal I₁,I₂,I₃for each subseries
Serial digital music messages corresponding to #1 to #3
No. S₁,S₂,S₃are applied respectively. Filter input system
The control circuit 37 connects the terminal I₁~I₃each faith given by
No. S₁~S₃AND circuit 8 for individually gating
3, 84, 85 and these AND circuits 83 to 8
In order to add the serial musical tone signals output from 5.
and a serial adder 86. daisy
The tall filter main circuit 38 includes the above-mentioned polar filter 4.
2 and zero filter 43, these filters
Selection for switching connection combinations of 42 and 43
87, 88, and 89. selector 87
The first input A of the input terminal F_igiven from
A musical tone signal is input, and a serial signal is input to the second input B.
Serial musical tone signal S output from adder 86_ibut
input, and the third input C is the zero filter 43.
Output signal Z_pis input. Output S of selector 87
Serial musical tone signal output from (this is converted into FS)
) is the first stage filter unit of the polar filter 42.
Forward input terminal FS of Tsuto L1_i(See Figure 4)
be done. In addition, the first stage filter of the polar filter 42
Reverse output terminal BS of unit L1_p(See Figure 4)
is output terminal B_pgiven to. The final stage filter unit L of the polar filter 42
12 forward output terminals FS_p(See Figure 4) is the delay time.
72 and output terminal F._pand select
89 is applied to the second input B of the data input terminal 89. selector 8
The first input A of 9 is connected to the serial adder 86 or
serial musical tone signal S output from_iis input.
This serial musical tone signal S_iand the selector 87
The serial musical tone signal FS output from the
Power terminal I₁~I₃serial musical tone signal S given to₁~
S₃The data format is the same as that of
The same is true for the following (see Figure 6b). Figure 8 Delay
The circuit 72 has the same function as the delay circuit 72 in FIG.
It is something that The output signal of this delay circuit 72 is
A second input B of the rector 88 is provided. Selek
The first input A of the input terminal 88 has a reverse input terminal B._ifrom
The output S
is the last filter unit L1 of the polar filter 42.
2 reverse input terminal BS_i(See Figure 4)
ing. Further, the output S of the selector 89 is zero.
Input terminal ZS of filter 43_i(See Figure 5)
has been done. Output terminal ZS of zero filter 43_i(No.
Serial musical tone signal Z output from (see Figure 5)_pteeth
As mentioned above, when applied to input C of selector 87,
AND circuits 90, 91, both of the output control circuit 39,
92. In the digital filter main circuit 38, one
As an example, the polar filter 42 and the zero filter 43
Connection can be switched in three ways. One of them
In this case, the polar filter 42 is placed in the front stage, and the zero filter 4 is placed in the front stage.
3 is the latter stage, and both are connected in series.
Ru. The other is, on the contrary, the zero filter 43.
The front stage and the polar filter 42 are the rear stage, and both are connected.
They are connected in series. Yet another thing is extremely futuristic.
Filter 42 is used alone, and zero filter 43 is used.
No wiring should be made. This way
Disconnecting the eel filter 42 and zero filter 43
Replacement is with multiple pieces as the digital filter section 14.
In combination with the digital filter circuit device DFC
It works effectively when used. pole filter 42
and zero filter 43 to control connection switching.
, control codes C1 and C2 are set to selectors 87 and 8.
8,89. Details of connection switching mode and control codes C1, C
The detailed contents of 2 are omitted, and only 1 data is provided.
Digitizing the digital filter circuit device DFC independently
It is used as a tall filter section 14, and is used as a polar filter section 14.
2 in the front stage and zero filter 43 in the rear stage.
The explanation will proceed assuming that the two are connected in series. the spot
In this case, both control codes C1 and C2 are signal “1”.
It will be done. The selector 87 selects codes C1 and C2.
“11” selects input B, and selector 88 selects input B.
Select input B with code C2 “1” and select
In the controller 89, input B is input by code C2 “1”.
select. Therefore, the serial number of the input control circuit 37
Serial musical tone signal S output from adder 86_ibut
Pole filter as signal FS via selector 87
42 forward input terminals FS_iis input into this pole file.
Forward output terminal FS of router 42_poutput signal is selected.
input terminal ZS of the zero filter 43 via the input terminal 89._i
and the forward output terminal FS_poutput signal of
signal delayed by 32 time slots in delay circuit 72
is the reverse input of the polar filter 42 via the selector 88.
force terminal BS_iFeedback will be provided to In this way, the pole
Filter 42 in the front stage, zero filter 43 in the rear stage
The two are connected in series. The timing signal generation circuit 40
Based on the synchronization pulse SYNC input as
Predetermined types for controlling real filter operations
Mining signals KL, LD, SH and serial file
Each filter channel ch1~ in the filter coefficient K
Channel synchronized with ch4 time division timing
Selection code Kch and serial musical tone signal S₁~S₃to
Time and minute of each filter channel ch1 to ch4 in
Channel selection code synchronized with split timing
Sch, and to serialize the filter coefficients
Generate synchronization pulses KSYNC, respectively. Taimin
Signals KL, LD, SH are sent to the poles via line 95.
The first stage filter unit L1 of the filter 42 (the first
(see Figure 4). Filter coefficient supply circuit
Serial data of filter coefficients output from 41
The filter K is also connected to the first stage unit L1 of the polar filter 42.
Supplied. Serial filter as described below
The coefficient data K is sequentially scanned through each stage in the polar filter 42.
Then, after passing through line 93, it reaches zero point.
filter 43, and each stage in this zero filter 43.
But it is shifted sequentially and finally from serial format to
Each coefficient is converted to parallel format and placed in a given stage.
K₁~K₁₅is beginning to be distributed. Taimi
The switching signals KL, LD, and SH are serial filter coefficients.
It is used to convert K into parallel. obey
These signals KL, LD, SH are connected to line 94.
The signal is also applied to the zero filter 43 via the filter. Described later
As shown, the signal KL is applied to each stage of filters 42 and 43.
Although they are given simultaneously, the signals SH and LD are serial
Similar to the filter coefficient K, it is sequentially shifted at each stage. to the first stage of the polar filter 42 via line 95.
One of the input timing signals KL, LD, and SH
An example is shown in FIG. 9. Also, selector
87 to the first stage filter of the polar filter 42.
Serial musical tone signal FS input to unit L1
time-shared channel state (i.e. S₁~S₃time division
Channel status) Figure 9 shows ch1 to ch4.
It looks like the FS column. Similarly, K in Figure 9
1 of the polar filter 42 via line 96.
Serial file given to unit L1 in row
time division channel state ch1~ of data coefficient data K
ch4 is shown. In Figure 9, the signal wave
The numbers attached to the figure are within one sampling period.
The number indicating the order of the time slot (see Figure 6a)
to indicate). Signal FS and
The details of data K are shown in Figure 6b and Figure 7a.
That's right. Serial filter coefficient data K and timing
The generation pattern of the signals KL and LD is 5 of the musical tone signal FS.
The sampling period is repeated as one cycle.
It is. Each of these five sampling periods is
to the fifth sampling period, the timing signal
No. KL is the 23rd time of the 1st sampling period.
Lot, 47th time slot of 2nd sampling period
71st time slot of 3rd sampling period
95th time slot of the 4th sampling period
This is a signal in which pulses are generated at
The period is 120 time slots. Also, Taimi
The switching signal LD has 120 time slots like KL.
It is a signal with one period, and one time period is shorter than KL.
This is a signal that generates a pulse with a lot delay. Siri
In the alpha filter coefficient data K, as described above,
120 ties for one channel filter coefficient
Muslot is assigned. First, the first San
2nd sample from the 23rd time slot of the pulling cycle
120 tabs up to the 46th time slot of the pulling cycle
Channel ch1 file in imslot
The coefficient K of the signal KL is assigned below.
change every 120 time slots in sync with the
The coefficients K of channels ch2, ch3, and ch4 are assigned sequentially.
ing. Timing signal SH has 24 time slots
24th, 48th, 72nd, 96th time slot in the period of
This occurs repeatedly. The chip generated from the timing signal generation circuit 40
The yarn selection code Kch is shown in column K in Figure 9.
The time division channel timing of filter coefficient K such that
Indicates each channel ch1 to ch4 in synchronization with the
Indicates the code content. Also, select the other channel
The code Sch is a serial number as shown in the FS column in Figure 9.
to the time-division channel timing of the musical tone signal FS.
Code indicating each channel ch1 to ch4 in synchronization
Indicate the content. The filter coefficient supply circuit 41 supplies filter coefficients.
This depends on ROM97 and tone parameter TP3.
A circuit for controlling reading of the ROM97 of
Contains. According to tone parameter TP3
The circuit for controlling readout of ROM97 is
Shift register 98, latch circuit 99, write and
Random access memory that can be read and read freely (hereinafter referred to as
RAM) 100, including selector 101
There is. Tone parameter TP3 has been serialized
Consists of parameter data PD, shift register
98 and latch circuit 99 use this serial data PD.
A serial/parallel converter that converts
function. The tone selection device 12 (FIG. 1) is
As information indicating timbre parameter TP3, Syria
Parameter data PD and its serialization
Timing pulse that indicates the reference timing for conversion
PE and output the digital signal via terminals T2 and T3.
It is supplied to the tar filter section 14. tone like this
To convert parameter TP3 into serial data
Therefore, from the tone selection device 12 to the digital filter
This is useful because the wiring to the section 14 can be simplified.
It is advantageous. An example of the tone selection device 12 is shown in FIG.
There is. Equipped with multiple tone selection switches TC-SW
The output is input to the encoder 102.
be done. Tone selection switch TC- depending on the player
When any SW is operated, that switch is
A code signal indicating is output from the encoder 102.
Ru. Also, when the switch TC-SW is operated,
AND circuit for load control input L of latch circuit 103
A load pulse is applied from path 104, and the encoder
The output code signal of the driver 102 is sent to the latch circuit 103.
It is captured. latched in latch circuit 103
Code signal, i.e. a code indicating the selected tone
The signal is input to the address of the tone parameter memory 105.
given to power. The tone parameter memory 105 is
Tone parameters corresponding to various selectable tones
This is a latch circuit that stores the data shown in advance.
selected according to the code signal given from 103.
Read the tone parameter data corresponding to the tone
put out. Of this, the digital filter section 14 is given
The parameter data TP3 to be set is a latch circuit.
106 in parallel. Latch circuit 106
The load control input L is output from the AND circuit 104.
The applied load pulse is delayed by flip-flop 1.
07. Therefore, latch circuit 1
The latch timing of 06 is that of the latch circuit 103.
It is slightly behind that. This is latch circuit 1
The tone pattern corresponding to the code signal latched to 03
The parameter TP3 is reliably read from the memory 105.
The latch operation of the latch circuit 106 is performed by waiting for the
This is to ensure that they do the following. For example, the tone parameter TP3 is a 10-bit day.
digital data, of which 5 bits are selected.
This is the tone code TC that represents the tone of the 3-bit tone.
is the musical tone signal S of each sub-sequence #1 to #3₁~S₃brain
which should be passed through the digital filter main circuit 38.
Filter enable signal FE1, FE indicating strength
2, FE3, and 2 bits give this tone.
Which series USL, USP, UCS,
Is it of LSP, i.e. which filter
Should this tone be given to channels ch1 to ch4?
This is the channel code CH. latch circuit
106 has 10 latching points and the parameters
Each bit of data TP3 is latched. Latsuchi
The output signal at each latch point in circuit 106 is
to one input of the control circuits 108, 109, 110.
are input respectively. The shift register 111 has 11 stages.
from the delay flip-flop 107 to the first stage.
The pulse signal given to the clock is converted to the clock pulse φ.
Therefore, they are shifted sequentially. of shift register 111
The output signals from the 1st stage to the 10th stage are
The other of the 10 AND circuits 108, 109, 110
are input to each input. Each AND circuit 108,1
All outputs of 09 and 110 enter the OR circuit 112.
This OR circuit 112
The output signal is the serial data of tone parameter TP3.
The data is given to the digital filter unit 14 as a data PD.
It will be done. 11th stage of shift register 111
The output signal is the set input of flip-flop 113.
is given to S and as a timing pulse PE.
and is applied to the digital filter section 14. The input pulse sequence in the shift register 111
Indicate the soft timing from 1 to 11, and
An example of the status of serial data PD corresponding to
The result is as shown in FIG. 11. Also, timing
As shown in the figure, the pulse PE is at timing 11,
In other words, immediately after finishing sending the serial data PD,
Occur. The OR circuit 114 includes all tone selection switches.
Now that the TC-SW output signal is input
and when any switch is pressed, the corresponding
The output of the circuit 114 becomes a signal "1". Or times
The output signal of path 114 is applied to AND circuit 104.
and the reset input R of flip-flop 113.
join. The output Q of flip-flop 113 is slow.
The extension flip-flop 115 outputs the clock pulse φ.
After being delayed by one cycle time, the AND circuit 104
join. Normally, flip-flop 113 is set.
and the AND circuit 104 is operational.
It has become Noh. Tone selection switch TC-SW
When pressed, the output signal of the OR circuit 114 rises.
In response to this, the output of the AND circuit 104 becomes a signal.
It becomes “1”. At the same time, flip-flop 113
reset and delayed after one period of clock pulse φ.
The output of the extended flip-flop 115 falls to “0”
As a result, the AND circuit 104 becomes inoperable. obey
Then, the AND circuit 104 is connected to the tone selection switch TC.
−1 of clock pulse φ at the moment SW is pressed
Outputs short pulses with periodic time width. And this
Based on the output pulse of the AND circuit 104, the
As per serial data PD and timing pulse
PE is sent out. Timing pulse PE is generated.
Then, flip-flop 113 is set.
This will cause the tone selection switch TC-SW to
When pressed, the load pulse is output from the AND circuit 104.
The AND circuit 104 is activated so as to generate a
Set to operational state. The tone selection device 12 further includes various musical tone control operations.
It includes an operator 116, and the operation of this operator 116 is
The parameter generation circuit 117 generates a predetermined value according to the
Generates tone parameters. Tone parameter memo
Tone for filter control read out from the reli 105
Parameter data and parameters other than parameter TP3
Parameters output from the parameter generation circuit 117
Among the parameters, predetermined ones are tone parameters TP1 and TP.
2. TP4 as musical tone signal generator 11, control circuit
13 and are supplied to the external storage device 20, respectively. this
The tone parameters TP1, TP2, TP4 are TP3
Similarly, supply it in serial data format.
It's okay. In addition, in FIG. 10, the timbre selection device 12 is
Shown to be configured by REET circuit
However, the microcomputer method is not limited to these.
It may also be treated by In that case, the keyboard section 9 and
The key assigner 10 (Fig. 1) is also
It is possible to process using a computer method. Returning to Figure 8, the series of tone parameter TP3
The al data PD is input to the shift register 98.
Ru. The shift register 98 has 10 stages, and the shift register 98 has 10 stages.
When serial data PD is set by lock pulse φ
Shift control is performed in synchronization with the divided time slots.
cormorant. The timing pulse PE is the lock of the latch circuit 99.
is given to the code control input L. shift register 9
The output of each stage of 8 is paralleled to the latch circuit 99.
is input to the timing pulse PE.
When the output signal of each stage is
It is latched in the lock circuit 99. Serial data PD
The relationship between and timing pulse PE is as shown in Figure 11.
, so the first and second shift registers 98
Channel code CH enters the second stage, and
3. Filter enable signal to 4th and 5th stage
No. FE3, FE2, FE1 are included, and the 6th to 10th stages
Timing when the tone code TC enters the stage
Pulsed PE is supplied and these data are latched.
It is now securely latched to circuit 99.
Ru. RAM100 is for each filter channel ch1~ch
Also for storing tone code TC corresponding to 4.
RAM118 is for each filter channel.
Filter enable signal corresponding to ch1 to ch4
This is for storing FE1 to FE3.
RAM100 and 118 are each channel ch1~ch
It has a memory location (address) corresponding to 4.
Ru. To write control input W of RAM100, 118
is a flip-flop that delays the timing pulse PE
A delayed signal is provided at 119. write ad
The response specification input WAD is latched to the latch circuit 99.
channel code CH is given.
For data input of RAM100, latch circuit 99 is used.
The latched tone code TC is input.
For data input of RAM118, latch circuit 99 is used.
Latched filter enable signal FE1~FE
3 is input. New data in latch circuit 99
Immediately after TC, FE1~FE3, CH are taken in
RAM100 and 118 are in write mode, and this
specified by the new channel code CH
Tone code TC and signals FE1 to FE are added to the specified address.
Write 3 respectively. In this way, the tone selection operation
Each time (data PD, PE are given)
data is written to RAM100 and 118
Finally, each filter channel ch1~ch
The tone code TC of the tone selected corresponding to 4 is
Each file is stored in RAM100 and
Selected corresponding to Tatiyan channel ch1~ch4
Tone filter enable signals FE1 to FE3 are
Each is stored in the RAM 118. RAM100 read address specification input RAD
Channel selection for each channel ch1 to ch4
When the code Kch is from the timing signal generation circuit 40
given in parts. Read access of RAM118
The address designation input RAD is also connected from circuit 40.
The Jannel selection code Sch is given in a time-sharing manner.
Ru. RAM100, 118 performs reading.
This is a typeface that allows you to write even while you are in the
It belongs to Pu. Channel selection code Kch is
As shown in column K in Figure 9, each channel ch1~ch
The code signal indicating 4 is 120 bits per channel.
This occurs in a time-division manner over the width of the imslot.
RAM100 is set for each channel according to this code Kch.
Read the tone code TC of channels ch1 to ch4 in a time-sharing manner.
Extrude. On the other hand, the channel selection code Sch is the 9th
Each channel ch1 to ch4 as shown in the FS column of the figure.
The code signal indicating 24 times per channel
This occurs in a time-division manner depending on the slot width.
RAM118 is set for each channel according to this code Sch.
Filter enable signal FE1 for channels ch1 to ch4
~Read FE3 in a time-division manner. Tone code TC read from RAM100
is given to the control input of selector 101. Sele
Kuta 101 selects a filter according to the content of the tone code TC.
Filter coefficient read from filter coefficient ROM97
Select number. Filter coefficient ROM97 is the timbre
The selection device 12 selects various tones that can be selected.
A set of filter coefficients is stored in advance. Before
As mentioned above, one set of filter coefficients corresponds to one tone.
is the 15 filter coefficients K₁~K₁₅consisting of one
Since the filter coefficient is 8 bits, one set of filters is required.
The data coefficient is 120 bit data. 5 bits
There are 32 types of tones that can be selected by tone code TC.
For example, 32 sets of files are stored in the ROM97.
The router coefficients are stored respectively. timing signal
Read filter coefficients generated from generation circuit 40
The synchronizing pulse KSYNC is supplied to the ROM97.
It will be done. ROM97 is based on synchronization pulse KSYNC.
A frame consisting of 120 bits is generated at a predetermined timing.
Serial bit-by-bit order of filter coefficients in time
Next readout and this serial readout for all tones.
simultaneously and in parallel. read in parallel
Each set of serial filter coefficient data
The state is as shown in FIG. 7a described above. File for each tone read from ROM97
The serial data of the data coefficient is input to the selector 101.
be done. Selector 101 selects hours and minutes from RAM 100
one set according to the given tone code TC.
Select serial filter coefficient data. 1 cha
The tone code TC related to the channel is selector 101
synchronized to the time span of 120 time slots given to
Then, in ROM97, one set of files for 120 bits is used.
Serial readout of router coefficients is repeated
It's becoming like that. On the other hand, read from RAM100
The content of the tone code TC that is output depends on the channel selection.
Hours and minutes every 120 time slots according to code Kch
It changes depending on the situation. Therefore, each filter channel
Corresponds to the tone selected corresponding to ch1~ch4.
Serial data of 4 sets of filter coefficients is 120 bits.
Output from the selector 101 in time division for each imslot.
Powered. The sequence output from this selector 101
The channel state of real filter coefficient data is
This is the same as that shown in column K of Fig. 9. The output of selector 101 is the input of selector 120
given to A. to the other input B of the selector 120
is read from the external storage device 20 (Fig. 1).
Serial data KO of filter coefficient is connected to terminal T5.
given through. This serial filter coefficient data
The serial data format of data KO is selector 101.
It is exactly the same as the output from the 4-channel
Serial filter coefficient data for channels ch1 to ch4
data is time-division multiplexed as shown in column K of Figure 9.
It is something that B selection control input of selector 120
SB has a filter coefficient changeover switch 21 (Fig. 1)
The output signal KS of is given via terminal T4.
This signal KS is inverted to the A selection control input SA.
will be given something. Therefore, the switch 21
The output of the external storage device 20 or
or the output of selector 101 (i.e. ROM97
output) is selected. switch 21 is on
When the signal is on, the signal KS becomes “1” and the selector 12
External data KO is selected via the B input of 0
be done. When switch 21 is off or
signal when T21 is not connected to terminal T4
KS becomes “0” and the internal coefficient is transmitted via the A input.
Data is selected. In this way, selector 120
The selected serial filter coefficient data K is
The first stage filter of the polar filter 42 is
It is input to unit L1. The filter coefficient external storage device 20 is a digital
Filter coefficient provided inside the filter section 14
It may have the same configuration as ROM97, but the key
A time-varying filter based on the on signal KON.
It may also be configured to supply router coefficients.
An example of the latter type of external storage device 20 is the twelfth external storage device 20.
As shown in the figure. In Figure 12, the filter
The coefficient memory 121 stores multiple sets of filters for each tone.
Set the router coefficients in advance to correspond to multiple types of tones.
The timbre selection device 12 (Fig. 1,
To the timbre parameter TP4 given from Figure 10),
Therefore, there are multiple sets of filters corresponding to one tone.
select the number and send the selected filter coefficient to the address signal.
address signal given from the signal generation circuit 122
Read each set sequentially as time passes according to ADRS.
Extrude. The address signal generation circuit 122 has a key address.
Key-on signal given from Cyna 10 (Figure 1)
An algorithm whose value changes over time based on the number KON.
Generate address signal ADRS and use this address
The temporal change pattern of the signal ADRS is expressed as a timbre parameter.
Control according to the data TP4. Address in address signal generation circuit 122
FIG. 13 shows an example of the generation of the signal ADRS. key on
Address signal is generated in synchronization with the rising edge of signal KON.
The value of ADRS is reset to “0” and the specified attribute is
According to the rate, the value of the signal ADRS is "0",
It increases sequentially as "1", "2", etc. address signal
The value of No. ADRS is the predetermined sustain value A._Sreach
, the increase stops and the sustain value A_SMaintain
do. Eventually, when the key-on signal KON falls, the
The value of the signal ADRS according to a fixed decay rate
"A_S”, “A_S+1", "A_S+2”... and increases sequentially.
Then, when the final value "N" is reached, the increase stops,
Address signal ADRS according to key-on signal KON
The time change of ends. Filter coefficient memory 12
1, the file stored corresponding to one tone
The number of router coefficients is N, and the address signal
of each set according to the ADRS value “0” to “N-1”.
Filter coefficients are read out sequentially. Furthermore, Figure 13
, attack rate, decay rate, support rate.
Stain value A_Sis possible depending on the tone parameter TP4.
It is set differently. Assigned to each filter channel ch1 to ch4.
The types of tones that can be selected are known in advance, so you can easily select
Which filter channel ch1~ is the selected tone?
Whether it belongs to ch4 is determined by the contents of the tone parameter TP4.
It becomes clear from this. Therefore, filter coefficient memo
Re-121 supports each channel ch1 to ch4
and set the filter coefficients of the selected tone to each channel.
read out in time division according to file timing.
can do. Thus, the filter coefficient memo
From the library 121, a set of 120 bits of files are sent.
data of router coefficients in parallel and for each channel.
Channels ch1 to ch4 are read out in a time-division manner.
Also, one set of filter coefficients is the address signal ADRS.
It changes over time according to changes in . pa
Is the parallel/serial converter 123 the memory 121?
From 120-bit data read in parallel from
A set of filter coefficients consisting of
(consisting of 120 time slots)
It is for. Reference tie during serial conversion
Sync pulse for use as timing signal
SYNC is used. In this way, the external storage device 2
Serial filter coefficient data supplied from 0
As mentioned above, KO is as shown in column K of Figure 9.
It is a data format. A diagram that changes over time, as shown in Figure 12.
The storage device 20 that supplies the router coefficient KO stores the frequency
Useful for creating tones whose characteristics change over time.
stand. In particular, human voice sounds have delicate frequency characteristics over time.
, so the filter coefficient for human voice is
suitable for supplying. In other words, the desired human voice
The filter is adjusted to respond to changes in the frequency characteristics of the sound.
The filter coefficient memory 121 and
and address signal generation circuit 122.
It is. In addition, in Fig. 13, in the sustain section,
constant value A_Swith a constant frequency as the address signal ADRS.
I am trying to read the filter coefficients, but this
The address signal is not limited to this, but also in the sustain section.
It is also possible to slightly change the value of ADRS.
stomach. For example, in the sustain section, the address signal
By subtly and periodically changing the ADRS value, the filter
It is also effective to make the coefficient change slightly periodically.
It is fruitful. Returning to Figure 8, the data read from RAM118
The input filter enable signals FE1 to FE3 are
AND circuits 83 to 85 of the control circuit 37 and output control
AND circuits 124, 125, 126 of control circuit 39
are input respectively. Of AND circuits 83-85
Filter enable signal FE1 input there
~Those with FE3 set to “1” are operable.
and the corresponding serial musical tone signal (S₁~S₃
If one or more of these are selected and
input to a file adder 86. As mentioned above, RAM
Filter enable signal read from 118
Timing of channels ch1 to ch4 of FE1 to FE3
The program is a serial musical tone signal as shown in the FS column in Figure 9.
No. S₁~S₃matches the channel timing of
Ru. Therefore, each filter channel ch1 to ch4
of each sub-series with the combination set corresponding to
Serial musical tone signal S₁~S₃is selected. The details of the serial adder 86 will be explained.
and the adder 127 receives the input from the AND circuit 84.
Serial musical tone signal S that can be obtained₂And AND circuit 85?
Serial musical tone signal S given by₃and this
The output signal of the adder 127 and the AND circuit 83
Given serial musical tone signal S₁and adder 128
Add with . Both adders 127 and 128
Re-input C_iFull adder with own key
Yarii output C₀₊₁is passed through AND circuits 129 and 130.
and carry input C_iwill be entered respectively in
ing. Addition time when carry-out signal occurs
and carry output C₀₊₁The signal “1” is output from
There is one time slot between the
Assume there is a delay. As shown in Figure 6b
Serial musical tone signal S₁~S₃In this case, the upper bit is
More data is assigned to later time slots.
ing. Therefore, the output is delayed by one time slot.
C₀₊₁The carryout signal output from the
A input C_iBy adding to the
can be added to the higher-order data by 1 bit.
Ru. The other inputs of the AND circuits 129 and 130 are
The timing generated from the timing signal generation circuit 40
delay circuit 131 for one time slot.
The delayed signal is inverted by the inverter 132.
is given. Timing as shown in Figure 9
Signal SH is the 24th, 48th, 72nd, 96th time slot
This is a signal that becomes “1” at each time.
The output signal of the delay circuit 131 delayed by the muslot is
in the 25th, 49th, 73rd, and 1st time slots, respectively.
It becomes “1”. On the other hand, serial musical tone signal S₁~S₃teeth
As shown in Figure 6b, each channel ch1
~Lowest bit of serial musical tone signal of ch4
(LSB), the output signal of the delay circuit 131 is
The signal becomes “1” and the output of the inverter 132 becomes “1”.
It becomes “0”. As a result, each channel ch1~ch
In serial addition every 4, the least significant bit
Another channel in the (LSB) time slot
generated by the operation of the sine bit (SB) of the file.
The carry out signal is the carry input C._igiven to
You may be prohibited from doing so. On the other hand, the AND circuit 124 of the output control circuit 39
The other input of 126 is the control code C.₂is entered
ing. Output signal Z of zero filter 43₀This de
Output musical tone signal of digital filter circuit device DFC
When used as a control code C₁,C₂of
Of which C₂is determined so that it is always “1”
There is. Therefore, the output signal Z of the zero filter 43₀of
AND circuit 12 when used as an output musical tone signal
4 to 126 are always enabled and filter enable
The corresponding AND circuit 1
The outputs of 24 to 126 are “1” or “0”.
Ru. The outputs of these AND circuits 124 to 126 are
The signals are input separately to code circuits 90, 91, and 92. one
The output signals of the AND circuits 124 to 126 are inverted.
The signals sent to AND circuits 133, 134, 135
They are input separately, and each AND circuit 133 to 1
The other inputs of 35 are the serial music messages of each sub-series.
No. S₁~S₃are entered separately. AND circuit 90 and
The output of 133 is sent to the output terminal via OR circuit 136.
O₁and the outputs of AND circuits 91 and 134
is the output terminal O via the OR circuit 137₂given to
The outputs of AND circuits 92 and 135 are OR circuit 1.
Output terminal O through 38₃given to. Output signal Z of zero filter 43₀Output musical tone signal
When used as a filter enable signal
Channel timing when FE1 to FE3 are “1”
The signal output from the zero filter 43 in response to the
No. Z₀is “1” for signals FE1 to FE3.
each through corresponding AND circuits 90, 91, 92.
Output terminal O corresponding to sub-series₁,O₂,O₃distributed to
be done. In that case, the filter enable signal FE
Compatible with sub-series where 1 to FE3 are “0”
AND circuits 133, 134, 135 are enabled.
Serial musical tone signal S that is processed and does not pass through a filter₁~
S₃is the output terminal O₁,O₂,O₃guided by. In other words,
Output signal Z of zero filter 43₀is not distributed
Output terminal O₁~O₃Input musical tone signal S₁~S₃is that
I will be guided. On the other hand, the output signal Z of the zero filter 43₀Output effortlessly
If not used as a sound signal, code C₂but
“0” and AND circuits 133 to 135 are always
AND circuits 90 to 92 are always enabled.
When disabled, all output terminals O₁~O₃type in
musical tone signal S₁~S₃will be guided as is. Polar filter 42 and zero filter in FIG.
43 is the same as that shown in Figures 4 and 5.
can be used. By the way, Figure 4,
Figure 5 shows only the basic configuration, and the serial
Convert the filter coefficient data K to parallel data and
Multipliers 64, 68...82 of units L1 to L12
and each multiplier 73, 74, 8 of the zero filter 42
Circuit for distributing to 1 channel and multiple channels
Enables time-sharing filter calculations for channels 1 to 4.
circuit and serial filter operation.
Illustrations of circuits and the like are omitted. There
Then, a polar fibre, consisting of the basic configuration as shown in Figure 4, is constructed.
Details of filter units L1 to L12 of filter 42
A detailed example will be explained with reference to Figure 14, and then
A detailed example of the zero filter 43 will be explained. FIG. 14 shows the first stage filter of the polar filter 42.
A detailed example of unit L1 is shown. other
Filter units L2 to L12 are also exactly the same.
They have one or almost the same configuration. Adder in Figure 9
61, 62, 63 and delay circuits 65, 66, 67
Circuits corresponding to are given the same symbols in Figure 14.
be. Also, a circuit section corresponding to the multiplier 64 in FIG.
The minutes are indicated comprehensively using the same symbols in Figure 14.
There is. Serial using timing signals KL, LD, and SH
Parallel convert the alpha filter coefficient data K and multiply
The coefficient distribution circuit 139 that distributes to the calculator 64 is shown in FIG.
Although it was omitted in Figure 14, it is not shown in Figure 14.
Ru. This circuit 139 will be explained first. still,
A delay of one time slot in the figure.
The circuit is represented by a block marked with the symbol “D”.
Unless otherwise specified, the information shall be displayed.
Reference numbers for individual timeslot delays are omitted.
Omitted. The coefficient distribution circuit 139 is connected to the delay circuit array 14
0, 142, 143 and latch circuit 141 and fi
144. 1 of 8
Delay circuit with cascaded time slot delay circuits
column (i.e. 8 stages of series shift parallel output type)
shift register) 140 and this delay circuit array 14
8 1-bit bits input each delay circuit output of 0.
The latch circuit 141 consisting of a gate type latch circuit is
Parallel conversion of real filter coefficient data K
It is for. The delay circuit array 140 has a serial
filter coefficient data K is input. this day
The data K is sequentially shifted by each delay circuit for 8 times.
After the lot is applied to the next stage filter unit L2.
It will be done. To each latch control input L of the latch circuit 141
is given a timing signal KL, and this signal
When the signal KL is “1”, each delay of the delay circuit array 140
Latch the output of the circuit to each latch circuit. Furthermore, this
In the example, the output timing of the latch circuit 141 is
One time slot behind the actual timing
shall be. 142 and 143 are 8 pieces like 140
Delay by cascading one time slot delay circuit of
Circuit array (series shift parallel output type shift register)
It is. The delay circuit array 142 has a timing signal.
LD is input, and timing signal SH is input to 143.
is input. These signals LD and SH are delay circuit arrays.
It is sequentially delayed by each delay circuit of 142 and 143, and
After the time slot, the next stage filter unit L2
given to. Delay circuit arrays 140, 142, 143 and latches
Circuits similar to circuit 141 are used in other filter units.
It is also provided in L2 to L12. Therefore, the
Real filter coefficient data K, timing signal
LD and SH are each filter unit L1 to L12.
They are sequentially delayed by 8 time slots. On the other hand,
The timing signal KL is applied to each film without delay.
It is simultaneously supplied to unit units L1 to L12.
In addition, the final stage filter unit of the polar filter 42
The data K, the signal KL, output from the gate L12,
KD and SH are connected via lines 93 and 94 (Fig. 8).
and is input to the zero filter 43. As mentioned later
, the three multipliers 73, 7 of the zero filter 43
4,81 (Figure 5), the coefficients in Figure 14
Distribution circuit 139 (delay circuit array 140, 142, 14
3. Same as latch circuit 141, storage device 144)
A circuit is provided, and from lines 93 and 94
The input data K and timing signals LD and SH are
8 times each for 3 stages of zero filter 43 calculation stage
Slots are sequentially delayed. Also, the timing
The signal KL is passed through zero filter 4 without being delayed.
It is simultaneously supplied to each of the three processing stages. From the timing signal generation circuit 40 (FIG. 8)
1st stage filter unit L1 via input 95.
Each timing signal KL, LD, SH given to
As mentioned above, the pulse generation timing is as shown in Figure 9.
It's getting old. Also, from selector 87 (Fig. 8)
The series given to the first stage filter unit L1
Channel timing of musical tone signal FS, and
from selector 120 (FIG. 8) via line 96.
Serial filter assigned to unit L1
The channel timing of the numerical data K is also as shown in Figure 9.
It is. As is clear from Figure 9, the amount for one channel is
Serial transmission of filter coefficient data K has been completed.
Immediately thereafter, timing signal KL is generated. Figure 7
Serial file for one channel as shown in a
The coefficient data K is obtained from the subsequent calculation stage (multipliers 81 and 7).
4,73, for filter unit L12-L1)
corresponding one (K₁₅,K₁₄,...K₁) is sent in order from
It will be done. Therefore, when timing signal KL is generated,
and the individual polar filter units L1 to L12 and
8-bit filter corresponding to zero filter calculation stage
ruther coefficient K₁~K₁₅are the given operations corresponding to each
stage delay circuit array (corresponding to 140 in Fig. 14)
), and these are the latitudes in each operation stage.
In the Tsuchi circuit (corresponding to 141 in Figure 14)
Each is latched. Thus, the serial filter
Each filter unit L1 has a predetermined coefficient data K.
- Parallel in L12 and zero filter operation stage
data K₁~K₁₅is converted to This parallel data is
The latch circuit remains closed until the next latch timing arrives.
(141 in FIG. 14). for example,
23rd time of the first sampling period shown in Figure 9
When the timing signal KL is generated in the slot
The filter coefficient data of channel ch4 is
L1 to L12 and zero filter calculation stage
Latch each circuit (141 in Figure 14).
and then the 47th time slot of the second sampling period.
Wait until the timing signal KL is generated at
The filter coefficients of channel channel ch4 are held. Therefore,
The filter coefficient output from the latch circuit 141
When channels ch1 to ch4 are shown, KD in Figure 9
become that way. In FIG. 14, the filter coefficient storage device 14
4 is the filter coefficient of each channel ch1 to ch4
and store these as serial numbers for each channel.
Multiplier 64 according to the timing of musical tone signal FS
It is intended to supply Filter coefficient memory
Device 144 includes a filter coefficient corresponding to each bit of the filter coefficient.
It consists of eight shift registers SR1 to SR8.
Ru. Each bit of the 8-bit filter coefficient is
The output of each latched latch circuit 141 is
KDi input of corresponding shift register SR1 to SR8
added to the force. Shift register SR1 to SR8
Of these, SR1 is the least significant bit of the filter coefficient.
(LSB), and SR7 is the most significant bit of the coefficient.
(MSB), SR8 is sign bit (SB)
corresponds to In addition, 8-bit filter coefficient data
is expressed in sine magnitude form.
The lower 7 bits represent the absolute value of the filter coefficient.
The positive sign bit (SB) of the coefficient
Represents a negative sign (“0” is positive, “1” is negative)
vinegar. The most significant bit (MSB) or shift of the coefficient
The weight of the bit corresponding to register SR7 is decimal.
Suppose that the number is 0.5. Timing input to filter unit L1
Signals SH and LD are input to SHi of shift register SR1.
are input to the power and LDi inputs, respectively. Also, the delay time
These signals LD and SH are connected to the path arrays 142 and 143.
The sequentially delayed ones are shift registers SR2 to SR.
It is input to the SHi input and LDi input of 8, respectively.
Note that the fifth stage in the delay circuit arrays 142 and 143
Delay circuits 145 and 146 input to any register
However, this is due to the operation in the multiplier 64, which will be described later.
This was established to accommodate calculation time delays.
Ru. Each of the shift registers SR1 to SR8 is the 15th shift register.
It is configured as shown in the figure. 1 time slot
four delay circuits 147, 14 with a delay time of
4 stage shift by 8,149,150
Registers are configured. KDi is a data entry
Yes, LDi is new data import control input, SHi is
This is a shift control input. New given to KDi input
Data is signaled to both LDi and SHi inputs.
When “1” is given, the AND circuit 151 and the
delay circuit 1 of the first stage via the circuit 160.
47. SHi input signal is “0”
When this signal is inverted, the output of the inverter 164 is
The force is “1” and the AND circuit 15 for holding
3,155,157,159 are enabled for each delay.
The outputs of extension circuits 147, 148, 149, 150 are
The AND circuits 153, 155, 157, 159 and
and via OR circuits 160, 161, 162, 163.
and self-maintained. SHi input signal is “1”
When the above-mentioned AND circuits 153, 15 for holding
5,157,159 has been disabled and the shift anchor has been disabled.
Enables code circuits 152, 154, 156, 158
be done. As a result, the first stage delay circuit 1
47 output Q1 is the second stage delay circuit 148
Then, the output Q2 of the second stage is the delay of the third stage.
The output Q3 of the third stage is connected to the extension circuit 149 by 4 steps.
The fourth stage output is input to the stage delay circuit 150.
The force Q4 is applied to the first stage delay circuit 147, respectively.
Shifted. In addition, the LDi input signal is inverted.
The signal inverted at 165 is input to AND circuit 152
The new data is transferred to the first stage delay circuit.
When importing into 147, output Q4 of the 4th stage
is prohibited from being shifted to the first stage.
Ru. With the above configuration, the timing signal LD
Every time the original signal “1” is applied to the LDi input
(every 120 time slots) Filter coefficient data
From the latch circuit 141 (Fig. 14) to the shift register
The data is taken into the first stage of SR1 to SR8, and
The signal “1” based on the timing signal SH is
every time applied to the SHi input (every 24 time slots)
) Each stage of each shift register SR1 to SR8
data is shifted to the next stage. Shift register of first stage filter unit L1
Looking at the data SR1, via the KDi input
The latch circuit 14 is added to the first stage delay circuit 147.
It is time for the filter coefficient data of 1 to be imported.
This is when the ringing signal LD is generated. In other words, the first
In the 24th time slot of the sampling period, the
The filter coefficient data of channel channel 4 is
channel in the 48th time slot of the ring period.
The ch1 data is the 72nd sampling period of the 3rd sampling period.
In the time slot, the data of channel ch2 is
At the 96th time slot of the 4th sampling period,
Channel ch3 data is the 1st stage respectively.
(LD, KD and L1 in Figure 9)
(See SR1). During one period of timing signal LD
Timing signal SH is generated 5 times, so shift
Shifts in register SR1 are performed five times.
Therefore, the 24th time slot of the first sampling period
Load it into the first stage delay circuit 147 with
The data of channel ch4 is 48th, 72nd, 96th,
Every time the signal SH occurs in 24 time slots (the
(See SH in Figure 9), 2nd stage, 3rd stage,
Shifted to the 4th stage, then the 1st stage,
Next, the 48th time slot of the second sampling period
The data of channel ch1 is delayed in the first stage.
When the chip is taken into the extension circuit 147, the chip taken in earlier is
Jannel ch4 data is the second stage delay time.
148. In this way, the shift register
Each stage of star SR1 (delay circuits 147 to 15
0) is responsible for the filters of each channel ch1 to ch4.
The numerical data is taken in sequentially. timing signal LD
The shift is performed in 4 periods, or 5 sampling periods.
Each channel ch1 to ch in register SR1
One rewrite of the filter coefficient data in step 4 is completed.
Ru. This rewriting is done every 5 sampling cycles.
It is done repeatedly. Due to the above control
and shift register of first stage filter unit L1.
Each stage of star SR1 (delay circuits 147 to 15
0) outputs Q1, Q2, Q3, Q4
Channels ch1 to ch4 of the filter coefficients are
It changes as shown in SR1 of L1 in the figure. Returning to Figure 14, filter unit L1
SHi input of other shift registers SR2 to SR8
The SHi input of shift register SR1 is connected to the power and LDi inputs.
Signals SH and LD applied to power and LDi inputs respectively
Next, a signal delayed by one time slot is added.
Therefore, these shift registers SR2 to SR8
The pattern of changes in the outputs Q1 to Q4 of each stage in
For turns, use the shift lever shown in SR1 of L1 in Figure 9.
It is the same as that of Jista SR1, but the type of change is
Assuming that the timing is sequentially delayed by one time slot at a time.
Become. However, between shift registers SR5 and SR6
are provided with extra delay circuits 145 and 156.
Therefore, the change in shift register SR6 is
The timing (shift timing) is that of SR5.
The event will also be delayed by two time slots. In this way, one
A total of 8 time slots per filter unit.
Each shift register SR1 to SR with a delay
8 change timing (shift timing) sequentially
It shifts. In the filter unit L1 of FIG. 14,
4 as the output Q of shift registers SR1 to SR8
The output Q4 of the stage (see Figure 15) is taken out.
and is input to the multiplier 64. Now, input from the forward input terminal FS-IN (FSi).
The received serial musical tone signal FS is sent to the inverter 166.
It is inverted and applied to the B input of adder 61.
The adder 61 is a full adder, and the adder 61 is a full adder.
and then feed the filter unit L2 from the next stage.
The musical tone signal to be picked up is applied to the A input. C₀₊₁
is the carry-out output, and the carry-out signal
The addition timing at which the signal occurred and this output C₀₊₁signal to
There is one tie between the timing when “1” is output.
Assume that there is a time delay in Muslot. Kyari
Iout output C₀₊₁The output signal of is passed through OR circuit 2.
and is applied to the Ci input of the adder 61. In Figure 6b
As shown, in the serial musical tone signal FS, the upper
The smaller the number of bits of data, the slower the time slot.
Assigned. Therefore, one time slot delay
Output C₀₊₁Carry out signal output from
By adding
can be added to the higher-order data by 1 bit.
Ru. The other input of the OR circuit 2 is a delay circuit array 143.
The signal output from the first stage delay circuit 167 of
SH1 is given. This signal SH1 is shown in Figure 9.
The timing signal SH generated as shown in Fig.
The slots are delayed, and the 25th, 49th, and
73 and becomes “1” in the first time slot.
It's a signal. On the other hand, input terminal FS-IN (FSi)
The input serial musical tone signal FS is as shown in Figure 6b.
Therefore, the series of each channel ch1 to ch4
Timing of the least significant bit (LSB) of the musical tone signal
In response to the switching, the signal SH1 becomes “1”.
Therefore, the adder 61 calculates the least significant bit (LSB).
“1” is added repeatedly at the appropriate timing. This operation
The operation is from input terminal FS-IN to B input of adder 61.
To convert the musical tone signal FS given to a negative value into a negative value,
It's a special thing. In other words, input the musical tone signal FS.
It is inverted by the inverter 166 and its least significant bit is
(LSB) by adding 1 to the two's complement form
An operation is being performed to convert the expression to a negative value.
Furthermore, the musical tone signal FS given to the input terminal FS-IN is also
Negative values are assumed to be expressed in two's complement format.
Ru. Therefore, when the musical tone signal FS has a negative value, the upper
2 compensation by the inverter 166 and signal SH1.
It can be effectively converted into a positive value by the digitization operation.
It becomes. In this way, in the adder 61, the reverse input
A input via terminal BS-IN and delay circuit 66
Amplitude of the given feedback musical tone signal
The power applied from the data to the forward input terminal FS-IN
An operation is performed to subtract the amplitude data of the sound signal.
Ru. The output of adder 61 is input to delay circuit 168.
and applied to the data input of the latch circuit 169.
It will be done. between the adder 61 and the delay circuit 168.
OR circuit 202, which will be described later, from the input point P1
The part up to output point P6 shown on the output side of
corresponds to the multiplier 64. Feedback musical tone signal and input musical tone signal FS
The output signal of the adder 61 indicating the difference between
Exclusive OR circuit 3 delayed by 24 time slots at 8
given to. The output of exclusive OR circuit 3 is sent to adder 4
is given to the A input of Delay circuit 168, latch
The circuit 169, the exclusive OR circuit 3 and the adder 4 are
The output signal of the adder 61 expressed in the complement form of
Sign magnitude (sign bit and absolute)
value) format. The latch control input L of the latch circuit 169 has a tie.
A timing signal SH is input. Signal SH is generated
24th time slot or 48th, 72nd, 96th tie
At Muslot, the acceleration is 61 and the sine bit is
(SB) is output (Figure 6b)
reference). Therefore, the value of sine bit (SB) is
It is latched in the hold circuit 169. This latch circuit 1
The output of 69 is sent to exclusive OR circuit 3 and AND circuit 5.
Given. For example, the 24th time slot
Set the sign bit (SB) for channel ch1.
and send the latched signal from the 25th time slot.
During 24 time slots up to the 48th time slot
When the latch circuit 169 is outputting, the first
to 24th time slot, output from adder 61.
24 times the signal related to channel ch1
The lot-delayed signal is output from the delay circuit 168.
It will be done. Therefore, the latch circuit 169 outputs
Sign bit signal and output from delay circuit 168
The channels of the signals are matched. latch circuit
Sign bit signal latched to 169 is “0”
That is, when it is positive, the output signal of the delay circuit 168
It passes through the exclusive OR circuit 3 as it is, and the A of the adder 4
It is output as is from the S output via the input. sa
When the inbit signal is “1” or negative, the delay
The output signal of circuit 168 is inverted by exclusive OR circuit 3.
It will be done. At this time, the output of the latch circuit 169 becomes “1”.
Therefore, the AND circuit 5 is enabled and the signal SH1 is
“1” is output from AND circuit 5 at the timing.
is input to the Ci input of the adder 4 via the OR circuit 6.
“1” is given. This signal SH1 is the timing
This is a signal obtained by delaying the signal SH by one time slot.
It corresponds to the least significant bit. For example, Chiyanne
The signal related to channel ch1 is output from the delay circuit 168.
In the 25th to 48th time slots,
At the 25th time slot, signal SH1 becomes “1”,
Output signal of exclusive OR circuit 3 regarding the least significant bit
Adder 4 adds 1 to . Result of addition
The resulting carry-out signal is delayed by one time slot.
output C₀₊₁output from AND circuit 7, OR
It is applied to the Ci input via circuit 6. and circuit
The other input of 7 is the signal SH1, which is connected to the inverter 170.
A signal 1 inverted at is given. lowest bit
At the calculation timing of
Then, the AND circuit 7 is disabled and the calculation timing is
The signal from the most significant bit of the channel preceded by
The layout-out signal is prohibited. exclusive
Inversion in OR circuit 3 and addition of 1 to the least significant bit
By arithmetic, the negative value expressed in two's complement becomes absolute.
Converted to a pair value. With the above configuration, from the output S of the adder 4,
A signal representing the output signal of the adder 61 in absolute value
FS′ is output. The state of this signal FS′ can be changed.
Regarding channel channels ch1 to ch4, as shown in Fig. 9.
FS′, and the timing of the input musical tone signal FS
24 time slots behind. this signal
FS' is one channel like the signal FS shown in Figure 6b.
Serial with 24 bits (time slots) per file
data, least significant bit (LSB) first.
ing. The multiplier 64 uses the 24 bits output from the adder 4.
The serial data FS′ of each shift register SR
8-bit filter output from SR1 to SR8
Multiply by a factor. 24-bit and 8-bit serials
Multiplication typically requires 32 time slots of computation time.
Importantly, the time and minutes of each series are calculated every 24 time slots.
Because a division operation must be performed, the lower 8 bits are
The multiplication result is rounded down and the upper part including the sign bit is rounded down.
The product of 24 bits is calculated. multiplier
64 is parallel from shift registers SR1 to SR7
Each bit of the absolute value part of the filter coefficient output as
The seven multiplier parts M1 to M7 corresponding to
Contains. These parts M1 to M7 are arranged vertically in order.
connected. Regarding parts M4, M5, M6
The detailed drawings have been omitted, but they are the same as parts M2 and M3.
It is one composition. Each part M1 to M7 is an address for calculating partial products.
The terminal circuits 171, 172, 173,...174
and each AND circuit 171 to 174.
is output from each shift register SR1 to SR7.
Each bit k of the absolute value part of the filter coefficient₁,k₂…
k₇are input respectively. Also, the parts M1 to M6 are
Cascaded delay circuits 175, 176, 177
..., respectively, and the output signal FS' of adder 4 and
These delay circuits 175, 176, 177...
Each time slot is sequentially delayed and each delay output is
to the AND circuits 172, 173...174, respectively.
Apply. The AND circuit 171 of part M1 has a delay
A signal FS' which is not applied is applied. Part M2no
to M7 respectively connect adders 178, 179,...180.
contains, and is calculated by each AND circuit 171 to 174.
The calculated partial products are added by these adders 178 to 180.
to add. The signal FS' is transmitted to each delay circuit 175, 17.
6,177, so the individual time
The output of each AND circuit 171 to 174 for each slot
The force weights match, so the adder 178
To 180, it is possible to add partial products of the same weight.
I can do it. In adders 178 to 180, each bit
partial products of
The outputs of are applied to the A inputs, respectively. For B input,
The sum of integrals or partial products is AND circuit 181, 1
82, 183, and so on. and circuit
181 is the output of the AND circuit 171 and the inverter.
The output signal 1 of the data filter 170 is input. and
Adders 178, 179 are included in the circuits 182, 183...
The output S of... and the signal 1 are transferred to a delay circuit 184,
Signals delayed sequentially at 185, 186, . . . are added.
These AND circuits 181, 182, 183...
This is for cutting off lower partial products. Each country
Carry out of calculators 178, 179,...180
Output C₀₊₁is AND circuit 188, 189...190
input to the carry-in input Ci. and
Other inputs of the circuits 188, 189...190 include signals.
SH1 in order with delay circuits 184, 185, 186...
Next, a delayed signal is added. AND circuit 188,1
89...190 are carriers related to the same channel
while allowing the addition of output signals, the calculation time
to the most significant bit of another channel preceded by
The related carry-out signal is sent to the next channel.
to prevent it from being added to the least significant bit of
It is something. Delay circuit 19 provided between portions M5 and M6
1,192,193 in parts M1 to M5
AND circuits 181, 182, 183... and addition
to compensate for the operation delay of the devices 178, 179...
It is something. In these parts M1 to M5
Total calculation operation delay time (this is one time slot)
) is delayed by the delay circuit 192.
1 time slot in synchronization with the change in time slot
and the delay to match this.
Delay circuit 1 is installed in the path of circuits 175, 176, and 177.
91 and delay circuits 184, 185, 186
A delay circuit 193 is inserted in the path of... Ma
In addition, in order to accommodate this delay, a delay circuit array 142
and 143, extra delay circuits 145 and 146 are inserted.
is included. Thus, the signal FS′ and the absolute value part of the filter coefficient
Minute (bit k₁~k₇) is the serial data corresponding to the product of
The data is output from adder 180 of portion M7.
The output of this adder 180 is sent to an exclusive OR circuit 194.
It is added to the A input of adder 195 through the input signal. exclusive or
Circuit 194 and adder 195 connect signal FS' and filter
The product is calculated according to the multiplication result of the sign bits of the data coefficients.
This is for converting into two's complement format. centre
Data indicating the sign bit (SB) of the filter coefficient
k₈is exclusive OR circuit 19 from shift register SR8
6 is input. The sign bit of signal FS′ is
It is latched in the hold circuit 169. This latch time
The output signal of line 169 is transferred to the output of shift register SR8.
A latch circuit 197 is provided to synchronize the
The output of the latch circuit 169 is connected to the delay circuit array.
The output of the 8th stage delay circuit 198 of 143 is “1”
It will latch at the timing. This latch circuit
197 output to other input of exclusive OR circuit 196
Given. Latch timing of latch circuit 197
The shift timing of shift register SR8 is
files on the same channel because they are the same.
Sign bit data of data coefficient and sign of signal FS′
The bit data is synchronized with the exclusive OR circuit 196.
It will be entered. The exclusive OR circuit 196
“1” indicates a negative value when the person’s sign bit does not match.
Outputs “0” indicating positive when they match.
Strengthen. The output of this exclusive OR circuit 196 is “0”
In other words, when the sign of the product is positive, adder 1
The output of 80 is sent to exclusive OR circuit 194 and adder 19
5 as is and given to the AND circuit 199.
It will be done. When the output of exclusive OR circuit 196 is “1”
In other words, when the sine of the product is negative, the adder 180
The output is inverted by exclusive OR circuit 194 and added to adder 1
It is added to the A input of 95. Ci input of adder 195
is after when the output of the exclusive OR circuit 196 is “1”.
As mentioned above, the AND operation is performed at the timing of the least significant bit.
“1” is given from the circuit 200 via the OR circuit 201.
It's starting to become possible. Thus, for negative values
The product is converted to two's complement form. The product expressed in two's complement form is sent to the adder 195.
via the AND circuit 199 and the OR circuit 202
It is applied to the A input of adder 62. Furthermore, adder 1
95 and 62 carryout output C₀₊₁The carriage of
AND circuit 20 that controls the supply to the input input Ci
3 and 204 are the AND circuits 188, 189,
...It was provided for the same purpose as 190. OR circuit 20 inputting the output of adder 180
5. Consists of an AND circuit 206 and a delay circuit 207
The loop detects whether the product is all bits “0” or not.
It is for the purpose of Signal 1 7 times
The lot-delayed signal 8 is sent to the AND circuit 206.
is added, and the memory contents of this loop are
It is reset by No. 8. Adder 180
If the output of becomes “1” even once, this loop 2
“1” is stored in 05, 206, and 207. Canada
The output of the calculator 180 never became “1”.
When the product is all “0”, this rule
"1" is not stored in the ports 205 to 207, but "0"
It remains as it is. Delay circuit 207 and exclusive OR circuit
The output of 196 is input to the AND circuit 208.
Ru. If the product is not all “0”, exclusive OR circuit
The output of 196, that is, the product of sign bits is
It passes through an AND circuit 208. The product is all
If “0”, the AND circuit 208 is disabled;
regardless of the output of the exclusive OR circuit 196.
The output of the AND circuit 208 is “0” (that is, positive signal
). The output of the AND circuit 208 is
Addition via AND circuit 209 and OR circuit 202
It is applied to the A input of the calculator 62. AND circuit 20
9 is a signal obtained by inverting signal 8 by inverter 210.
Possible only at the timing of the sign bit depending on the issue.
It is becoming more and more popular. Therefore, the AND circuit
The output of 208 indicates the sign bit of the product.
Therefore, when the product is all “0”, the sine bit is strong.
It is legally defined as "0", that is, positive. In the multiplier 64, the 24-bit serial signal
FS′ and 3-bit coefficient k₁~k₈The serial multiplication with
Performed sequentially from the lowest digit during 32 time slots.
Ru. However, the first 8 ties out of 32 time slots
MSlot (when performing multiplication of lower digits)
performs high-order digit multiplication on the preceding channel.
This is also the time when you are getting used to the song.
The multiplication result of the channel is truncated and the leading channel is
Priority is given to the operation of the file. Thus, the tag of signal FS′
The signal is delayed by 8 time slots from the timing.
The multiplication results for 24 time slots regarding FS′ are available.
is output via the adder circuit 202 and input to the adder 62.
Force A is given. The input A of this adder 62 is
Judging from the timing of issue FS, it is exactly 32 times.
Lotto is late. Input B of adder 62 has a delay
Circuit 65 delays input signal FS by 32 time slots
A signal dFS is given. The output of the adder 62 connects the forward output terminal FS-OUT.
It is input to the next stage filter unit L2 via
Ru. In the next stage filter hotlet L2, the forward direction is
Input terminal (corresponding to FS-IN in Figure 14)
from the previous stage filter unit L1 via
musical tone signal and shift register (see Fig. 14)
SR1 to SR8)
Perform the same calculation as above based on the filter coefficient etc.
cormorant. However, each filter unit L1 to L12
Input terminal FS-IN and output terminal FS-OUT at
The time delay of the musical tone signal between the two is 32 time slots.
On the other hand, the timing signals LD and SH are
The time delay is 8 time slots, so other users
All units L2 to L12 are replaced with the above units.
If the configuration is exactly the same as L1, the multiplier (Fig.
(equivalent to 64)₁~k₈
and a shift occurs in the channel of the signal FS′.
Therefore, the multiplier of each unit L1 to L12 (the
(corresponding to 64 in Figure 14)
k₁~k₈In order to match the channel of signal FS′ with
As output Q of shift registers SR1 to SR8,
Each unit L1 to L12 has a stage to be taken out.
The differences shall be as follows: Sunawa
In unit L1, shift registers SR1 to
4th stage output Q4 as output Q of SR8
(See Figure 15), but the unit
In L2, the output Q1 of the first stage, unit L3
Then, the output Q2 of the second stage and the unit L4 are
Output Q3 of the third stage, fourth stage in unit L5
The stage output Q4, and so on, is the output Q.
The stage to be taken out is shifted sequentially. Figure 16 shows the zero filter shown in Figure 15.
is shown in more detail, and the multiplier in Fig. 5 is shown in more detail.
73, 74, 81, adder 75, 76, delay circuit
The circuits corresponding to 77, 79, and 80 are also shown in Figure 16.
The same symbols are attached. Serial filter coefficient data
data K according to timing signals KL, LD, and SH.
Convert each multiplication to parallel filter coefficient data
Coefficient distribution circuit for distributing to the components 73, 74, 81
Roads 212, 213, and 214 are omitted in FIG.
However, it is illustrated in FIG. Multipliers 73, 74, 81 and
Internal configuration of coefficient distribution circuits 212, 213, 214
are the same as those 64 and 139 shown in FIG.
can be used. i.e. multiplier
73, 74, 81 are each shown in FIG.
It can have the same configuration as the multiplier 64, and the coefficient
Each of the wiring circuits 212, 213, and 214 is a first
The coefficient distribution circuit 139 (delay circuit array 140,
142, 143, latch circuit 141 and coefficient storage
The same configuration as the part consisting of the device 144)
Can be done. In detail, the multiplication in the first stage
In the blocks of the circuit 73 and the coefficient distribution circuit 212,
Input points P1, P2, P3, P4, P5 and
Output points P6, P7, P8, P9, P10,
P11 is the point with the same symbol in Fig. 14.
This corresponds to the delay circuit 16 in FIG.
8 and the input shown on the input side of the latch circuit 169.
Indicated from point P1 to the output side of OR circuit 202.
output point P6 and signal 9 line.
Details of the multiplier 64 leading to the output point P7 shown.
The detailed circuit and the detailed circuit of the multiplier 73 in Fig. 16 are completely
are the same. In addition, the data and each signal in Figure 14
The input points indicated on the input lines of KL, LD, and SH
Output points indicated on the output line from points P2 to P5
of the coefficient distribution circuit 139 leading to points P8 to P11.
Detailed circuit and details of the coefficient distribution circuit 212 in FIG.
The circuit is exactly the same. Also, in Figure 14
Filter coefficient storage device 1 in coefficient distribution circuit 139
The output Q of each of the 44 shift registers SR1 to SR8 is
Just like the input to the multiplier 64, the
Also in Figure 16, from the coefficient distribution circuit 212 to the multiplier 73
A signal indicating a filter coefficient is input. second performance
Multiplier 74, coefficient distribution circuit 213 and
and a multiplier 81 in the third arithmetic stage, a coefficient distribution circuit
Similarly, the path 214 also connects each input/output point P1 to P1.
1 corresponds to the points with the same symbols in Figure 14.
Ru. In addition, in each coefficient distribution circuit 212, 213, 214
Outputs of shift registers SR1 to SR8 (Fig. 14)
The stage that extracts the force Q is the polar filter mentioned above.
The units are shifted sequentially in the same way as units L1 to L12.
do. In the last polar filter unit L12, the third
The stage output Q3 (Fig. 15) is taken out.
Therefore, the first calculation stage in the zero filter 43
(Distribution circuit 212) output Q4 of the fourth stage
(Fig. 15) and put it into the second calculation stage (distribution circuit).
In path 213), the output Q1 of the first stage is taken out.
However, in the third calculation stage (distribution circuit 214), the second stage
The stage output Q2 is taken out. In FIG. 16, the last unit of polar filter 42 is
Provided via lines 93 and 94 from unit L12.
The obtained serial filter coefficient data K and tie
The timing signals KL, LD, and SH are the coefficient distribution circuit of the first stage.
212. 1st stage coefficient distribution circuit 2
Data K, signals KL, LD, and SH via 12 are
It is applied to the second stage coefficient distribution circuit 213, and further 2
From the circuit 213 in the third stage to the circuit 214 in the third stage
It will be done. As mentioned above, data K and signals LD and SH are
8 ties for each stage of circuits 212, 213, and 214
Muslot is delayed and signal KL is not delayed.
Finally, the coefficient distribution circuit 212 of each stage,
Storage device 144 in 213, 214 (see Figure 14)
(see) the predetermined filter coefficients corresponding to the relevant operation stage.
(K in Figure 5₁₃,K₁₄,K₁₅) is each channel ch1
~Memorized for each ch4. By the way, the input to the first stage of the zero filter 43 is
The states of the timing signals LD and SH are shown in Figure 17.
Shown in the *LD and *SH columns. FS column in Figure 17
is from selector 87 (Fig. 8) in the same way as in Fig. 9.
Channel timing of output musical tone signal FS
It is shown. Signals LD and SH are polar filter 4
8 in each of the 12 units L1 to L12 of 2.
Since the time slot is delayed, the signal in Figure 9
LD, SH delayed by 96 time slots is zero
The signal is input to the first stage of the filter 43. Therefore,
The timing signal LD with a period of 120 time slots is
96 time slot delay as shown in *LD in Figure 17.
Although the state is extended, the period of 24 time slots is
The signal SH is shown in Fig. 9 as *SH in Fig. 17.
It is virtually the same as SH. In the KD column of Figure 17
is the latch circuit (first stage) of the coefficient distribution circuit 212 in the first stage.
(corresponding to 141 in Figure 14)
This shows the channels of filter coefficients.
However, as mentioned above, this is the same as KD in Figure 9.
Ru. Therefore, the buffer in the first stage coefficient distribution circuit 212
filter coefficient storage device (corresponding to 144 in Figure 14)
shift register SR1 of the least significant bit of
Outputs Q1 to Q4 of each stage (see Figure 15)
"212" in Figure 17 shows the channel status of
The SR1 column will look like this. This is shown in Figure 9.
I understand that the state is the same as in the "SR1 of L1" column.
will be done. In addition, as described later,
Musical tone signal input to input terminal ZSi of filter 43
*The FS channel status is extremely low in any case.
The channel of the serial musical tone signal FS input to the router 42
It is the same as the Jannel condition. Therefore, zero fill
The serial operation in the first stage multiplier 73 of the
The calculation timing is based on the first stage unit of the polar filter 42.
Serial operation timing of multiplier 64 of L1
is synchronized with. This means that polar filter 42 and
When switching the connection combination of the filter 43,
Freedom without having to consider calculation timing
This is advantageous because it allows switching to On the other hand, it is applied to the input terminal ZSi of the zero filter 43.
The musical tone signal *FS is input to the input B of the adder 75 and
Input to the delay circuit 78 and input point
The first stage multiplier 7 via P1 (see FIG. 14)
3 is input. This musical tone signal *corresponds to FS
The multiplication result is delayed by 32 time slots as described above.
output from output point P6 (see Figure 14).
It will be done. Serial output from output point P6
The musical tone signal is delayed by 64 time slots in the delay circuit 77.
After that, it is applied to input A of adder 75. child
The serial musical tone signal given to input A of
Serial musical tone signal given to B *FS timing
96 time slots (exactly 1 sample)
serial on the same channel.
The adder 75 adds bits of the same weight to the musical tone signal.
Can be added. Carry output C of adder 75₀₊₁is Anne
Carry input C via the code circuit 215_igiven to
Ru. The other input of the AND circuit 215 includes the multiplier 7
3 output point P7 (see Figure 14)
The signal 9 is processed by the delay circuit 216 for 64 times.
A lot-delayed signal is provided. As mentioned above,
This signal 9 is connected to the output point P6 (see Fig. 14).
Serial musical tone signal output from the OR circuit 202)
When the weight of the signal is the least significant bit, it becomes "0". slow
The delay circuit 216 is synchronized with the delay operation of the delay circuit 77.
This is a system that was provided for the purpose of
The difference caused by the addition of the most significant bit of the channel.
The layout signal is output to the lowest bit of the next channel.
Carry input C at the addition timing of_itype in
An AND circuit 215 is provided to prevent
It is being At the input point P1 of the second stage multiplier 74,
Serial musical tone signal *FS is 128 ties with delay circuit 78
A delayed message is being input. 1st
4. Coefficient distribution circuit 139 configured as shown in FIG.
When performing serial multiplication using the multiplier 64,
Synchronize the serial operation timing in the multiplier.
(serial musical tone signal to be multiplied and filter
Synchronize the channels of numbers and the weight of each bit.
As is clear from the above, the serial
The input timing of the sound signal is determined by the input timing of the multiplier in the previous stage.
Must be 32 swim slots behind timing
Must be. Therefore, the musical tone of the second stage multiplier 74
Signal input timing and that of the first stage multiplier 73
Compared to
One sampling period (96 tie
muslot) and 32 time slots (total 128 ties)
32 time slots).
The condition of a delay of 10 minutes is met. obey
Therefore, the second stage multiplier 74 also performs serial operation.
Timing can be synchronized. Output point P6 of the second stage multiplier 74 (first
(See Figure 4)
In other words, the multiplication result is processed in 32 time slots by the delay circuit 79.
is applied to input A of adder 76.
Ru. The input B of the adder 76 is the input of the adder 75 in the previous stage.
An output S is given. As before, multiplier 74
is output from output point P7 (see Figure 14).
The signal 9 is synchronized with the delay time of the delay circuit 79.
The signal is then delayed by 32 time slots in the delay circuit 217.
After that, the signal is input to the AND circuit 218. and circuit
The other input of 218 is the carry output of adder 76.
C₀₊₁is given and its output is the carry input C_igive to
available. This delay circuit 217 and the AND circuit 21
8 performs the same function as the circuits 215 and 216 described above.
vinegar. As mentioned above, the delay circuit 79 is connected to the adder 76.
The timing of the signal input to input A is the input signal
*2 sampling cycles longer than FS timing
(192 timeslots) Also for making it late
It is. In other words, the delay circuit 78 takes 128 times.
slot, 32 time slots inside the multiplier 74
The delay circuit 79 has a delay of 32 time slots.
By setting each, a total of 192 time slots
delay is set. The output signal of the adder 76 is sent to the delay circuit 80 for 64 times.
After being delayed by muslot, the input point of multiplier 81 is
is input to component P1. Then, the output of the multiplier 81
From force point P6, the tie of input point P1
Timing 32 time slots later than timing
A serial musical tone signal is output, and this is the zero-fi
Output musical tone signal Z of router 43₀as output terminal ZS₀to
Given. The delay circuit 80 has the same reason as above.
As a result, the musical tone signal input tie of the second stage multiplier 74 is
There are 32 terminals between the multiplier 81 and the multiplier 81 in the third stage.
Provided to set the imslot time delay.
It is something that was given. That is, inside the multiplier 74
32 time slots, 32 time slots with delay circuit 79
The delay circuit 80 delays the time of 64 time slots.
are set respectively, resulting in a total of 128 time slots of delay.
is set between the two. 128 time slots
is 1 sampling period (96 time slots) and 32
Since it is a time slot, the second stage multiplier 74
The musical tone signal input timing and the third stage multiplier 81
There are essentially 32 time slots between that of
There will be a delay. Zero filter 43 input signal *FS and output signal
Z₀Comparing the timing with the delay circuit 78,
Multiplier 74, delay circuits 79, 80, multiplier 81
Total delay of 288 time slots depending on route
This is exactly 3 sampling periods.
Therefore, input signal *FS and output signal Z₀of Thailand
(each bit of channel and serial data)
(timing of weights) are completely synchronized.
Therefore the output signal Z₀is shown in Figure 9 or Figure 17.
Serial musical tone perfectly synchronized with FS timing
It's a signal. Note that the final stage unit L12 of the polar filter 42
Forward output terminal FS₀Serial musical tone output from
The signal timing is also completely synchronized with the FS in Figure 9.
ing. In other words, each of the 12-stage units L1 to L12
The musical tone signal is delayed by 32 time slots in each case.
Therefore, the total delay time is 384 time slots.
This is exactly 4 sampling periods, so
Forward input terminal FS of polar filter 42_iand forward-looking
The timing of the serial musical tone signals of the output terminal FSo is the same.
It will take a while. As shown in Figure 8, the pole
The signal at the output terminal FSo of the router 42 or the input control circuit
Serial musical tone signal S output from path 37_ione side
is selected by the selector 89 and the zero filter 43
Given to input terminal ZSi. Therefore, the input terminal
Serial input to zero filter 43 via ZSi
The timing of the musical sound signal *FS is as described above.
In any case, it is synchronized with the FS in Figure 9.
Therefore, the input terminal I in FIG.₁~I₃input from
Serial musical tone signal S₁~S₃, from the input control circuit 37
Output serial musical tone signal Si, selector 87?
Serial musical tone signal input to polar filter 42
FS, output from the output terminal FSo of the polar filter 42.
Serial musical tone signal input to zero filter 43
Serial musical tone signal input to terminal ZSi *FS, Z
The signal output from the output terminal ZSo of the filter 43
Real musical tone signal Z₀timing (channel and
The timing of the weight of each bit of serial data is
All are synchronized, as shown in Figure 9 or Figure 17.
It looks like the FS column. Note that the filter in the digital filter main circuit 38
The model of ita is not limited to the one mentioned above.
Good too. As described above, according to the present invention, a simple configuration is possible.
Therefore, digital filters can be used to create multiple tones.
It can be used for time sharing as well as for each channel.
You can easily assign tones to channels.
It has the effect of being able to do.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the overall configuration of an example of an electronic musical instrument implementing a digital filter device according to the present invention, and FIG. 2 is a block diagram of the musical tone signal generation section and the musical tone signal distribution, accumulation, and serial conversion control circuit in FIG. FIG. 3 is a block diagram showing an example of the digital filter section in FIG. 1. FIG. 4 is a block diagram showing an example of the polar filter shown in FIG. 5 is a block diagram showing an example of the zero filter in FIG. 3, FIG. 6 is a timing chart showing an example of the serialization format of musical tone signals, and FIG. 7 is a timing chart showing an example of the serialization format of filter coefficients. 8 is a block diagram showing a detailed example of a digital filter circuit device that can be used as the digital filter section of FIGS. 1 and 3;
FIG. 9 is a timing chart showing an example of the serial musical tone signal, filter coefficients, and timing signals input to the polar filter of FIG. 8, as well as channel timing states of the main signals in the first stage of the polar filter; The figure is a block diagram showing an example of the timbre selection device in Fig. 1, Fig. 11 is a timing chart showing an example of the serialization format of the timbre parameters output from Fig. 10, and Fig. 12 is the filter coefficient in Fig. 1. A block diagram showing an example of an external storage device, FIG. 13 is a diagram showing an example of address signal generation in the address signal generation circuit of FIG. 12, and FIG. 14 is a diagram showing an example of address signal generation in the address signal generation circuit of FIG. 15 is a circuit diagram showing a detailed example of the filter unit; FIG. 15 is a circuit diagram showing an example of the internal configuration of the shift register for storing filter coefficients in FIG. 14; FIG. 16 is a circuit diagram showing a detailed example of the zero filter in FIG. 5. , Figure 17 is the 16th
2 is a timing chart illustrating the states of various signals in the first calculation stage in the figure. 11... musical tone signal generation section, 12... timbre selection device,
13...Music signal distribution, accumulation and serial conversion control circuit, 14...Digital filter section, 20...
Filter coefficient external storage device, 21... Filter coefficient changeover switch, 37... Filter input control circuit, 3
8... Digital filter main circuit, 39... Output control circuit, 40... Timing signal generation circuit, 41... Filter coefficient supply circuit, 42... Pole filter, 43...
Zero filter, 97...Filter coefficient ROM, 10
0...RAM for tone code, 101, 102
...Selector, 98, 99...Shift register and latch circuit for serial-parallel conversion, TP1 to TP4
...Tone parameter, TC...Tone code, CH...Channel code.

Claims (1)

[Scope of Claims] 1. A digital filter that receives digital musical tone signals of multiple channels and performs filter calculation operations in a time-sharing manner, and a plurality of sets of filter coefficients to be used in calculations in this digital filter that are stored in advance. A filter coefficient storage means, a timbre selection means for selecting a desired timbre, a timbre code for identifying each timbre selectable by the timbre selection means, and a channel indicating a channel to which the timbre should be assigned. timbre parameter supplying means for reading and outputting the timbre parameters corresponding to the timbre selected by the timbre selection means from the memory; timbre storage means for storing timbre codes included in the timbre parameters stored in addresses corresponding to the channel codes; and timbre storage means for sequentially reading out the timbre codes stored in each address of the timbre storage means in accordance with the time-sharing timing of each channel. readout control means, the readout control means outputs a corresponding filter coefficient set from the coefficient storage means in a time-divisional manner according to the tone color code of each channel read out in a time-divisional manner, A digital filter device for an electronic musical instrument. 2. The timbre parameter supply means includes means for outputting the timbre parameters in a temporally serial data format, and the timbre storage means converts the serial timbre parameters into a parallel data format and then stores the timbre parameters in the timbre code. A digital filter device for an electronic musical instrument according to claim 1, wherein the digital filter device stores information.