JPH0746960Y2 - Music synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a musical tone synthesizer, and more particularly to a technique for exponentially converting a linear envelope or a linear key code.

[Background] In fields such as electronic musical instruments where real-time demands are demanding, memories (tables) are often used for function conversion of data. In order to perform the function conversion with one memory, it is necessary to prepare a memory having the same number of words for all combinations of input data, and the capacity is sacrificed. For example, if the input data is 13 bits, then 8192 data must be stored in the memory.

For this reason, techniques have been developed for combining an interpolation circuit with one or more memories. For example, a coarse data memory that stores the function conversion value of the integer part of the input data,
A difference memory that stores the difference between the function conversion values of adjacent integer parts of the input data is prepared, and the function conversion value of the integer part uses that from the rough data memory, and the function conversion value of the decimal part is the above. The difference value from the difference memory is multiplied by the interpolation coefficient determined by the decimal part of the input data, and the result is added to the means of the coarse data memory. Mathematically, A = A (N) + C * (A (N + 1) -A (N)). Here, A (N) is the output of the coarse data memory, A (N + 1) -A (N) is the output of the difference memory, and C is the interpolation coefficient determined by the fractional part of the input data.

The interpolation technique as described above is advantageous in that the memory capacity can be saved. For example, in the configuration in which the upper 7 bits of the 13-bit input data are input to the coarse data memory and the difference memory, the number of words required for each memory is 2 ⁷ = 128, and a total of 256 is sufficient. However, the decimal part calculation C × (A (N + 1) −A (N)) is an approximate calculation called linear interpolation. Therefore, when high numerical accuracy is required, most of the input data must be converted by the coarse data memory or the like, and the advantage of saving the memory capacity is lost. That is, the merit of reducing the memory capacity by the interpolation technique is based on a compromise with the required numerical accuracy.

By the way, in many musical tone synthesizers, musical tone control signals such as envelopes and key codes are not generated linearly in the exponential data format, but are generated once in the linear data format and then subjected to exponential conversion to obtain a waveform. Input to the generation circuit.

Here, there is a demand for a musical sound synthesizer capable of realizing this kind of exponential conversion with an optimum configuration.

[Object of the Invention] Therefore, an object of the present invention is to provide a musical sound synthesizer which has a small storage capacity and has an exponential conversion function with high numerical accuracy.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention has a musical tone control signal generating circuit means for generating a musical tone control signal of straight line data and a waveform generating circuit for generating a musical tone waveform using the musical tone control signal of exponential data as a parameter. Exponential conversion circuit means for interfacing with the means, exponential coarse data storage means for outputting exponentially converted value of upper bit data of linear data, and exponential fine data storage means for outputting exponentially converted value of lower bit data of linear data. , And arithmetic circuit means for multiplying the outputs from both storage means.

[Operation and Development of Device] Now, the upper bit data of the straight line data is represented by X, the lower bit data is represented by Δx, and the output of the exponent rough data storage means is represented.
A ^x , the output of the exponential fine data storage means is represented by A ^Δx ,
The calculation result of the calculation circuit means is A ^X · A ^Δx .

If exponential conversion is performed in one memory, this memory outputs A ^{(X + Δx)} for straight line data (X + Δx). This is an accurate exponential conversion value for linear data.

Here, when the operation result according to the present invention and the operation result by this single memory structure are compared, it is understood that both are equal because A ^X · A ^Δx = A ^{(X + Δx)} .

That is, the present invention can perform exponential conversion with high numerical accuracy.

On the other hand, in terms of capacity, if the upper bit data X is N bits and the lower bit data ΔX is M bits, the number of words of 2 ^{(N + M)} is required in the case of a single memory, whereas the present invention In case of, the number of (2 ^N +2 ^M ) words is sufficient. For example, assuming N = 7 and M = 6, a single memory type requires 8192 data, whereas 192 data is sufficient in the present invention. That is, the present invention can significantly reduce the storage capacity.

In the above description, the format of exponential conversion is represented by A ^x and the coefficient is assumed to be 1. However, conversion to a · A ^x having a coefficient a other than 1 may be used.

Further, in the above description, the straight line data is divided into two parts, the upper bit data and the lower bit data, and the respective converted values are provided in the exponent rough data storage means and the exponential fine data storage means. It may be divided into three or more parts, each exponential conversion value may be stored in each conversion memory, and each memory output may be multiplied.

Since the present invention guarantees exponential conversion with high numerical accuracy in principle, approximate multiplication, for example, multiplication by shift circuit means, is sufficient for multiplication at the output of the arithmetic circuit.

The data to be subjected to exponential conversion is typically an envelope or a key code.

Further, in the embodiments described later, the individual exponential conversion circuits are
Rather than performing exponential conversion between the linear envelope and the key code, one exponential conversion circuit uses this
Performing exponential conversion of data of type.

Further, in the embodiment described later, in consideration of the exponential conversion value of the lower bit data of the linear data being close to 1, the exponential fine data memory has numerical data excluding 1 (data of the effective decimal part). By storing only the word length in the exponential fine data memory is saved.

[Embodiment] FIG. 1 is a functional diagram of an electronic musical instrument according to an embodiment of the present invention. The CPU3 is a general-purpose microcomputer, which scans the keyboard 1 and the switch 2 to detect key depression and tone color selection according to the control program, and generates tone color data and sound control data using the ROM4, RAM5, etc. arranged on the bus. And control the pronunciation of the sound source LSI. The tone generator LSI 6, which will be described later in detail, uses the external RAM 7 as a calculation buffer for tone generation to generate a tone and transfers it to a DAC (digital-analog converter) 8. The tone signal is converted into an analog signal by the DAC 8, amplified by the amplifier 9, and emitted by the speaker 10.

FIG. 2 is a block diagram for explaining the operation of the tone generator LSI 6 to which the present invention is applied. The tone generator LSI 6 uses the RAM 7 as a tone color data memory or a calculation progress data memory in order to generate a key code including an amplitude envelope and a pitch variation. In addition, RAM7, as shown in FIG.
It is occupied by the interface / control unit 11 (interface occupancy time) and the envelope / key code generation circuit (arithmetic circuit occupancy time) every 0 nsec, and handles access from the CPU for data writing and envelope arithmetic operations.

First, the interface / control unit 11 will be described. CPU3
The tone color data or the tone generation control data is transferred from the sound source LSI 6 to the sound source LSI 6, but the sound source LSI 6 takes in the data on the data buses DB0 to DB7 at the rising edge of ▲ ▼ when ▲ ▼ is LOW. At that time, if ▲ ▼ / D is LOW, data bus D
B0 ~ DB7 data instructions, ▲ ▼ / D is HIGH
If it is H, the data corresponding to the instruction is taken in (see Fig. 4). The instruction indicates the type of data that is subsequently transferred. The interface / control unit 11 receives the instruction and data from the CPU 3, and receives the RAM 7 corresponding to the instruction.
The addresses AA0 to A11 and the write signal ▲ ▼ are generated, and the data transferred to the external RAM 7 via the external RAM interface 16 is stored. However, if the data transferred from CPU3 is special, it is stored in the internal memory. For example, when the transferred data is an operation code (control data for waveform generation), writing to the external RAM 7 is prohibited, and a write signal WO to the OC register 14 is generated, so that the data is written to the OC register. Be done. Further, the interface / control unit 11 generates the basic timing signal as shown in FIG. 6, and the 2 to 6 bit memory of the counter A outputs it as C1 to C5.

The envelope / key code generation circuit 12 uses addresses BA0 to 11 to access the data written in the external RAM 7.
And write signal for envelope calculation progress data, etc.
Generate ▼. As a result, based on the tone color data (envelope rate / level, etc.) of the external RAM 7, according to the sound generation control data (key code, modulation, etc.), a key code containing the amplitude envelope or pitch variation of each channel, module (synthesized key below). Code) and convert exponentials via buses L0-12
The data is transferred to the phase angle generation circuit 13 in a time division manner.

The exponential conversion / phase angle generation circuit 13 exponentially converts the amplitude envelope and the composite key code from the envelope / key code generation circuit 12 by sharing one exponential converter in a time division manner. The exponentially converted amplitude envelope (exponential envelope) and the exponentially converted composite key code (frequency information) are temporarily stored in the envelope register and the frequency information register, respectively. These are used as interface buffers for accessing the external RAM 7 to generate an amplitude envelope and a synthetic key code and performing exponential conversion at low speed, and for performing subsequent arithmetic processing at high speed. Fig. 5 shows the time relationship between the two calculation processes. The low-speed calculation cycle is the high-speed calculation cycle.
Is doubled. This is because the change rate of the output waveform must be twice the audible frequency or more, so the waveform calculation is performed at high speed (about 40 KHz in this embodiment), and the other calculations are performed at low speed according to the access to the external RAM 7. Because it is.

The exponent envelope stored in the envelope register is read corresponding to the high speed operation and transferred to the waveform generation circuit 15 as envelopes E0 to E11. The frequency information stored in the frequency information register is read and accumulated in correspondence with the high-speed operation, and the waveform information is generated as the phase angle data P0 to 11 in the waveform generation circuit.
Transferred to 15.

The waveform generating circuit 15 is based on the operation codes OC0 to 7 read from the OC register 14, and in accordance with the envelopes E0 to 11 and the phase angle data P0 to 11 transferred from the exponential conversion / phase angle generating circuit 13, the tone waveforms O0 to 15 are generated. Is generated and output to DAC8.

FIG. 7 is a detailed block diagram of the envelope / key code generation circuit 12. The calculation address generation circuit 16, the write prohibition circuit 17, the counter B18, the clock generation circuit 19, the calculation timing signal generation circuit 20, and the calculation control signal generation. A circuit 21 and an arithmetic circuit 22 are provided. The counter B18 is composed of counters 1, 2, and 3 (not shown) that operate as shown in FIG. The arithmetic circuit 22 is operated by the circuit 16, the clock generation circuit 19, the arithmetic control signal generation circuit 21 and the like as shown in the operation flow (FIG. 9).
Here, S, A, A ^M , A ^L , B, B ^M , B ^L and M are respectively
Arithmetic circuit 22 S register, A register, A register upper, A register lower, B register, B register lower, M
It means a register (not shown). In the operation flow, EF _ij ; envelope flag i = 0 to 8 (module, pitch), j = 0 to 7 (channel) ER _ij (s); envelope rate i = 0 to 8 (〃), j = 0 to 7 (〃), s = 0 to 7 (envelope step) ERC _j ; envelope rate change j = 0 to 7 (〃) ▲ E ^M _ij ▼; envelope upper level i to 8 (〃), j = 0 to
7 (〃) ▲ Ei ^L _ij ▼; Lower envelope i = 0 to 8 (〃), j = 0 to 7 (〃), EL _ij (s); Envelope level i = 0 to 8 (〃), j = 0 ~ 7 (〃), s = 0 to 7 (〃) ELC _ij ; envelope level change i = 0 to 8 (〃), j = 0 to 7 (〃), ▲ AMD ^M _j ▼; upper amplitude modulation j = 0 ~ 7
(〃) ▲ AMD ^L _j ▼; 〃 Lower j = 0 to 7
(〃) ▲ PMD ^M _j ▼; Higher pitch modulation j = 0 to 7
(〃) ▲ PMD ^L _j ▼; 〃 Lower j = 0 to 7
(〃) MS _ij ; Modulation sensitivity i = 0 to 7 (module), j = 0 to 7 (〃) ▲ KC ^M _j ▼; Key code higher j = 0 to 7 (〃) ▲ KC ^L _j ▼; 〃 Lower j = 0 to 7 (〃) ▲ PE ^M _j ▼; pitch envelope upper j = 0 to 7 (〃) ▲ PE ^L _j ▼; 〃 lower j = 0 to 7 (〃) ▲ FR ^M _ij ▼; frequency ratio upper i = 0 to 7 (〃), j = 0
~ 7 (〃) ▲ FR ^L _ij ▼; 〃 Lower i = 0 to 7 (〃), j = 0
-7 (〃) MR _j ; Modulation rate j = 0 to 7 (〃) ML _j ; Modulation level j = 0 to 7 (〃). In the flow of FIG. 9, the numbers on the left side mean timing, and 0 to 11 are counters 1.
Value itself, 12 ▲ ▼ to 19 ▲ ▼ are the values of counter 1 12 to 1 when the value of counter 3 is other than 8 (pitch calculation)
9 and 12P to 19P correspond to the values 12 to 19 of the counter 1 when the value of the counter 3 is 8 (pitch calculation).

Thereby, the following arithmetic functions are executed.

Change the envelope rate (envelope slope data) by changing the data envelope rate corresponding to the key range or key touch.

Change the envelope level (target data of each step of the envelope) by changing the data envelope level corresponding to the key range or key touch.

Generate an envelope according to the changed envelope rate and envelope level.

Amplitude modulation data corresponding to aftertouch, LFO, etc. is interpolated and calculated as the amplitude envelope to generate the final amplitude envelope wave.

Calculates pitch modulation data corresponding to vendors, LFOs, etc. with the pitch envelope.

The key code and the pitch envelope with modulation are calculated, and the frequency ratio representing the frequency ratio of each module is calculated to generate the final synthesized key code.

As shown in FIG. 10, the arithmetic timing symbol generation circuit 20 is provided for the arithmetic timing signal and the exponential conversion control circuit 23 according to the values BC0 to 4 and 11 of the counter B18 and the flag signal F'from the arithmetic circuit 22. Timing signals 0, 5, 6, 8, 15,
Generates 18.

FIG. 11 is a detailed circuit of the exponential conversion control circuit 23. The exponential conversion control circuit 23 is a circuit for generating signals CN, FN, MST, WEE, WEF, etc. as shown in the time chart of FIG. 14 according to the output of the lower 5 bits (counter 1) of the counter B18.
However, the signals WEE and WEF are generated only when the value of FF51 that takes in the values of the upper 7 bits (counters 2 and 3) of the counter B18 is 0 by the clock CKI generated when the value of the counter 1 is 19. This is the envelope / key code generation circuit 12
It means that only the amplitude envelope generated by the calculation other than the pitch and the exponentially converted synthetic key code are written in the envelope register and the frequency information register. The exponential conversion control circuit 23 further includes the addresses of the envelope register and the frequency information register.
Generates DA0-DA5. Address DA0 is the value of FF45 fetched by clock CKI. Further, the addresses DA1 to DA5 are write addresses when the signal T2 is 0 by the clock inverters 63 to 72, and the values of FF46 to 50 that fetch the value of the upper 7 bits (counters 2 and 3) of the counter B18 with the clock CKI, T2
When 1 is 1, the read address is selected from the values C1 to 5 of the 2 to 6 bit memory of the counter A shown in FIG. That is, for writing, the values of the channels and modules of the envelope / key code generation circuit 12 are addresses, and for reading, the values C1 to C5 of the counter A of the interface / control unit 11 are addresses.

FIG. 12 is a block diagram of the exponential conversion / phase angle generation circuit 13. The envelope and key code generated by the envelope / key code generation circuit 12 are taken into the FF 73 at the clock CKE. The output of the FF 73 is input to the exponential conversion circuit 74, subjected to exponential conversion, and then written to the envelope register 75 or the frequency information register 77. In the envelope register 75, the written envelope after exponential conversion is read appropriately,
It outputs as E'0-11 to the waveform generation circuit 15 via FF76. In the frequency information register 77, the written key code after exponential conversion, that is, the frequency information is read out as appropriate, and FF78
Is input to an accumulator composed of an adder 79 and a shift register 80 to accumulate. Phase angles P0 to 11 generated by accumulation
Is output to the waveform generation circuit 15.

FIG. 13 is a block diagram of the exponential conversion circuit 74 which is a feature of the present invention. Since the exponential conversion circuit 74 performs exponential conversion of the key code as well as exponential conversion of the envelope, the slope and range of the exponential conversion match the exponential conversion (frequency information) of the key code. Since the frequency information R is proportional to the tone frequency f, R = Af, and the tone frequency f becomes f = f ₀ ^{.2Z / 12} when the lowest tone frequency is f ₀ . However, Z is a key code having a resolution of one semitone or less.
Therefore, ^{_{R = Af 0 · 2 Z /}} 12. When the key code Z is represented by 7 bits for the semitone or more and 6 bits for the semitone or less, and Z = X + ΔX / 64 (X = 0 to 127, ΔX = 0 to 63) is set, R = Af _0. 2 ^{X / 12} · 2 ^{Δx / 768} (1) Therefore, if the rough data R _c is R _c = Af ₀ · 2 ^{X / 12} and the fine data R _f is R _f = 2 ^{Δx / 768} , the target exponential conversion data can be obtained by the multiplication of equation (1). Is obtained. Here, the fine data is shown in Table 1 in binary.

As can be seen from Table 1, the upper 5 bits are all 10,000. Therefore, in this embodiment, the exponent coarse data ROM 81 of FIG. 13 stores the value of R _c , but the exponential fine data ROM 83 does not have 12 bits of R _f but the sixth bit to the sixth bit. It saves word length by storing 12 bits. That is, the value of the exponential fine data ROM 83 is set to E _f
Then, R _f = 1 + 1/2 ⁵ · E _f . here, Is.

The purpose of exponential conversion is to multiply the output E _c (= R _c ) of the exponential fine data ROM 81 by R _f . That is, the target value E is E = E _c · R _f . This is E = E _c (1 + 1/2 ⁵ · E _f ) Therefore, E = E _c · (1 + 1/2 ⁵ · E _f6 + 1/2 ⁶ · E _f5 + _··· + 1/2 ¹¹ · E
_f6 ). As one calculation method, first, the output E _c of the exponential rough data ROM 81 is read and E _c is set to 1 by bit shift.
/ 2 ⁵ was intended to 1/2 ⁵ · E _c, gated by the most significant bit E _f6 exponent fine data ROM 83, the output ^{_{1/2 5 · E c · E f6}} , accumulated value (here E _c ), and then similarly, adding the elements after 1/2 ⁶ · E _c · E _f5 to the accumulated value gives the target exponential conversion value. This is the exponential conversion circuit in Figure 13.
This is the basic operation of 74. The details will be described below.

First, the shift register 82 is a parallel-in parallel-out shift register, which inputs data when the signal CN is "1", and otherwise shifts to the left every clock CK2 and outputs it. The shift register 84 is a parallel-in-serial-out shift register, which inputs data when the signal FN is "1", and otherwise shifts to the right every clock CK2 and outputs it. First
The exponential conversion circuit of FIG. 13 will be described with reference to the time chart of FIG. "Counter 1" at the top of the time chart is the calculation timing of the envelope / key code generation circuit 12,
Calculation is performed at timings 0 to 19 for each channel and each module, and the exponential conversion / phase angle generation circuit 13 fetches the envelope at timing 14 by the clock CKE and the key code at timing 0 of the computation time of the next channel module. First, the envelope interpolation will be described. The CN of the shift register 82 becomes "1" in the first half of the timing 18, the output of the exponent rough data ROM 81 is taken in, and the shift is started.
That is, the outputs E _c '0 to 20 are 0 shift in the latter half of the timing 18, 1 shift in the first half of the timing 18, etc., as shown in the item of "interpolation calculation" of the time chart. Shift register 84
Indicates that FM becomes "1" in the latter half of timing 0 and the exponential fine data
Capture the output of ROM83 and start shifting. That is,
As shown in "FN" of the time chart, E _f6 in the first half of timing 1, E _f5 in the second half, and so on. Gate circuit 87
Outputs 0 when the control input C is 0 and outputs input data when the control input C is 1, and when ▲ ▼ is 0
Since the output of 86 becomes 1, the E input of E _c ′ 0
~ 20 is entered. On the other hand, the output of the gate circuit 90 is ▲
When ▼ is 0, all are 0, so 0 is input to the A input of the adder 88, and E _c ′ 0 to 20 are set in the FF 89.
In the shift register 84, 7-bit data is set when FN is 1, and is sequentially output from the upper side. When the output of 7 bits of data is completed, 0 is continuously output. Therefore, the gate circuit 87 always outputs 0.
Is being output. Therefore, in the latter half of timing 18, FF89
E _c ′ 0 to 20 taken in are continuously held. The gate circuit 87 is controlled by the outputs E _f6 , E _f5 , ..., E _{f0 of the} shift register 84 from the first half of the timing 1 to the first half of the timing 4, so the calculation is as follows.

From the second half of the timing 4 to the first half of the timing 6, the output of the shift register 84 becomes 0, so the output of the gate circuit 87 becomes 0, and the calculation result up to the first half of the timing 4 is held. Therefore, the output of FF89 becomes the above calculation result from the latter half of timing 4 to the latter half of timing 6, that is, the calculation result of equation (1) by the multiplier of Table 1. Since the key code is interpolated in the same manner, the outputs Ex0 to 20 of the FF89 become exponential envelopes from the latter half of timing 4 to the latter half of timing 6, and frequency information from the latter half of 12 to the latter half of 18.

FIG. 15 is a detailed diagram of the envelope register 75. As described above, the inputs Ex9 to 20 are exponential envelopes at the timings 5 to 6, and the address DA0 is the LSB and D of the channel data of the exponential envelope when T2 is 0 from FIG.
Since A1 to A5 are the inversions of the upper 2 bits of the channel data and the inversion of the module data, they are written to ENVERAM95 when the channel data is even in the first half of timing 5, and to ENVORAM96 when it is odd. When T2 is 1,
Since the addresses DA1 to DA5 are the inversions of the basic timings C1 to C5 from the interface / control unit 11, the output of ENDERAM95 becomes E0 to 11 when T2 = 1 and the output of ENVORAM96 becomes E0 to 11 when T2 = 0. .

The frequency information register of FIG. 16 is written in the first half of timing 15 similarly to the envelope register, and is normally read out in the same manner as above.

[Effect of the Invention] As described above, in the present invention, the musical tone control signal expressed by the straight line data from the musical tone control signal generating circuit means is
In order to convert the exponent data suitable for the waveform generation circuit means, the exponent coarse data storage means for outputting the exponent conversion value of the upper bit data of the straight line data and the exponential fine data for outputting the exponent conversion value of the lower bit data of the straight line data. The data storage means and the arithmetic circuit means for multiplying the outputs of both storage means are used. Therefore, it is possible to perform exponential conversion with high numerical accuracy even with a small storage capacity.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a block diagram of a tone generator LSI, and FIG. 3 is an external RAM by an interface / control unit and an envelope / key code generation circuit of the tone generator LSI. A time chart showing allocation of occupancy, a time chart of data and a write control signal sent from the CPU to the interface / control unit of the sound source LSI in FIG. 4,
FIG. 5 is a time chart showing a low-speed operation cycle for generating a tone control signal and a high-speed operation cycle for generating a waveform. FIG. 6 is a time chart of a timing signal generating circuit.
The figure shows the block diagram of the envelope / key code generation circuit.
FIG. 8 is a time chart of the counter B, FIG. 9 is a flow chart of the envelope / key code generation circuit, FIG. 10 is a detailed view of the arithmetic timing signal generation circuit, and FIG. 11 is a detailed view of the exponential conversion control circuit. 12 is a block diagram of the exponential conversion / phase angle generation circuit, and FIG. 13 is a detailed diagram of the exponential conversion circuit.
FIG. 14 is a time chart of the exponential conversion circuit, FIG. 15 is a detailed view of the envelope register, and FIG. 16 is a detailed view of the frequency information register. 12 …… Envelope / key code generation circuit, 15 …… Waveform generation circuit, 74 …… Exponential conversion circuit, 81 …… Rough exponential data RO
M, 82, 84 …… Shift register, 83 …… Exponential data RO
M, 87, 90 ... Gate circuit, 88 ... Adder, 89 ... Flip-flop.

Claims (5)

[Scope of utility model registration request] 1. A tone control signal generating circuit means (12) for generating a tone control signal expressed by straight line data, and a waveform generation circuit means (12) for generating a tone waveform based on the tone control signal expressed by index data. 15) and an exponential conversion circuit means (74) for converting the straight line data from the musical tone control signal generation circuit means into exponential data used by the waveform generation circuit, wherein the exponential conversion circuit means comprises: An exponent coarse data storage means (81) which is addressed by the upper bit data of the straight line data and outputs an exponential conversion value of the upper bit data, and an exponent of the lower bit data which is addressed by the lower bit data of the straight line data. Exponential fine data storage means (83) for outputting the converted value, output of the exponential coarse data storage means and output of the exponential fine data storage means Musical tone synthesizing apparatus characterized by having a processing circuit means (82,84～90) for calculating the exponential conversion value of the linear data by multiplying the. 2. A musical tone synthesizing apparatus according to claim 1, wherein the straight line data is a linear envelope. 3. A musical tone synthesizing apparatus according to claim 1, wherein the straight line data is a linear key code. 4. A tone synthesizer according to claim 1 of the utility model registration, wherein said arithmetic circuit means includes shift circuit means (82, 84) for executing multiplication. . 5. The tone synthesis apparatus according to claim 1, wherein the exponential conversion circuit means executes exponential conversion of a linear envelope and exponential conversion of a linear key code in a time division manner. Sound synthesizer