JPS5838998A - Waveform signal synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention combines a waveform signal representing a reference waveform such as a sine wave stored in advance in a memory, and an amplitude multiplier signal representing an envelope of a musical sound wave shape stored in advance in another memory. The present invention relates to a waveform signal synthesizer that sequentially reads out and performs multiplication to generate a desired synthesized waveform signal, typically a musical tone signal, and particularly relates to an improvement for speeding up 1 multiplication processing. .

In the conventional Jinnotane device, a reference waveform such as a sine wave is sampled in a large number of time slots, and a digital code representing the amplitude value is stored in a memory as a waveform signal. The envelope of the waveform is sampled in a large number of time slots, the digital code representing the amplitude value is stored in another memory as an amplitude multiplier signal, both signals are sequentially read out and multiplied, and the multiplication result is digitally stored. Often used is one that converts the signal into an analog signal using an analog converter to generate a composite waveform signal having a desired frequency plate and envelope.

With the above-mentioned conventional devices, if you try to improve the resolution and improve the accuracy of waveform signal synthesis processing by representing the waveform signal and amplitude multiplier signal with multiple digits, a large amount of calculation processing is required for multi-digit multiplication processing. Since this method requires time, there is a problem in that the multiplication speed is insufficient and it is not possible to synthesize a waveform with a sufficiently high frequency.

Therefore, in order to solve this problem, the waveform signal and the amplitude multiplier signal are converted into logarithms in advance to generate logarithmic signals and amplitude logarithmic signals, which are stored in memory, and both signals are sequentially read out and summed. By executing the process and converting the addition result into an antilog number (hereinafter referred to as inverse conversion) according to the logarithm-antilog number conversion table (hereinafter referred to as inverse conversion table) stored and formed in memory, it is possible to perform the addition process as a logarithm addition process. It has also been proposed to perform multiplication operations.

However, although the logarithm addition process described above can be executed at high speed, if we try to improve the accuracy of waveform signal synthesis processing by improving the resolution, a huge amount of storage capacity is required to create the inverse conversion table, which is extremely difficult. The drawback was that it was uneconomical.

An object of the present invention is to solve the problem of storage capacity for forming an inverse conversion table based on the above-mentioned prior art, and to store a logarithmic signal in its upper digits (hereinafter referred to as main logarithm number) and 1. A main inverse conversion table for inversely converting the addition result of the main logarithm signal and the amplitude logarithm signal, and the addition result of the interpolation logarithm signal and the amplitude logarithm signal. By providing an interpolation and inverse conversion table for inversely converting the data, we have developed an excellent waveform signal synthesis device that can significantly reduce the storage capacity required for forming the inverse conversion table without sacrificing the precision of waveform synthesis processing. This is what we intend to provide.

The configuration of the present invention in accordance with the above object is to provide a main logarithmic signal memory section and an interpolated logarithmic signal memory section, each of which stores a series of amplitude values obtained by sampling a reference waveform in a large number of time slots. The main logarithm signal (upper digits), which is a logarithmic representation of the waveform signal, and the interpolated logarithm signal (lower digits)
An amplitude logarithm signal memory section is provided, and a series of amplitude multiplier signals as each amplitude value obtained by sampling the envelope of the reference waveform in a large number of time slots is stored in this memory section. Ichisaku's amplitude logarithm signal expressed in logarithms, in Teniya's opinion, a series of amplitude logarithm complement signals expressed in complements are stored in advance, and further, A main inverse conversion table memory section and an interpolation inverse conversion table memory section are provided, each of which performs main inverse conversion for inversely converting the sum of a series of main logarithm signals and a series of amplitude logarithm complement signals into an antilog number. table and
An interpolation inverse conversion table for inversely converting the sum of a series of interpolated logarithmic signals and a series of amplitude logarithmic complement signals into an antilog number is stored in advance, and when synthesizing waveform signals, the main logarithm signal memory section and One main logarithm signal and one amplitude logarithm complement signal are read out from the amplitude logarithm signal memory section, the two signals are added in the main adder, and the antilog corresponding to the main sum signal as the addition result is calculated as the main inverse. Search according to the conversion table,
This is read out as the main waveform signal from the main inverse conversion table memory section, and then one interpolated logarithmic signal and one amplitude logarithmic complement signal are read out from the interpolated logarithmic signal memory section and the amplitude logarithmic signal memory section, and both signals are interpolated. The adder performs addition, searches for the antilog number corresponding to the interpolated sum signal as a result of the addition according to the interpolation inverse conversion table, reads it out from the interpolation inverse conversion table memory unit as an interpolated waveform signal, and combines it with the main waveform signal. The above-mentioned interpolated waveform signal is added by an adder, and the digital composite waveform signal as a result of the addition is converted into an analog composite waveform signal by a digital-to-analog converter, and such signal processing is performed to generate a series of main logarithm signals, interpolated logarithm signals, etc. signal, amplitude log-complement signal, and multiplying a reference waveform represented by a series of main log signals and an interpolated log signal by an envelope represented by a series of amplitude log-complement signals. When generating a composite waveform signal and searching according to the main inverse conversion table, each address of the memory elements constituting the main inverse conversion table memory section has a common ratio of 2'' (M is a positive integer).
Each numerical value of two numerical sequences (n is a positive integer) extracted from successive parts of the geometric series sequence is stored in advance and stored at the address specified by the main sum signal. When reading numerical values from the main inverse conversion table memory section and performing draft processing according to the interpolation inverse conversion table,
Each numerical value obtained by dividing the numerical value stored in each address of the memory element constituting the interpolation inverse conversion table memory section into each address of the memory device constituting the main inverse conversion table memory section (the second ward is a positive integer) is stored in advance, and the numerical value stored at the address specified by the interpolation sum signal is read out from the interpolation and inverse conversion table memory section.

The configuration and operation of an embodiment of the present invention will be described below based on FIGS. 1 to 4.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
Both output terminals of the amplitude logarithmic signal memory section 2 consisting of OM are:
The output terminals of the interpolation logarithmic signal memory section 3 and the amplitude logarithm signal memory section 2 are respectively connected to both input terminals of the interpolation addition section 50, and are respectively connected to both input terminals of the main addition section 4. be done.

Both output terminals of the main addition section 4 and interpolation addition section 5 are R
Main inverse translation table memory section 6 consisting of OM, same < RO
It is connected to an address signal terminal of an interpolation inverse conversion table memory section T consisting of M, and both output terminals of the inverse conversion table memory section 6 and T are connected to both input terminals of an adder section 8, respectively.

The output terminal of the adder 8 is the digital-to-analog converter
connected to the input terminal of

Note that the main logarithm signal memory section 1 and the interpolation logarithm signal memory section 3
An accumulating unit 1° is connected to the address signal terminal of the amplitude logarithm signal memory unit 2, and an address counting unit 11 is connected to the address signal terminal of the amplitude logarithmic signal memory unit 2.

Then, a control signal 1m9L%10 is sent from a noise control section (not shown).
aj1m each extends, and includes a digital-to-analog converter 9, an accumulator 10 . Each is connected to the address counting section 11.

In the above configuration, the main logarithm signal memory section 1 and the interpolated logarithm signal memory section 3 contain a main logarithm signal S1 representing four reference waveforms.
and interpolated logarithmic signal s3 are stored in advance.

As an example, a waveform signal when the reference waveform is a positive arc wave, a main logarithm signal S 1 corresponding to this, and an interpolated logarithm signal S
FIG. 2 is a graph showing the relationship between .

According to FIG. 2, the latter half cycle of the reference waveform A is folded back to form a positive half cycle A'. Each of the waveform signals 1o-IL1t7 obtained by sampling the previous half cycle and the second half cycle using 64 time slots, that is, the entire cycle using 128 time slots, is shown on the vertical axis. However, such a logarithmic signal is converted into a logarithm as represented by a scale, and a logarithmic signal sl, s is obtained. RO that formed memory
Since it serves as an address signal for M, it must essentially be a positive integer.Moreover, it is necessary to increase the number of digits of the logarithmic signal, reduce the quantization error, and obtain each signal with high resolution. When trying to obtain a logarithmic signal corresponding to the waveform signal "O""all?, the number of 7 addresses of the ROM for storing and forming the table required for the inverse conversion process, that is, the storage capacity becomes enormous, which is extremely inconvenient. It's the economy.

Therefore, the number of digits of the logarithmic signal is severely restricted by the above-mentioned Shioyama, so when converting each waveform signal '(1'' alhy) into a logarithmic signal while maintaining the restricted number of digits, is accompanied by a large quantization error during the conversion process.

The main logarithm signal S1 obtained by converting each waveform signal 80 to altF into a logarithm using the restricted number of digits as the upper digits and the quantization error generated during the conversion process are interpolated. In order to explain the relationship with the interpolated logarithm signal S obtained by converting the amount to be interpolated (hereinafter referred to as the interpolation amount) into a logarithm using the number of digits as the lower digits, the graph shown in FIG. FIG. 3 is an explanatory diagram showing a portion extracted and enlarged.

And in #I, Figure 2, - As an example, the reference waveform A
The maximum amplitude of the waveform signal all, that is, the value of the waveform signal all, is selected as the maximum value that can be expressed with 16 binary bits, 65536, and O~8.
If the one-sided amplitude of 55311 is divided into 1211 ranks specified by the main logarithm signal S1 of 128 states that can be expressed with T bits, as shown in FIG. 128 (O~
It is divided into the 108th rank of the 127th rank), so it is converted into a main logarithm signal turtle representing 101.

In this case, the waveform signal a8 is the amplitude value sampled in the 8th time slot of one cycle of a sine wave with one side amplitude of 655311 sampled in 1211 time slots from 0 to 127th. is 28
02G, this waveform signal a- is classified into ranks K
Okay, the main logarithm signal S that came to be applicable! The value of 108 is 2
Since it is a value obtained by converting TS54 into a logarithm, the waveform signal 1-
The difference between the value 21020 and the above 27554, ie, the part indicated by b8 in FIG. 3, is a quantization error due to logarithmic transformation due to the restricted number of digits, and this is the interpolation amount.

Then, if this interpolation amount is divided into 128 ranks specified by the interpolated logarithm signal S3 of 12 states, which can be expressed by the lower digits of the T bits following the upper digits of the main logarithm signal, the above interpolation amount , i.e. 2@020 and 27554 O
Since the difference 4@li d O corresponds to the 78th rank among the 127th ranks, an interpolated logarithm signal Ss having a value of 18 is obtained.

Here, in general, an arithmetic expression should be presented for converting each of the waveform signals ms""any into the main logarithm signal S1 and the interpolated logarithm signal 8m, but the above arithmetic expression is Since it is closely related to the inverse transformation process, the operation of the inverse transformation process will be explained below. In the following explanation, for convenience of explanation, the amplitude logarithmic signal S! is zero, the addition processing of the amplitude logarithm signal St in the main adder 4 and the interpolation adder 5 is not performed, and the main logarithm signal S 1 and the interpolated logarithm signal Sm are directly converted into the main sum signal S4 and the interpolated sum signal 5s.
Assume an example of operation such as ic.

Generally, the inverse conversion table is stored in each R constituting the main inverse conversion table memory section 6 and the interpolation inverse conversion triple memory section T.
Each of the series of addresses in OM is stored as a geometric series (a sequence in which the M+1st value is twice the first value) with a common ratio of 2, and the address specified by the address signal is stored. By reading out the stored contents, the logarithm represented by the main logarithm signal 81% interpolated logarithm signal Ss as an address signal is converted into an antilogarithm.

However, since the total number of series forming the table is limited from the viewpoint of storage capacity, the table is formed from a partial number sequence obtained by extracting a portion of the geometric series.

So, first, let's consider the main inverse transformation table.
Numerical value Ax (main waveform signal S
・) is represented by .

Here, ■ is a constant for specifying when X is 0, that is, the first numerical value of the partial sequence (hereinafter referred to as the first term), and the first address is ! ■ Taking 2 as a common ratio, based on the viewpoint of storage capacity and resolution, 2
Arrange a finite number of geometric series represented by , and the final (maximum) numerical value (hereinafter referred to as the final term) is the code bit stored in each address of the ROM that constitutes the main inverse transformation table memory section. From the viewpoint of ROM usage efficiency, it is desirable that the value be close to the maximum value that can be expressed numerically.

As an example, in a geometric series with a common ratio of 2, the first term (2
511) and the final term (6
When forming a main inverse transformation table with a partial sequence of 21 numbers ending in 275F), that is, 128 numbers, in equation (1), M=IL I e
It turns out that it is sufficient to select 1211.

One of the main inverse transformation tables created based on this selection
Table 1 shows the relationship between the 28 addresses and the 128 numerical values (main waveform signal Sa) stored in each address.

Next, considering the interpolation inverse conversion table, the numerical value Bx (interpolated waveform signal S?
) is represented by .

Here, K is a constant representing the ratio of digit weights between the main logarithm signal S1, which is the upper digit, and the interpolated logarithm signal Sm, which is the lower digit.

And J is a constant representing (I-MK).

Now, as an example, if we select K = 4, J = 64, and by dividing each value in Table 1 by 2', we can obtain 6 interpolation inverse transformation tables as shown in Table 2. It is something.

Subsequently, in order to search the main inverse transformation table and the interpolation inverse transformation table, the main logarithm signal S1 and the interpolated logarithm signal Ss are supplied as address signals to the main inverse transformation table memory section 6 and the interpolation inverse transformation table memory section T. Each waveform signal &
(1-Jt? When considering the calculation formula based on iC with reference to FIGS. 2 and 3, the formula is as follows.

First, the main logarithm signal S corresponding to the X-th waveform signal &X is 1 Srs −I NT (Ihxl) −・−・−−−
----------, , (s).

Here, Ax is a real number obtained by converting the waveform signal - into a logarithm, and the absolute value IAxl means turning back the half period after the reference wave A. (In order to eliminate the negative part of the waveform signal, the double-logarithmic signals s1 and s3 are used as they are in the 7-dress signal of the ROM in which the double-logarithmic conversion table is stored and formed when the double-logarithmic signals s1 and s3 are inverted.) This is the book you need to
T (IAxl) represents a value obtained by truncating the above IAXI to an integer that can be expressed by the number of digits of the main logarithm signal field.

However, the value Ax obtained by converting the waveform signal ~ into a logarithm is as follows:Ax=(Mklr, ari-■・・・・・・・・・・・・
...It is expressed as (4).

On the other hand, it is expressed by the interpolation amount IL when converting the waveform signal - into the main logarithm signal S1.

That is, the interpolation amount area is the difference between the X-th data of the main inverse conversion table and the waveform number -.

Therefore, the interpolated logarithmic signal 83 with respect to the waveform signal, 8sx = I N T (lBxl) −
・---(6)B! -(MkIlsbt)
-J 、、、・・・－・・・・・・・・・・・・(1
).

Then, each waveform signal 16""&11 is converted to M-16,'L"=12 according to the above calculation formulas (Equations (3) 2 to (7)).
8, lK# 4, the main inverse transformation table selected and created, the main logarithm signal S1 adapted to the interpolation inverse transformation table,
Interpolated logarithmic signal 8. When converted to , it becomes as shown in Table 3.

(3) Read out the main logarithm signal S1 corresponding to each of the waveform signals, which is stored in advance according to (3) and (4) 2, from the main logarithm signal memory section 1, and use this as an address signal. The main inverse transformation table is supplied to the memory section 6, and is calculated in advance according to equation (1).
Among the numerical values stored at each address, the numerical value stored at the address specified by the main logarithm signal S1,
That is, when reading out the main waveform signal S, both (5)
(@) Read out the interpolated logarithmic signal am corresponding to each of the waveform signals, which is calculated and stored in advance according to equation (7), from the interpolated logarithmic signal mesori section 3, and use this as an address signal in the interpolation inverse conversion table memory. 12)
From among the numerical values calculated in advance according to the formula and stored at each address of this memory section T, the numerical value stored at the address specified by the interpolated logarithmic signal S, that is, the interpolated waveform signal S By reading out p, the waveform signal is expressed separately with the main logarithm signal Ss as the upper digit and the interpolated logarithm signal Ss as the lower digit, and the double logarithm signals B@, 8@
is inversely converted into an antilog according to separate main inverse conversion tables and an interpolation inverse conversion table to obtain the main waveform signal S- and the interpolated waveform signal S.
1 and furthermore, both signals 8g and 8? The digital composite waveform signal S- can be obtained by adding them in an adder section.

The main operations in the configuration of this invention are shown in Tables 1 to 3.
Referring to the table, the operation example when processing the above-mentioned waveform signal &- will be explained in detail as follows.
.

The value of the waveform signal a shown as an example in FIG.
11. Selecting $(s) and calculating the main logarithm signal S1 corresponding to the waveform signal a according to equation (4), we get
As shown in BK in Table 3, 101 was obtained, and furthermore, K
-4 (J■・4) Select K (II), (・), ff
) If the interpolated logarithmic signal am is calculated according to the formula, $1 can be obtained as shown in C in the %#48 table.

Furthermore, the main inverse conversion table is searched using 1011 represented by the upper main logarithm signal S1 as an address signal, and the main waveform signal S.
As shown in Table 1, %! 7114 is obtained.

Furthermore, when the interpolation inverse conversion table is searched using 1. expressed by the interpolated logarithmic signal 8m as an address signal and the interpolated waveform signal Sma is obtained, as shown in E in Table 2, 4 is obtained.
10 is obtained.

Then, the digital composite waveform signal S・ obtained by adding both waveform signals S- and S-ma at the adder Hatake is 2755
The sum of 4 and 470, i.e. - As shown in F in Table 3,
28024, and the waveform signal a s (28020) has been approximately recombined.

Here, considering the basis for selecting K=4 in the above numerical example, the following is a general idea.

The eight interpolated waveform signals correspond to the maximum amount of interpolation that can be obtained with respect to the main waveform signal S6, that is, as shown in G in Table 1, the value (II 2 T 5 T) and the next address 028) after that final address are prepared.
As shown in H in Table 1, the numerical value to be stored there (
The turtle should be selected in such a way that it can express the difference of 21T@ between the two.

However, as shown in Table 2 I, the maximum value of the interpolated waveform signal St is the numerical value stored in the final address 027) of the interpolation inversion table memory section T, and this numerical value is as shown in Table 1 G. As shown in K, main and half conversion table memory section 6
The numerical value (627) stored in the final address 027) of
Since it is obtained by dividing 5F) by 2, KK should be selected so that this value is l larger than 2771.

Therefore, in the case of the above numerical example, K=4 is selected and the first
Dividing by @275[-2' shown in Table G, 3s22 shown in No. 21III is obtained, and this value is also larger than the maximum possible interpolation amount 2T79, so all interpolation amounts are Tpi) (128 states) can be expressed by an interpolated logarithm signal Bm.

In general, regarding the range of K that satisfies the above corollary, K is an integer within the range.

According to the numerical example above, M=1@, so 0(K(4,49,......
(9), and it can be seen that K-4 is one of the possible table selections.

The accumulator 10 receives a high-speed clock pulse C through the control signal line 10m from a control section (not shown), processes it, and adjusts the constant speed or the period of the reference waveform based on the calculation result. An address signal A1 that advances at a variable speed that changes as a unit is simultaneously supplied to the address signal terminals of the main logarithmic signal memory section 1 and the interpolated logarithmic signal memory section 3, and while ensuring synchronization, the address signal A1 is inputted from both memory sections 1.3. A series of main logarithm signals S1 and interpolated logarithm signals SS are sequentially read out at a constant speed 1 or at a variable speed. During this time, the address counting section 11 receives a clock pulse Cs from a control section (not shown) through a control signal line 11a. counts this,
In many cases, the amplitude logarithmic signal memory unit 2 stores the address signal A3, which advances at a constant speed lower than that of the address signal A1.
A series of amplitude logarithmic signals Ss are sequentially read out from the memory section 2 at a constant speed.

The amplitude logarithm signal memory section 2 is composed of a ROM like the main logarithm signal memory section 1 and the interpolated logarithm signal memory section 3, and each address stores a series of amplitude logarithm signals 8 representing a reference waveform.
m is stored in advance.

FIG. 4 shows the relationship between the series of amplitude logarithmic signals Ss and the reference waveform, and the process of generating the amplitude logarithmic signal 8s will be explained in the following manner with reference to FIG.

A specific reference waveform, typically an envelope R of a musical tone signal consisting of an attack part R1, a decay part R1, a sustain part R3, and a release part R4, is divided into a number of time slots (this time slot is the waveform signal "0," 1, al・
The time slots of ... do not need to be the same.

) by converting each of the series of amplitude multiplier signals r0, rl, rfi, . . . as amplitude values obtained by sampling at
This is the amount of money you can get.

9. Complement of each numerical value represented by the amplitude logarithm signal S3, for example, main/interpolated logarithm signal output; Similarly, the amplitude logarithmic signal S! When expressed with T bits, the maximum number of states that can be expressed with 7 bits is 128, so the "complement of 128" obtained by subtracting each numerical value represented by the amplitude logarithm signal S from 128 is By calculating, an amplitude logarithm complement signal S (hereinafter referred to as a complement signal) is obtained.

However, in practice, the arithmetic processing for obtaining the complement signal Sm can be replaced by arithmetic processing for representing the amplitude logarithm signal Sm in binary and calculating a "two's complement" number.

At this time, in many cases, the amplitude logarithm signal S, which is logarithmically expressed by the amplitude multiplier signal r0 corresponding to the peak value of the reference waveform R, is a numerical value (0), and the value for the minimum value is a numerical value (- 127), the amplitude of the reference waveform is standardized in advance.

In this way, a series of amplitude multiplier signals ro%r1, r atmosphere, etc., which vary as positive numbers less than or equal to the maximum value 1-, are converted into a series of waveform signals a. Complement signal S! is an arithmetic process that adds the negative amplitude logarithmic signal Sm encountered when multiplying ... to the main and interpolated logarithmic signals S1, S, S! This can be executed in place of the addition process.

Thus, processing companies that convert the amplitude logarithm signal St to the complement signal Sm, amplitude multiplier signals r@, rl, r2...
...is a positive number less than or equal to 1. Therefore, the amplitude logarithm signal Ss referred to in this specification is one form of the complement signal S3. It is inclusive.

Returning again to FIG. 1, the main logarithm signal S! is sequentially read out from the main logarithm signal memory section 1 in response to the address signal A1. , and each of the amplitude logarithm signals Ss sequentially read out from the amplitude logarithm signal memory unit 2 in response to the address signal Ax are supplied to the main adder 4, and the main adder 4 receives both signals S1 . Sm is added and a main sum signal S4 is output.

At this time, the amplitude logarithmic signal S! Since S is a negative number with a maximum value of 0, the subtraction is actually performed using the complement signal S.

Additionally, in many cases, the address signal As is the address signal A! Since Yoshi also steps at a high speed, the above addition process is executed according to the sidewalk speed of Address Tongo A1.
The same amplitude logarithm signal S1 is added (subtracted) until the address signal A3 advances.

Then, upon receiving the main sum signal S4 at the address signal terminal, the main inverse conversion table memory section 6 sequentially reads and outputs the main waveform signal islands stored at the address designated by the main sum signal S4.

On the other hand, each of the interpolated logarithmic signals Sm sequentially read out from the interpolated logarithmic signal memory section 3 in response to the address signal A1 and the address signal A! In response to the amplitude logarithm signal memory section 2
Each of the amplitude logarithmic signals Ss sequentially read out from
, Sm are added (subtracted) and an interpolated sum signal SS is output.

Then, receiving the interpolated sum signal S, at the address signal terminal,
The interpolation inverse conversion table memory section 7 sequentially reads and outputs the interpolated waveform signal St stored at the address specified by the interpolated sum signal Ss.

As mentioned above, the main waveform signal S6 and the interpolated waveform signal S1, which are read out sequentially while maintaining synchronization, are supplied to the adder.
The adder adds both signals 5-1Sγ and outputs a digital composite waveform signal S-.

The digital composite waveform signal S- generated in this way
is the waveform signal a・, &1s & for each time slot.
1'...- is the amplitude multiplier signal r for each time slot.
, rl, rl.''. The amplitude value of the composite waveform for each time slot is expressed as a digital quantity.

By converting the digital composite waveform signal S- into an analog quantity in the digital-to-analog converter 9 and executing this process for all time slots,
An analog composite waveform signal S- representing a desired composite waveform obtained by multiplying the reference waveform by the reference waveform is obtained at the output terminal of the digital-to-analog converter $.

In addition, in the above-mentioned signal processing 1M, the digital-to-analog converter 9 connects the control signal line 9 from the illustrated controller to the control signal line 9.
By receiving the polarity switching signal C1 through A and inverting the polarity of the output signal, that is, the analog composite waveform signal S, the negative part of the waveform can be generated according to the same signal processing as described above.

In addition, in the configuration of the above embodiment, as shown in FIG. 2, by folding back the half period after the reference waveform, the main inverse conversion table and the interpolation inverse conversion table are formed using only positive values. Therefore, the double-inverse conversion table memory sections II and 7 do not output negative waveform signals S and S.

Therefore, when generating the negative portion of the composite waveform, the polarity of the output signal must be inverted in the digital-to-analog converter 9.

In addition, the main waveform signal S. and the interpolation waveform signal 8? is obtained by inversely converting a logarithm into an antilog, so it is impossible to represent a numerical value (◎). However, for example, the minimum numerical value stored in the main inverse transformation table memory section 6, , as shown in J in Table 1, the main waveform signal S6 representing the numerical value (0) is obtained by replacing the numerical value (1511) stored at the address (0) with the numerical value (0) for convenience. I can do it.

Since the main and interpolated logarithmic signals Sl and Sg are closely related to the values stored in the main and interpolated inverse conversion table memory section 6.7, as mentioned above, several Substituting numerical values with other numerical values and slightly changing the regularity can be done arbitrarily without affecting the essence of the invention.

A configuration of a second invention related to the present invention is that, in the configuration of the present invention, each numerical value of the main inverse conversion table stored and formed in the main inverse conversion table memory section is divided by 2, so that the interpolation inverse conversion table memory Focusing on the property that each numerical value of the interpolation inverse conversion table stored in the main inversion table memory section can be obtained, the main logarithm signal read out from the main inversion table memory section is temporarily stored in the temporary storage section, and then , the main logarithm signal read from the main inverse conversion table memory section is shifted by bits in the direction of lower digits and supplied to the addition section, and the addition section stores the shifted main logarithm signal and the temporary storage 1 section. This is characterized in that K is added to the stored main logarithm signal.

FIG. 5 is a block diagram showing the configuration of an embodiment of the second invention related to the present invention. 1, its second input terminal is connected to the output terminal of the interpolation logarithmic signal memory section 3, and 1 its output terminal is connected to the first input terminal of the main adder section 4. .

The second input terminal of the main adder 4 is connected to the output terminal of the amplitude logarithmic signal memory section 2 .

The output terminal of the main inverse conversion table memory section 6 is connected to the first input terminal of the addition section S via the temporary storage section 13 consisting of a latch circuit, etc., and the second input terminal of the addition section S is connected to the main inversion table memory section 6. It is directly connected to the output terminal of the conversion table memory section 6.

The input terminal of the switching control section 140 is connected to a control signal line 141 from a control section (not shown), and its two output terminals are connected to the control terminals of the logarithmic signal switching section 12 and the temporary storage section 130, respectively.

Note that the other components are the same as those indicated by the same reference numerals in FIG.

In the above configuration, when the switching control section 14 receives a control signal C4 from a control section (not shown) through the control signal line 14a, it sends a switching command signal C to the logarithmic signal switching section 12 and outputs it to its first input terminal. Main logarithm signal S1 being supplied
is output and supplied to the first input terminal of the main adder 4.

The main adder 4 receives the main logarithm signal S1 and the amplitude logarithm signal S3 from the first and second input terminals, adds them, and outputs the main sum signal S4 to the main inverse transformation table memory section 6. supply to. The main inverse conversion table memory section 6 reads out the main waveform signal S from the address specified by the main sum signal S4 and outputs it.

At this time, the switching control section 14 sends an update command signal C to the control terminal of the temporary storage section 130, so in response to this, the temporary storage section 13 replaces the previously stored main waveform signal S. The read main waveform signal S. is temporarily stored.

Subsequently, while the address signal A1 remains in the same state, the switching control section 14 receives the control pulse C4 again.
sends the switching command signal C to the logarithmic signal switching unit 12, which in turn outputs the interpolated logarithmic signal Sm supplied to its second input terminal, and supplies this to the main adder 4.

The main adder 4 adds the interpolated logarithm signal Ss and the amplitude logarithm signal S3 and supplies the interpolated sum signal S@ to the main inverse conversion table memory section @. The main inverse conversion table memory section 6 reads out the main waveform signal S- from the address specified by the interpolated sum signal S, and outputs it.

At this time, the switching control section 14 does not send the update command signal C- to the temporary storage section 13, so the temporary storage section 13
remains in the state where the main waveform signal S6 is stored.

Therefore, the main waveform signal S@ read out this time is not stored in the temporary storage section 13, but is shifted by bits in the direction of the lower digits, that is, according to the embodiment of the present invention. Since K: 4, it is shifted by 4 bits in the direction of the lower digits and is supplied to the second input terminal of the adder as an interpolated waveform signal S.

FIG. 6 is a wiring diagram that extracts and shows the connection relationship between the main inverse conversion table memory section 6 and the adder section 8 that involve such a 4-bit shift.

As shown in the figure, among the output lines 6 extending from the output terminal of the main inverse conversion table memory section 6, the output line 6m corresponding to the MSB (most significant bit) is connected to the second input terminal of the addition section. is connected to the input terminal corresponding to the 11th bit of
Shift 4 bits in the direction of the lower digits and connect them, connect the following output lines sequentially in the same way, and connect the output line 61 corresponding to the 4th bit to the Oth bit of the second input terminal of the adder 8. The main waveform signal shift line 11m' is connected to the corresponding input terminal as the LSB (least significant bit).

In this way, the output line from the main inverse conversion table memory section $ is shifted in the direction of the lower digits by 4 bits and connected to the second input terminal of the addition section S, and the main waveform signal shift line 8 is connected to the second input terminal of the addition section S.
By forming a', the second input terminal of the adder 8 is supplied with a signal representing the numerical value obtained by dividing the numerical value represented by the main pair ◆ number signal S6 by 2. .

In the above embodiment, since K=4 is selected, this signal is nothing but the interpolated logarithmic signal Sv, and this signal is supplied to the second input signal of the adder 8, and , the first and second input terminals of the adder section ・temporary storage section I
The main logarithm signal S@ stored in SK and the interpolated logarithm signal S
Both signals S.1 and S7 are supplied simultaneously, and the addition of both signals S. and S7 is performed.

Subsequently, the address signal A1 of the main logarithm signal memory section 1 and the interpolated logarithm signal memory section 3 is incremented, and then the same operation is repeatedly executed.

By incrementing the address signal A of the amplitude logarithmic signal memory section 2 and repeating the same operation, the digital-to-analog converter 9 also converts a series of digitally synthesized waveform signals S- sequentially output from the adder L. By converting it into an analog quantity, one analog composite waveform signal S9 can be obtained.

In the configuration of the upper rear example, after the logarithmic signal switching section 12 switches between the main logarithm signal S1 and the interpolated logarithm signal Sm, the main addition section 4 adds the amplitude logarithm signal Sm. However, the present invention is not limited to this, and the main sum signal S4 and the interpolated sum signal 8. If the signals are supplied alternately, there will be a shortage, so as shown in FIG. Therefore, it is optional that the main sum signal S4 and the interpolated sum signal SI are switched by the sum signal switching section 12' and supplied to the main inverse conversion table memory section IK.

Next, referring to the above-mentioned invention and the operation when the second interpolated sum signal 8siZ that is zero consecutive to ζ·re becomes a negative value, it is as follows.

For example, the main logarithm signal S1 consisting of T bits is a numerical value (0)
, the bit array of 1,000 is roooooo
oOJ (0), and when this is supplied to the main inverse translation table memory section as an address signal, the address (
0) is specified and the first term shown in J in Table 1 (2S @)
is read out.

By the way, in general, when expressing a numerical value using a fixed number of bits, negative numerical values are often expressed using complements.

Now, hypothetically, the amplitude logarithm signal Sm is a numerical value (-1
), then the complement signal S! is expressed as a two's complement number. The bit array of is rllllllllJ (12υ), and this complement signal core and the rooo0000J (
The bit arrangement of the main sum signal S4 obtained by adding the main logarithm signal S4 having a bit arrangement of 0) in the main adder 4 is rl.
llllllJ θ2T), so if such a main sum signal S4 is supplied to the tt main inverse conversion table memory section 6 as an address signal and the main waveform signal S is searched,
The address (12F) is specified and the last item (@ 2 F SF) shown in G in Table 1 is read out.

The result of this calculation is converted into a waveform signal 10%a! , & so...- and the amplitude multiplier signal ro%r1, r! When checking in the area of ......, for a waveform signal that represents a numerical value equal to the peak value (1) of the normalized amplitude multiplier signal mentioned in the example, a positive number less than or equal to 1 The result of multiplying by the amplitude multiplier signal is,
It is clearly disadvantageous that a value much larger than the peak value (1) of the normalized amplitude multiplier signal (6 to 15゛υ) is obtained.

Generally, a T-bit complement signal 8s expressed in two's complement
When adding , the fact that the addition result does not become 8 bits (no overflow occurs) means that the addition result is a member, so rllllllll in the above operation example
When receiving the main sum signal S4 having a bit array of J, the address (-1), that is, the next address adjacent in the decreasing direction to the address (0) as shown in K in Table 1, is received. It is necessary to specify a value and read a different value.

When it is detected that the main sum signal S4 or the interpolated sum signal S is negative, the main inverse transformation table 1. as shown in Table 1 is performed. Alternatively, since it is not possible to search for the main waveform signal S6 and the interpolated waveform signal S1 by using the interpolation inverse conversion table as shown in Table 2, the main inverse conversion is also necessary for negative addresses expressed in complements. table
Alternatively, it is necessary to extend and store the interpolation and inverse conversion table, which is also a factor in increasing the storage capacity.

Therefore, the configuration of the third and fourth inventions that are directly related to this invention is that in the configuration of this invention and the second invention that is directly related to this, the main inverse conversion table memory section 1 or the 'interpolation inverse conversion table When the main sum signal S4 and the interpolated sum signal Ss supplied as address signals to the memory section FK become negative values, the address designated as 1 is circulated to the final address i, and then the negative value In addition to the property of sequentially stepping toward the first address as the absolute value of increases, the number of numerical values forming a storage string in the main/interpolation and inverse conversion table memory section 6.7. . ) is a partial sequence that is to be formed continuously from the first term of the partial sequence forming the above-mentioned key interpolation bi-inverse conversion table and extended to the area of smaller numerical values than the first term, In other words, each of two number sequences (n is a positive integer) obtained by extracting consecutive parts of the number sequence of a geometric series whose common ratio is 2 (M is a positive integer) to correspond to a negative address signal. Focusing on the property that numerical values can be calculated, the main sum signal S4
, when it is detected that the interpolated sum signal S m Al has become negative, these signals are used as address signals to be stored in the main inverse conversion table memory section 6 or shifted in the interpolation inverse direction, and the negative main sum signal S m S4, obtain the main waveform signal S and 8 interpolated waveform signals corresponding to the interpolated sum signal S, and then obtain the main inverse conversion table prepared for the positive main sum signal 84 and the interpolated sum signal Ss, or This tortoise is characterized in that the interpolation inverse conversion table can also be used for the negative main sum signal s4 and the interpolation sum signal Sg.

The structure and operation of the embodiment of the third invention related to this invention will be explained as follows based on FIG. S.

FIG. 8 is a block diagram showing the configuration of an embodiment of the third invention, in which a shift control section 1s is connected to the main addition section 4, and a main inverse conversion table memory section 6 and an addition section are connected. In between, there is a main waveform signal shift switching section 1 consisting of a data selector, etc.
6 is inserted, and its control terminal is connected to the output terminal of the shift control section 15.

- The output line of the main inverse conversion table memory section 6 is directly connected to the first input terminal of the main waveform signal shift switching section 16, while the second input terminal thereof is connected directly to the first input terminal of the main waveform signal shift switching section 16. Similar to the main waveform signal shift line 1m', the output line from the main inverse conversion table memory unit 6 is shifted by 8 bits in the direction of the lower digits and connected.

Similarly, a shift control section 15' is connected to the interpolation and addition section S, and an interpolation waveform signal shift switching section 11, which also includes a data selector, is connected between the interpolation and inverse conversion table memory section 1 and the addition section 8. The output terminal of the shift control section 15' is connected to the control terminal of the shift control section 15'.

1 interpolation waveform signal shift switching unit 17c) IR-connection between the second input terminal and the interpolation inversion table memory unit T, and between the main waveform signal shift switching unit 16 and the main inversion table memory unit 6 The wiring is done in exactly the same way.

Other constituent elements are the same as those indicated by the same reference numerals in the enlarged view of FIG.

In the configuration of the embodiment of the third invention, the main adder 4
When adding the main logarithm signal S1 expressed in binary and the complement signal Ss expressed in two's complement, for example,
Based on the fact that no digit deviation occurs, it is detected that the main sum signal S4, which is the addition result, is negative, and the polarity signal C? is sent to the shift control section 15.

In response to this, the shift control section 15 sends a shift switching signal C, to the main waveform signal shift switching section 1@, and its output terminal receives the signal supplied to the second input terminal, that is,
The main waveform signal S is shifted by 8 bits in the direction of the lower digits.
Perform a switching operation that outputs .

Furthermore, when the interpolation adder 5 adds the interpolated logarithm signal S expressed in binary and the complement signal S expressed in 2's complement, the interpolated sum signal which is the addition result is similarly added. Sg
is negative, and sends a polarity signal C'γ to the shift control section 15'.

In response, the shift control section 15' sends a shift switching signal C4 to the interpolation waveform signal shift switching section 17.
a signal that is fed to a second input terminal to its output terminal;
That is, a switching operation is performed to output the interpolated waveform signal S which has been shifted by 8 bits in the direction of the lower digits.

Therefore, when the main sum signal S 4 supplied as an address signal to the main inverse conversion table memory section 6 or the interpolated sum signal Ss supplied as an address signal to the interpolation inverse conversion table memory section T becomes negative. The two input terminals of the adder 8 respectively receive the main waveform signal S・, which has been shifted by 8 bits in the direction of the lower digits, and the interpolated waveform signal 8? is supplied.

Note that operations other than those described above are the same as those of the configuration of the embodiment of the present invention shown in FIG.

Here, in the operation of the above embodiment, the main waveform signal S.
Considering the meaning of shifting each of the interpolated waveform signals S by 8 bits in the direction of the lower digits, the following is true.

First, while referring to Table 1, regarding the partial sequence constituting the main inverse transformation table, the first term A(l
Quantitatively expressing the relationship between 18÷L that should be placed next to the final term A-3 shown in HK in the same table, n) b---+L = A6 X 2 --- = ”
-...(10).

Furthermore, if we follow the numerical example in Table 1, Am* +L ”
Since All5 sM=16, n-7, Alm = A 6 X 2' −・−・−・・
・, ・,, ・・, ,,, (11>, so the first
It can be seen that the first term (256) shown in J in the table is a numerical value obtained by dividing the next term (s s s s s) after the last term shown in H in the same table by 21. □This means that the main inverse transformation sigil is a sequence of numbers extracted from successive parts of a geometric series with a common ratio of 2.In other words, for any number in the table, the larger region And M+
If the number placed in the first position is twice that number, the relationship holds true, and this relationship is extended for the range of numbers beyond the range shown in Table 1. This is due to the property that it holds true.

Therefore, the area below by one number, that is, the first term A@
Equation (11) also holds true for the relationship between the term A-, which should be placed one position lower, and the final term AIF, so As5y = A ml X 2'' -...
・・・・・・・・・・・・・・・・・・02) If you divide the final term (627!?) shown in G in Table 1 by 28, you will get K in Table 1. The term adjacent below the first term shown, i.e.
Numerical value (z4s) to be searched according to address (-1)
) is calculated.

Then, in the 01)(1υ formula, Ao, 1118%, -1, and Auytt are all in a "12s complement" relationship, that is, a "2's complement" relationship when expressed in binary numbers, so the address signal The bit arrays of the main sum signal S4 as Ao and All8 are both roooooo.

Regarding A-1 and ASrI, both rll
llllll'' and shi, each having the same bit arrangement.

Therefore, it can be seen that when it is detected that the main sum signal S4 is negative, the main waveform signal S read out from the address specified by the main sum signal S4 itself can be divided by 2''.

Then, the bit array of the main sum signal S4 representing the numerical value (-1) is rllllmlJ, and even if the main adder 4 detects that this is negative, the bit array rllll1111J is Since it is supplied as an address signal to the main inverse conversion table memory section -, the final term shown in G in Table 1 is read out as the main waveform signal S- in the main inverse conversion table, and this is divided by 28. In particular, a value that is suitable for the value adjacent to the lower part of the first term shown in Table 1, ie, the value to be stored at address (-1), is calculated.

This means that the number of numerical values composing the partial sequence forming the main inverse conversion table is two, and the address specifying each numerical value is expressed as an h-bit binary number, that is, According to the above operation example, the number of numerical values is selected to be 2q, and the main sum signal S4 as an address signal is also 7.
This is due to the fact that it is expressed in bits.

Therefore, in the same way, each value in Table 1 is changed to 21.
By dividing by It is possible to obtain an appropriate external main waveform signal S@ corresponding to the negative zero main sum compensation signal 84 only by arithmetic processing.

Table 4 shows a numerical example of a virtual main inverse conversion table corresponding to the address signal of the negative area calculated in this way, that is, the main sum signal S4 of the negative area.

Regarding the interpolation inverse conversion table shown in Table 2, the book,
Since there is no change in the nature of the numerical sequence, the above explanation can be applied to it, and by dividing each numerical value in the interpolation inverse conversion table by 2a), an appropriate interpolation waveform corresponding to the interpolation sum signal SI in the negative region can be obtained. Of course, it is possible to obtain the signal S.

Returning to FIG. 8, when it is detected that the main sum signal S4 supplied as an address signal to the main inverse conversion table memory unit @ is negative, the main waveform signal S is also transferred to the interpolation inverse conversion table memory unit When it is detected that the interpolated sum signal S$ supplied to T as an address signal is negative,
The operation of shifting each of the interpolated waveform signals S by 8 bits in the direction of the lower digits is to divide the main waveform signal S4, the main waveform signal S-1 read out corresponding to the interpolated sum signal island, and the interpolated waveform signal S1 by 2'. The calculation process required is 11.

Next, the structure and operation of the fourth embodiment of the invention, which is directly related to the present invention, will be explained as follows based on FIG.

FIG. 1 is a block diagram showing the configuration of an embodiment of the fourth invention described above. Between the main inverse conversion table memory section, the temporary storage section 13, and the addition section 8, there is a main waveform signal shift A switching section 16 is inserted, and a shift control section 15 is connected to the addition section 4.5, and its output terminal is connected to a main waveform signal shift switching section 160 control terminal.

The other components are the same as those indicated by the same reference numerals in FIG.

In the configuration of the embodiment of the fourth invention, the adder 4, B performs the addition process of the main logarithm signal s1 and the complement signal S and the addition process of the interpolated logarithm signal s3 and the complement signal Eb in a time-division operation. When , the main logarithm signal S! When k detects that the addition result of the and the complement signal S is negative, it sends a polarity signal C to the shift control section 15, and in response, the shift control section 15 sends a shift switching signal C-. The main waveform signal S6 supplied to the main waveform signal shift switching section 16 and read out from the main inverse conversion table memory section is shifted by Kl bits in the lower digit direction and stored in the temporary storage section 13.

Then, the subsequent addition process in the addition unit 4.5, that is,
Interpolated log signal 8. It operates in exactly the same way when adding the signal Sm and the complement signal Sm.

In this way, when it is detected that the main sum signal S4 or the interpolated sum signal Sll is negative, the main waveform signal S6 or the main waveform signal shift line 6 to be stored in the temporary storage section 1s is By shifting ``a'' by 4 bits, the interpolated waveform signal S1 and the main waveform signal S to be interpolated are shifted by 8 bits in the direction of the lower digits.

Operations other than those described above are the same as those of the configuration of the second embodiment of the invention that is directly related to the present invention shown in FIG.

As described above, the present invention converts and represents a reference waveform into a series of main logarithmic signals as the upper digits and a series of interpolated logarithmic signals as the lower digits, and further converts the reference waveform into a series of amplitude logarithmic signals. If the main waveform signal is generated by inversely converting the main sum signal obtained by adding the main logarithm signal and the amplitude logarithm signal to an antilog according to the main inverse conversion table, then 4, the interpolated logarithm signal The interpolated sum signal obtained by adding the and the amplitude logarithmic signal is converted into an antilog number according to the interpolation inverse conversion table to generate an interpolated waveform signal, and then both waveform signals are added to generate a composite waveform. The main inverse conversion table consists of two sequence numbers (n is a positive integer) obtained by extracting consecutive parts of a geometric series sequence with a common ratio of 2 (CM is a positive integer) for each address of the memory element. The interpolation inverse conversion table stores each value obtained by dividing each value in the main inverse conversion table by 2 (K is a positive integer) at each address of the memory element. Therefore, according to the present invention, although it is possible to perform multiplication processing at high speed as logarithmic addition processing, it is possible to perform multiplication processing at high speed by using only the main logarithm signal as the only main inverse transformation table. Compared to previous devices that perform inverse conversion, it is possible to significantly reduce the capacity of the inverse conversion table required to maintain the same accuracy, that is, the total storage capacity of the main inverse conversion table memory section and the interpolation inverse conversion table memory section. It has excellent effects.

Furthermore, a second invention related to Jin's invention is to alternately supply the main sum signal and the interpolated sum signal as address signals to the main inverse conversion table memory section, and read out from the address specified by the main sum signal. The main waveform signal read out from the address specified by the interpolated sum signal is then shifted by K (positive integer) bits toward the lower digits to create an interpolated waveform. By supplying the signal to the adder as a signal and adding this signal to the main waveform signal stored in the temporary storage section, each value in the main inverse conversion table is divided by 2, and each value in the interpolation inverse conversion table is Based on the property that it can be obtained, the main inverse conversion table memory section is configured so that it can be shared as an interpolation inverse conversion table memory section in a time-sharing manner.According to the second invention related to this invention, There is no need for an interpolation inverse conversion table memory section, and the present invention has an excellent effect in that the capacity of the inverse conversion table memory section is increased compared to the configuration of the present invention.

Furthermore, a third invention related to this invention is that when it is detected that the main sum signal or the interpolated sum signal is negative,
In response to the polarity signal output from the main adder or interpolation adder, the main waveform signal shift switching section and interpolation waveform signal shift switching section shift the output from the main inverse conversion table memory section in the direction of the lower digits. In addition, a fourth invention related to this invention is that when it is detected that the main sum signal or the interpolated sum signal is negative, the polarity signal outputted by the adder is In response, the main waveform signal shift switching section is configured to be able to change the main inverse transformation table of the negative region, according to the third and fourth inventions, at the expense of a large storage capacity. Alternatively, it is dangerous to memorize and form an interpolation inverse conversion table for the negative region, and the main sum signal and interpolated sum signal become negative by simply adding a main waveform signal shift switching section or an interpolation waveform signal shift switching section. Even if
Based on the main waveform signal and interpolated waveform signal read in response to the negative main sum signal and interpolated sum signal, appropriate main waveform signal and interpolated waveform corresponding to the negative main sum signal and negative interpolated sum signal are determined. It has the excellent effect of being able to generate signals.

Tables 1 to 4 are listed below.

Table 2 Table 3 Table 4

[Brief Description of the Drawings] Figures 1 to 4 relate to an embodiment of the present invention, with Figure 1 being a block diagram showing its configuration, and Figure 2 showing the main logarithm signal 81% interpolated logarithm signal S1. An example graph, FIG. 3 is an explanatory diagram showing an extracted and enlarged part of the graph in FIG. 2,
FIG. 4 shows the amplitude logarithmic signal St and its complement signal S! This is a graph illustrating. Figures S to T relate to an embodiment of the second invention that is connected to this invention, Figure 5 is a block diagram showing its configuration, and Figure 6 is the main inverse transformation table memory in Figure 5. A wiring diagram extracting and showing the connection relationship between the section 6 and the addition section 8, 1st
The figure is a block diagram extracting and showing the main parts of another embodiment. It is a block diagram which shows the structure of the Example of the fourth invention which is zero-continuous. 1...Main logarithm signal memory section 2...Amplitude logarithm signal memory section 3...Interpolation logarithm signal memory section 4...Main addition section 5-... ...Interpolation and addition section 6...Main inverse conversion table memory section T...
...Interpolation inverse conversion table memory section 8...Addition section ■...Digital-analog conversion section 10...
... Accumulator 11 ... Address counting section 12 ... Logarithmic signal switching section 12' ...
Sum signal switching section 13...Temporary storage section 14.
...Switching control section Is, 15'... Shift control section 16... Main waveform signal shift switching section 1T...
...Interpolation waveform signal shift switching unit patent applicant Roland Co., Ltd.

Claims (6)

[Claims] (1) Sequentially read out a series of main logarithmic signals S1 as the upper digits of a series of logarithmic signals formed by logarithmically representing a series of waveform signals as each amplitude value obtained by sampling a reference waveform in a large number of time slots. a main logarithmic signal memory means 1 for storing a reference waveform in a sequentially readable manner; an amplitude logarithm signal memory means 2 for storing in a sequentially readable manner a series of amplitude logarithm signals Sm logarithmically representing a series of amplitude multiplier signals as each amplitude value obtained by sampling; and a main logarithm signal memory means 1. main addition means 4 for adding the main logarithm signal S1 sequentially read from the amplitude logarithm signal S1 and the amplitude logarithm signal Ss sequentially read from the amplitude logarithm signal memory means 2 and outputting the addition result as a main sum signal S4; and interpolation logarithm signal memory means an interpolation adding means 5 for adding the interpolated logarithmic signals S sequentially read from the amplitude logarithmic signal measurement means 3 and the amplitude logarithmic signal Ss sequentially read from the amplitude logarithmic signal measuring means 2 and outputting the addition result as an interpolated sum signal aS;
A main inverse conversion table memory means 6 that searches the main sum signal S4 as an address signal according to a main inverse conversion table, inversely converts it into an antilog number and outputs it as a main waveform signal S@; and an interpolated sum signal Sm as an address signal. an interpolation and inverse conversion table memory means T that retrieves the result according to an interpolation and inverse conversion table, inversely converts it into a one-log number, and outputs it as an interpolated waveform signal S7; and a digitel composite waveform by adding the main waveform signal $- and the interpolated waveform signal ay. The main inverse conversion table memory means 6 comprises: an addition means for outputting a signal S; and a digital-to-analog conversion means 1 for converting the digital threat waveform signal S into an analog composite waveform signal S; Allocate each value of a 2nIl number sequence (n is a positive integer) obtained by extracting a continuous part of the number sequence of a geometric series whose common ratio is 2M (M is a positive integer) to each address. form the main inverse transformation table,
The interpolation inverse conversion table memory means T stores each numerical value stored in each address of the main inverse conversion table memory means 6 into 2
A waveform signal synthesis device characterized in that each numerical value obtained by dividing by (K is a positive integer) is stored in each address to form an interpolation inverse conversion table. (2) Sequentially read out a series of main logarithmic signals s1 as the upper digits of a series of logarithmic signals formed by logarithmically representing a series of waveform signals as each amplitude value obtained by sampling a reference waveform in a large number of time slots. a main logarithmic signal memory means 1 for storing a reference waveform in a sequentially readable manner; amplitude logarithm signal memory means 2 for storing in a sequentially readable manner a series of amplitude logarithm signals Ss logarithmically representing each amplitude value obtained by sampling and a series of amplitude multiplier signals; a main addition means 4 for adding the main logarithm signal S1 sequentially read from the memory means 1 and the amplitude logarithm signal S1 sequentially read from the amplitude logarithm signal memory means 2 and outputting the addition result as a main sum signal S4; interpolation and addition means 5 for adding the interpolated logarithm signal ss sequentially read from the signal memory means 3 and the amplitude logarithm signal Ss sequentially read from the amplitude logarithm signal memory means 2 and outputting the addition result as an interpolated sum signal SL1; , signal switching means 12,12' which alternately selects the main sum signal S4 and the interpolated sum signal S and supplies it to the main inverse conversion table memory means 6; and the main sum signal S as an address signal.
4. A main inverse conversion table memory means 8 for searching each of the interpolated sum signals S- according to the main inverse conversion table, inversely converting it into an antilog number, and outputting it as a main waveform signal S, and in response to the main sum signal S4. Temporary storage means 13 temporarily stores the main waveform signal S- outputted by the main inverse conversion table memory means 6, and main waveform signal S- outputted by the main inverse conversion table memory means 6 in response to the interpolated sum signal Ss. main waveform signal shift means 8m' that generates an interpolated waveform signal S by shifting it by bits (integer) toward the lower digits, and a main waveform signal S6 from the temporary storage means 13 and the main waveform signal shift means 6a'. an adding means 6 for adding the interpolated waveform signal S7 and outputting the resultant as a digital composite waveform signal S8;
The main inverse conversion table memory means 6 has a common ratio of 27'r (M is a positive integer), etc. A waveform signal synthesis device characterized in that a main inverse conversion table is formed by storing each value of two number sequences (n is a positive integer) at each address by extracting consecutive parts of a number sequence of a ratio series. (3) The signal switching means 12 alternately selects the main logarithm signal S1 output from the main logarithm signal memory means 1 and the interpolated logarithm signal S3 output from the interpolation logarithm signal memory means 3, and supplies the selected signals to the main addition means 4. The waveform signal synthesis device according to claim 2, wherein the waveform signal synthesis device is logarithmic signal switching means 12 that performs a logarithmic signal switching means 12. (4) The signal switching means alternately selects the main sum signal S4 outputted by the main addition means 4 and the interpolated sum signal Ss outputted by the interpolation addition means S, and supplies the sum signal to the main inverse conversion table memory means 6. The waveform signal synthesis device according to claim 2, which is the switching means 12'. (5) Sequentially read out a series of main logarithmic signals SX as upper digits of a series of logarithmic signals formed by logarithmically representing a series of waveform signals as each amplitude value obtained by sampling a reference waveform in a large number of time slots. a main logarithmic signal memory means 1 for storing a reference waveform in a sequentially readable manner; an amplitude logarithm signal memory means 2 for storing in a sequentially readable manner a series of amplitude logarithm signals Sm logarithmically representing a series of amplitude multiplier signals as each amplitude value obtained by sampling; and a main logarithm signal memory means 1. a main addition means 4 for adding the main logarithm signal S1 sequentially read from the amplitude logarithm signal S1 and the amplitude logarithm signal S sequentially read from the amplitude logarithm signal memory means 2 and outputting the addition result as a main sum signal S4; and an interpolation logarithm signal memory. interpolating and adding means 5 for adding the interpolated logarithmic signal S3 sequentially read from the means 3 and the amplitude logarithmic signal S sequentially read from the amplitude logarithmic signal memory means 2 and outputting the addition result as an interpolated sum signal Ss;
A main inverse conversion table memory means 6 searches the main sum signal S4 as an address signal according to a main inverse conversion table, inversely converts it into an antilog and outputs it as a main waveform signal S6, and interpolates an interpolated sum signal Sg as an address signal. an interpolation inverse conversion table memory means 1 that searches according to an inverse conversion table, inversely converts it into an antilog number and outputs it as an interpolated waveform signal S1; and a digital composite waveform signal SS that adds the main waveform signal S and the interpolated waveform signal S1. and a digital-to-analog converter US for converting the digital composite waveform signal 81 into an analog composite waveform signal S. -IGN is 3 ratio 82
A main inverse conversion table is formed by storing each value of two number sequences (net positive integers) obtained by extracting consecutive parts of the number sequence of a geometric series that is positive (Ma positive integer) at each address, The interpolation inverse conversion table memory means T stores each numerical value obtained by dividing each numerical value stored in each address of the main inverse conversion table memory means 6 by 2 (Kli positive integer) in each address and performs interpolation inverse conversion. In a waveform signal synthesis device characterized by forming a conversion table, a main sum signal S
4 is negative, when the main addition means 4 supplies the main waveform signal shift switch R1@ to the output addition means 8.
and 1 when it is detected that the interpolated sum signal S$ is negative.
An interpolated waveform signal shift switching means 1T is provided which shifts the interpolated waveform signal S7 by M bits in the direction of lower digits in response to the polarity signal Cz outputted by the interpolating and adding means 5, and then supplies the interpolated waveform signal S7 to the adding means 8. Waveform signal synthesizer. (6) Sequentially read out a series of main logarithmic signals S1 as upper digits of a series of logarithmic signals formed by logarithmically representing a series of waveform signals as each amplitude value obtained by sampling a reference waveform in a large number of time slots. a main logarithmic signal memory means 1 for storing a reference waveform in a sequentially readable manner; A series of amplitude logarithmic signals S! are formed by logarithmically representing a series of amplitude multiplier signals as each amplitude value obtained by sampling at S! an amplitude logarithm signal memory means 2 which stores the amplitude logarithm signal in a sequentially readable manner; a main logarithm signal 8 which is sequentially read out from the main logarithm signal processing means 1; the main addition means 4 which adds the addition result as a main sum signal S4, the interpolated logarithm signal S3 which is successively read out from the interpolation logarithm signal memory means 3, and the amplitude logarithm signal Sm which is successively read out from the amplitude logarithm signal memory means 2. interpolation addition means 5 for adding the sum and outputting the addition result as an interpolation sum signal 8m;
Signal switching means 12 which alternately selects the main sum signal S4 and the interpolated sum signal S1 and supplies it to the main inverse conversion table memory means.
12', a main sum signal S4 as an address signal, and an interpolated sum signal S@, respectively, according to a main inverse transform table, and are inversely converted into antilog numbers and outputted as a main waveform signal S@. 6, a temporary storage means 13 for temporarily storing the main waveform signal S@ outputted by the main inverse transformation table memory means 6 in response to the main sum signal S4, and an interpolated sum signal S1.
main waveform signal shifting means 6a/ for generating an interpolated waveform signal S by shifting the main waveform signal S@ outputted by the main inverse conversion table memory means 6 by bits (integer) in the direction of the lower digits in response to; Main waveform signal S from temporary storage means 13,
and the interpolated waveform signal S? from the main waveform signal shift means 6m'.
an adding means for adding together the digital composite waveform signal S and outputting the digital composite waveform signal S@; Digital-to-analog conversion means for converting ■ A main inverse conversion table is formed by storing each value of two number sequences (n positive integers) in each address by extracting consecutive parts of a number sequence of a certain geometric series. In the waveform signal synthesis device characterized in that the main sum signal S4 or the interpolated sum signal S
When detecting that 1 is a member, the main addition means 4 or the interpolation addition means 5 outputs a polarity signal C! In response to this, the main waveform signal S read out from the main inverse conversion table memory means 6 is shifted by M bits in the direction of the lower digits, and then transferred to the temporary storage means 13 and the main waveform signal shift means 51.
A waveform signal synthesis device comprising main waveform signal shift switching means 11 for supplying to aI.