JPS58200294A - Envelope signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope signal generator that generates various envelope signals of musical tone signals used in electronic musical instruments as digital data, and in particular, the present invention relates to an envelope signal generator that generates various envelope signals of musical tone signals used in electronic musical instruments as digital data. It is made possible to occur.

FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is the keyboard section, 2 is the operation section consisting of a tone tablet switch, an on/off switch for the vibrato effect, a volume for setting the depth of the vibrato effect, etc., and 3 is the central processing unit (CPU), which is used for computers etc. 4 is a read/write storage device (random access memory, usually called RAM), and 5 is a read-only storage device in which the program that determines the operation of the CPU 3 is stored. memory (usually called ROM).

A ROM 7 stores envelope parameters among parameters for synthesizing timbres, and a ROM 6 stores data related to frequencies among parameters for synthesizing timbres.

8 is the frequency control device of the present invention, 9 is the patent application No. 56-165.
A sine wave generator such as No. 189, 1o an envelope signal generator, 11 a multiplier that multiplies the envelope data representing the sine wave and the envelope signal, and 12 a time division multiplexed multiplication result. Of these, you can add certain things together,
A time slot controller for changing the order of time division multiplexing, 13 a time division multiplexed phase modulator, 14 a digital to analog converter, and 15.16 an electroacoustic transducer.

Keyboard section 1. Operation unit 2, CPU5, RAM4, RO
M5, ROMe, ROMy, frequency controller 8° envelope signal generator 1o are coupled by a data bus, an address bus and a control line. The method of coupling the data bus, address bus, and control lines in this way is a well-known method used mainly in minicomputer beaters and microcomputers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner.

Multiple address buses, for example 16, are also prepared, and normally the CPU a fr near address code is output, and other parts receive and receive the address code. The control line is usually the memory request line (MREQ).

5 pages A light line (WR) or the like is used.

MREQ indicates reading and writing memory, l0R
Q indicates that the contents of the input/output device (Ilo) are retrieved, and RD indicates that the contents of the input/output device (Ilo) are to be retrieved. WR indicates the timing to read data from memory or I/? 5 shows the timing of writing data.

An example of a microprocessor using such a control line is the microprocessor Zao manufactured by Zilog.

Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.

The keyboard section 1 divides a plurality of key switches into a plurality of groups □-□
The i:5N-OFF state of the key switches in the group can be sent to the data bus all at once. For example, in the case of a five-octave keyboard, the 61 keys are divided into 10 groups of six keys (half an octave) and 11 groups of one key each, and one address code is assigned to each group. An address code indicating one of the above groups arrives on the address line, and the 6-page address code is decoded to produce 6-bit or 1-bit data indicating ON-OFF of the key switch in the corresponding group. Output to data bus. Of the 0 operation section 2, which can be constructed using a decoder, a bus driver, and some gate circuits, the tablet switch can have a configuration similar to that of the keyboard section 1. Regarding the setting status of the volume, the voltage output from the volume is converted into a digital code by an analog-to-digital converter, and this is read out by the address code and the control lineman ΦRQ and RD.0 CPUA is the internal program counter. The instruction code is read from the address of the ROMes corresponding to the code, and is decoded to perform operations such as arithmetic operations, logical operations, reading and writing data, and jumping instructions by changing the contents of the program counter. The procedures for these operations are written in the ROM6. First, the CPU
3 reads from the ROM 5 an instruction for importing data of the keyboard section 1, reads seven pages, and imports codes indicating ΦN-0FF of each key of the keyboard section 1 for each group. Then, the key code being pressed is assigned to a finite channel of the tone generator.

Next, the CPU 3 sequentially reads from the ROM 5 a group of instructions for importing data from the operating section 2, decodes them, outputs address coated control signals 10RQ and RD corresponding to the operating section 2, and outputs them to the data bus. Codes expressing the states of the switches and volume of the operating section 2 are output and read into the CPU 5. Then, the CPU 3 knows which timbre of musical tone signals should be synthesized.

Now that it is clear which tone with which frequency should be generated in which channel of the musical tone generator,
The CPU 5 receives the address code and control signal MRE that stores the frequency parameters of the desired tone from the ROMcs that stores data regarding the frequency of each tone.
Q and RD are output, a desired frequency parameter is read out onto the data bus, taken into the CPU 5, and written into the frequency control device 8. In order to write, the frequency control device 8
The CPU 5 outputs an address code corresponding to a data register provided inside the CPU 5, and at the same time, data representing a frequency parameter that is output on the data bus from time to time is written to the data register.

Next, timbre parameters representing the content of the timbre to be output are read from the ROM 7 and written into the internal register of the envelope generator 10. Next, when a sound output command is given to both the frequency control device 8 and the envelope generator 1o, the frequency control device 8 gives a jump number of 1 to the sine wave generator 9, and the envelope signal generator 1o sends the envelope data. Occur.

The sine wave data output from the sine wave generator 9 and having a frequency proportional to the jump number 1 and the envelope data are multiplied to give an envelope to the sine wave. The sine wave data and de-envelope data are generated by time division multiplexing, respectively. Time division multiplexing is, for example, 160 multiplexed, and 2.9 pages of sine waves are allocated to each channel, providing 8 channels.

Normally, one musical tone is synthesized by synthesizing 20 sine waves. Therefore, as known from the Fourier series formula, 20 sine wave data are added. The time slot converter 12 performs data addition between these idle time slots. The time slot converter adds predetermined data to reduce the number of time slots among the sine wave data strings modulated with envelope data, which are time-division multiplexed and input into 160 time slots, or This converts time slots like the time division multiplex converter of Japanese Patent Application No. 57-202790. The time-division multiplexing phase modulator 13 performs multiple types of modulation simultaneously by time-division multiplexing, as in Japanese Patent Application No. 56-1820831 "Digital Musical Tone Modulation Apparatus".

The output of the time division multiplex phase modulator 13 is converted into an analog signal by the analog-to-digital converter 14, and is outputted from the electroacoustic transducers 15 and 16. Slot converter 12
The module is connected to the CPU 3 via the address bus, data path, and control line to the time division multiplexing phase modulation device 13, and controls the time slot in response to the tone color and modulation effect settings made by the operation section 2. It is possible to set the conversion and modulation conditions by changing them.

In FIG. 1, the envelope signal generator 10 outputs an address and a read command signal to the ROM 7 so that desired data can be directly read.

FIG. 2 is a block diagram of an embodiment of the envelope signal generator of the present invention. In FIG. 2, 7 is the above-mentioned parameter R and M, and data obtained by compressing the sample value of the envelope signal is stored inside the column. 20 is a sample calculator, 21 is a tablet interface, 221d is a key interface, and 23 is an interpolation calculator.

Tone color codes are supplied to the tablet interface 21 and the parameter ROM 7 from the CPU shown in FIG. The upper three bits of the tone code are applied to the upper address of the parameter ROM7 as a code specifying one of the eight types of musical instruments, and the parameters of the specified instrument sound among the parameters R◇M7 are stored. Select the area that is displayed.

The lower bits of the timbre code include data indicating the timbre mode, for example, whether the envelope shape is organ-shaped or piano-shaped, and is supplied to the sample arithmetic unit 20 via the tablet interface 21. The tablet interface 21 includes a data latch, and the CPU 3 writes a tone code to the data latch, and then the sample arithmetic unit 20 reads it out at a necessary timing. The CPU 3 communicates with the key interface 22,
Note octave data that represents the pitch of the sound you are trying to generate, and a key Φ that represents whether the key for that pitch is ON or OFF.
N-0FF signal is supplied and written to the internal latch.

The sample arithmetic unit 2o reads the data held by the tablet interface 21 and the key interface 22 according to internal predetermined timing, outputs address data to the parameter RΦM7 based on this data, and calculates its contents. is read out, a sample is generated by calculation, and is supplied to the interpolation calculator 23.

The interpolation calculator 23 performs an interpolation operation, for example, linear interpolation, on the middle of the envelope samples supplied one after another, and outputs smoothly changing envelope samples.

FIG. 3 shows examples of envelope signals and their sample values for explaining the sample calculation applied in the present invention. Figure 3(b) shows the envelope to be generated in dB scale, with the maximum value in odB.
, the minimum value is -80 dB.

The black dots (So, Sl, S2...) on this curve represent sample values sampled at time intervals Ti=T and 2T. Based on such data, if we take the dB scale of each sample value: the difference value on the eaves, we get (
ΔE0. ΔE1. ΔE2. ...).

Figure 3 (fc) shows the sample values shown by the black dots in Figure 3 (b) at dB13, from the digital scale to the linear scale values (LEo, LEl, LE228).
．． .

...) and connect each point with a dotted straight line. In the present invention, the dB difference values ΔEo, ΔE1 . ΔE2. . . . is stored in the parameter ROM 7. By sequentially reading and accumulating these dB difference values, a dB scale eaves envelope sample S is obtained. , Sl, S2. . . . is obtained. Next, the dB scale eaves envelope sample is transformed logarithmically to linearly to obtain the linear scale envelope sample LEO1LE1°L.
E2. obtain...

The sampling period of this envelope sample is the above-mentioned T, =T, 2T, etc., but this period is 0, which is larger than the period T8 of the musical tone sample that is finally output. To generate envelope samples one after another, samples LE0. LEl, L
E2. Linear interpolation is performed between two adjacent samples of . . . to obtain envelope samples having a shape as shown by the dotted line in FIG. 3(C) every period T80. 314, - is a block diagram of an embodiment of the present invention;
This implements the calculation procedure described in Figure 1. In FIG. 4, the readout calculation control unit 25 reads the timbre code, note octave data, and key 0NOFF data, and according to these data, calculates the dB difference value ΔEi representing the envelope signal corresponding to the timbre code and note octave data. It sequentially generates the address AD of the address to be stored, and then sends the read command signal R.
Output D, parameter ROM7! The 1 ldB difference value ΔE is read out to the output terminal Do and stored in the latch 3o.

The adder/subtractor 32 adds ΔEi and zero to produce ΔEi, which is supplied to one input of the adder/subtractor 32.
The output of 3 is stored in the register 34 and the logarithm -
The output of the register 34 is supplied to the other input of the zero adder/subtractor 33 which is supplied to the linear converter 35 . Register 34 is a one word latch. Adder/subtractor 33 and register 3
4 means that the 0 logarithm-linear 15-page converter 35, which acts as an accumulator that accumulates ΔE1 and outputs the following, is a readout function that generates a linearized output code LEn for an input code Sn. Dedicated memory (RO
M). If the input is 8 bits and the output is 16 bits, the ROM will be 256×16=4096 bits. Envelope sample LEn is applied to register 36 and delayed by one sample time.

Then, in the subtracter 37, ΔLEn=LEn−L
En.

is calculated. The output ΔLEn of the subtracter 37 is shifted downward by a predetermined number of bits in the bit shift register 38 and is supplied to one input of the adder/subtracter 39 . The output of the adder/subtractor 39 is delayed by the tone sample period Tll in the shift register 4o and then supplied to the other input of the adder/subtractor 39.

The bit shift register 38 is a kind of divider, and δ, =
(LEn-LEn, )/(Tn, /T8) ・・−
...-(2) (n-213r' r...)
Execute.

T,,/T8=2'・・・・・・・・・・・・・・・
two··!・・・・・・・・・・・・・・・・・・(To)
), shifting by P bits corresponds to division.

δ. If you accumulate 2P times, ΔLEn=LEn-LEn-1(n=2,3,4...
Song) becomes (4). Therefore, it is possible to linearly interpolate between LEn and LEn in a time of ``n-1.The interpolated envelope samples are ``n, j=''n-1+j (LEn-LEn-1
)/(Tn, , -1/r, )Sn, LE, , ΔL
The generation of En, δU is executed in Ti cycles. Therefore, the memories in the latch 30i register 34, 36 and bit shift register 38 are updated by outputting latch pulses every T from the read operation control unit 26. be done. The number of shift bits P of the bit shift register 38 is determined by the read operation control unit 2.
Output code ΔLE shifted in multiple ways by the code representing P corresponding to T, /T, output from 5
n.

dLEn/2. ΔLEn/22. . . . and its output is latched.

Since the contents of the register 40 are updated every cycle T, a latch pulse is supplied to the read 17 page arithmetic control unit 25 every cycle Ts.

Figure 5 shows simplified envelope data (Δ town) (i=1
, 2, 3. . . . is an example of N). The dB difference value ΔE· is placed at addresses 1 to N in the parameter ROM. The first address 0 is the release address RAD.
is stored. Now, for the sake of simplicity, Figure 3 (b
) where Ti (i = 1, 2, 3-, ...) are all equal. When the key ON/OFF signal input to the read calculation control unit 25 is pressed to '1#,' first, address AD indicating address 0 is output to ROMy, RD becomes "o", Read the release address RAD stored at address 0 and store it in an internal register. Next, increase AD by 1, and set RD to °'O" and write ΔE1 at address 1 to latch 3o. . Assuming that zero is stored in registers 30, 34, 36°38.40 as an initial state, 51=o
, LE1=o, ΔLE1=o, δ1=io. Therefore, the output of the adder/subtractor 33 becomes S2=ΔE1.

After this, calculations are performed according to the procedure described above.

18 pages The address AD increases by 1 each time 1 increases.

If you keep pressing the key, T will advance more and more, but Ti=T1
5, the envelope signal is changed to LFl by stopping the increment of address AD9, clearing the contents of bit shift register 3B to zero, and holding the previous accumulated value.
, will remain maintained.

After that, when the key 0NOFF signal becomes "0" and it is known that the key has been turned off, T,=71. Corresponding to ΔE1
0T16 is the release start point, and the address where the corresponding Δ"15 is stored is set as the release address RAD.

When the key 0NOFF signal becomes "o#" before "1=T15", the address AD is rewritten to RAD and output instead of being incremented by 1, and ΔE15 is read out as 0. After that, RAD+1, RAD+2°・・・・・・
and proceed through the release process - if you do this,
No matter what time the key is turned off, the camera can jump to the 19-page RAD at that time or at a predetermined time closest to that time, and immediately enter the release after the key is turned off. Moreover, since the dB difference value is used, the connections become smooth. For example, S12 to 81
．． If the data jumps to , there will be a discontinuity of about sdB, but if the data jumps from ΔE11 to ΔE15, after S12, 816 to S2o will be connected smoothly with a decrease in sdB compared to the original data. Therefore, no discontinuity occurs in the connection before and after the flight, no matter what the envelope shape. Furthermore, since it is on the dB scale, the dB change per unit time (slope on the dB scale) in the release process is maintained. Therefore, the way you hear the time change in the decay of a musical tone depends on when you turn the key off.
Even if it is F, it will be the same thing.

The read arithmetic control unit 25 that realizes the operations described above includes a register that controls the address AD, a register that stores the RAD, an arithmetic unit that increases, decreases, or changes the address;
It is realized using the same method as the sequential control of a minor computer, using the so-called ALU, a ROM containing a program to control these, and its decoder, and other element circuits used in a minor computer. be able to.

FIG. 6 shows envelope data consisting of one dB difference value. This group of data can be stored separately for each different octave of the keyboard, or even separately for each different note within one octave. By having separate data like this, you can use the optimal envelope for each key in each range, allowing you to create excellent tones in any range. For this purpose, the note octave data shown in FIG. 4 is received, the address AD of the parameter ROM is changed according to this data, and data in the same type of format is stored at addresses different from addresses 0 to N in FIG. You can also select.

In the data format of FIG. 6, T is constant, but since the envelope generally changes rapidly at the rise of a musical tone, it is better to reduce Ti and increase the number of sample points. In order to be able to change the size of T depending on i, a data format as shown in FIG. 6 may be used. In FIG. 6, the release address 21 page RAD is at address 0, the Nithrop data 5LoPE is at address 1, and the point interval PI and point number PN are at address 2.

After that, ΔΣ and ΔE6 are stored at addresses 3 to 7.

Next, PI and PN, followed by ΔE6 to ΔE14,
The PI is stored in the RAD address as the last group.
and PN, followed by ΔE15 to Δ"19. RAD is as described in FIG. PI is a code that indicates the interval T between sample points, and PN is a code that indicates how many points the sample point interval T lasts.For the envelope shown in Fig. 3(b), The PI at address 2 specifies T1 and the PN is 5. At address 8, the PI is T6 (=2T1) and the PN is 9. At the release address RAD, the PI specifies T and the PN is 6. .

The procedure for reading out the parameter ROM in the data format shown in FIG. 6 in the embodiment shown in FIG. 4 will be explained. When the key reaches 6N, the RAD at address 0 is first stored in the RAD register. Next, the slope data 5LOPE22 vanes are stored in the read register 31 (FIG. 4).

After that, PI and PN are read out and stored in the PI register and PN register. Next, the data is stored in the ΔE1'ffl output register 3o starting from address 3. Then, subtract PN by 1. P
A bit shift code corresponding to T and /TB determined according to I is supplied to the bit shift register 38. In this way, the enveloping line sample LE1. between the section T1.
, is calculated. T.

Immediately before the end of the process, read ΔE2 from address 4 and register 30.
, and decrement PN by 1.・When you advance to address 7 in this way, PN=o, so you can see that PI and PN are stored next.

Therefore, address 8 is read and stored in the PI register and PN register. Then, ΔE6 is read out and stored in the register 30, and the register 31 is cleared.

Furthermore, find PN-1 and follow the PI code to T6 (
=2T, ) is supplied to the bit shift register 38. Since the PN becomes zero when it reaches the RAD-1 address, it can be seen that the PI and PN are stored next on page 23. Then, by performing the same operation as at address 8, the release process begins. Since it can be determined that RAD is in the release process by comparing the data in the RAD register with the current address, after reading ΔE19, the same ΔE19 can be read out subsequently.

If the key continues to be ON, it is sufficient to stop in front of the RAD address. If the key turns OFF before the RAD, it is sufficient to rewrite the contents of the AD register to RAD and enter the release process.

If 5LOPE data is provided as shown in Figure 6, ΔE1~
The data length at the rising edge of ΔE5 can be reduced,
Data can be compressed. The 5LOP data shows the average slope of the envelope shape of FIG. 3(b), and ΔE1 to ΔE5 are deviations from the slope. In the release process, reverse slope data, that is, negative slope data may be provided to RAD.
゛□ Parameter R of the data format in Figure 6? The read operation control device 25 for reading 5M is internally equipped with a PI register, a PN register, an AD register, a RAD register, etc. as shown in FIG. 7, and further includes an ALU (arithmetic logic unit),
It can be constructed using well-known circuits for microcomputers, such as a ROM, a program counter, and an instruction decoder for instructing these operating procedures. Further, it can be configured using a well-known circuit of a microcomputer. Furthermore, it is also possible to construct the system using the microcomputer itself.

In the above explanation, the case where one type of envelope signal is generated has been explained. Since musical tones generally consist of multiple frequency components, multiple envelope signals are required. Furthermore, when producing not only a single melody but also multiple notes, a separate envelope signal is required for each note. To this end, in the embodiment of FIG.
0 is provided with a plurality of registers, including an adder/subtractor 33.39, a subtracter 37. Logarithmic-linear converter 35. The bit shift register 38 may be used in a time-division multiplexed manner. The registers 34, 36, and 40 may be shift registers having the same number of stages as the number of multiplexers. The operation procedure of the readout calculation control unit 26 may also be configured to perform time-division operation in accordance with the number of multiplexed units.

FIG. 8 shows that the sample arithmetic unit of the envelope signal generator of the present invention explained in FIG. This is an embodiment in which the data is transmitted and the calculation procedure is executed under program control.

In Figure 8, 5o is the address controller o'-
Address code ADR from CPU3 in the figure.

Data DB, input/output command signal l0RQ, write command signal W
In response to R, the address AD is sent to the parameter ROM 7, and data specified by the address AD is read from the parameter ROMy from the data bus RDB. A timing pulse generator (TPG) 51 generates internally necessary pulse signals from the master clock frequency.

T-PGsl can be constructed using a clock oscillator, a counter, and a gate. Reference numeral 52 denotes a sequencer, which processes addresses, write command signals, read command signals, etc., which will be described later.
, - An RO that stores the procedure for outputting according to the calculation procedure.
It is M. Reference numeral 63 denotes an instruction decoder which inputs the instruction code output from the sequencer 62 and outputs an address code, a write command signal, and a read command signal.

64Fi, in the tremolo modulation register, the difference value of the periodic fluctuation data that causes tremolo modulation is sent to the data bus RD.
The reception is input from B and stored at the rising edge of WRl. ΦC1 is”
When OCR is 1', the contents are output to the A path. The slope register 55 receives slope data from the data bus RDB and stores it at the rising edge of WR2. When OCR is 1', the contents are output to the A bus. An address code is given that specifies one of 120 registers in register 55. 66 is a dB difference register with 12
It consists of 0 data registers, one of which is designated by ADl. Then, at the rising edge of WR3, the dB difference data is received from the data bus RDB and stored.
When C3 is “1”, the contents are output to the B bus.
67 is the Empeo-27 page preregister, which consists of 120 data registers, one of which is specified by address code AD2, and C
Data Sn supplied from the bus is stored at the rising edge of WB2. When OC4 is 1''', envelope sample data Sn on the dB scale is output to the A bus. 58 is a logarithm-to-linear converter that latches the data Sn supplied from the C bus at the rising edge of WRs, and converts it to the logarithm-linear converter. The linearly converted envelope sample LEn is output to the A bus when 0Cts is 1'.

59 is an envelope sample register consisting of 120 registers, one of which is specified by the address code ADs, and the envelope sample LEn supplied from the C bus is
It is latched at the rising edge of Ra, and is output to the B bus when oC6 is “1”. 6o is a working register (WREG).
), one of them is selected by the address code ADa, and the data supplied from the C bus is stored internally at the rising edge of WB7.
When C7A is 1°°, it outputs its contents to the A bus, and Φ
When C7B is "1", the contents are output to the B bus. 61 is an adder/subtracter that operates on each input data of the A bus and B bus and outputs it to the C bus. The selection of addition/subtraction is determined by instruction decoding. It is specified by the device 63.

62 is a differential envelope data register that stores ΔLEn. It consists of 20 registers, one of which is selected by address code AD4, and stores ΔLEn output from adder/subtractor 61 at the rising edge of WRlo. 6
Reference numeral 3 denotes a differential envelope data register, which is composed of 120 data registers, one of which is specified by address data ADs, and input data is stored when WRa rises and is output when 7508 is "1". 64 is a shift gate for shifting input data by a predetermined number of bits. The number of bits to be shifted is specified by the 5HIFT signal. The shifted signal corresponds to the data δU. 66 is an adder/subtracter for accumulation. 66 is a register that receives and stores the output of the adder/subtractor 66, and is made up of 120 registers. One of them is specified by address data ADs, stored at the rising edge of WB9, and 0C
Output when page 929 is II 11+.

In the embodiment shown in FIG.
160 of 20X8=160 so that the notes occur at the same time.
It is designed to perform heavy time division multiplexing operations. The number of the 8 tones is represented by 1 to 8, and the number of the 20 tones is represented by I = 1 to 20.

The calculation procedure will be explained next. Instead of the subscript n used earlier, i is used here.

WREG 4-8LOPE (K, I)
1ΔEi (K, I) (e) WREG , -
WREG +5i (K, I) ke)Si+
, (K, I) ←WREG 1ΔAMi
(K, I) (a) LBIIN, -Vll'
REG +ΔAM, (K, I) (9
)ΔLE, 1(K, I) ←WREQ −L
Ei (K, I) (1o)LE,, (K, I) ←
LOG/I, IN - (11) First, according to equation (6), 5LOPE (K, I) is read from the slope register 55, and the dB difference data ΔEi (K, I) is
The contents of the working register 60 and the contents of the envelope register 57, S, (K, ) are read out, added, and stored in the working register 60.

Next, according to equation (8), the contents of the working register 6o and the contents ΔAM of the tremolo modulation register 54, (K
, I) and are added to obtain a new envelope sample Si+, (K, I), which is stored in the envelope register 57 at address (K, I). Also(@
Write the same answer to the input latch of the log-linear converter 58 according to the formula. Next, read the output of the log-linear converter 58 and the output of the envelope sample register 69 according to formula (1o), and The difference ΔLE1+, (K, I) is taken and written to address (I) of the differential envelope data register 62. Next, LE,1 (K, I), which is the output of the logarithmic-linear converter 58, is written to address (K, I) of the envelope sample register 59 according to equation (11). In the above explanation and formulas (6) to (11), (K, I)
indicates one of the registers of 8×20=160 words. Ol is a positive integer and is a sample number that starts at 1 after detecting the key 5N and increases sequentially in 31 pages.

To execute the above calculation procedure, address codes AD1 to AD4. Write command signal WR4~7゜10, read command signal OC1~6.7A, 7B (6)~(11)
The equation is first run for ~1, I=1~2°, then ~2. . . , 8, then in - order, and then back to the beginning, so that i can be incremented one by one.

The differential envelope data register 62 has 20 of I=1 to 20.
Consists of word registers. Therefore, I=1~2o
After finding the new 20 ΔLE,,(K, I), then this new ΔLE,,1(K,I) is,
The registers at the corresponding 20 addresses inside the differential envelope data register 63 are transferred. The speed of this transfer must match the reading speed of the differential envelope data register 63, that is, the updating speed of the address code AD5. Further, this speed corresponds to the period in which the envelope data LE is finally output. The address AD5 of the differential envelope data register 63 always changes cyclically with a period of 160, and ΔLE, (K, I) is output one after another according to (K, I) determined by the address code AD5. The shift gate 64 has ΔLEi (K, I
) is shifted by a predetermined number of bits, δi(K, I) is output, and is accumulated by an adder/subtractor 65 and a register 66.

FIG. 9 is an example of data of the parameter ROMy used in the embodiment of FIG. 8. Address 0 indicates the basic nature of the sound, such as vercussive or normal envelope. It consists of a 5DE code and a harmonic restriction code that specifies the maximum number of envelopes to output out of the 20 envelopes of knees 1 to 2o. Address 1 is the release address mentioned above. Addresses 2-21 are
This is a table of data specifying the number of envelope data to be used in each time slot corresponding to 20 envelope signals. Addresses 22 to 41 are 20 pieces of slope data. Address 42 is the point interval PI and point number PN of the rising portion. 43-62
, 63-82, ・, 103-122 are 20 each
Each page is PNN group dB33 page difference data. These are the PI and PN at address 12323. 124-143, 144-163, 164-18
3. ......, 204 to 223 are 20 d each
B is differential data. From then on, the arrangement is the same. Multiple sets of parameters with such a configuration are prepared. Each set is provided corresponding to a specific range of a specific tone.

Address code, data, and control signals l0RQ, W are sent from the CPU 3 (FIG. 1) to the address controller 5o in FIG.
When R is supplied, and the tone code, note octave data, and key ΦN0FF data are supplied, based on these data, it corresponds to the note octave in the specified tone area in the nomura meter ROM. You can find the start address of the area containing the parameter set. (This start address may be given directly from cp'os.) This start address is supplied via the parameter ROM head address bus AD, and the data is
It is read from the DB and stored in the internal register of the address controller 6o. The address is then advanced 34 pages and the data from addresses 0 to 21 are taken in. Next, the slope data is read from addresses 22 to 41 and stored in the slope data register 55. Next 42
The PI and PN of the address are stored in a predetermined register in the address controller 6o.

Next, the dB difference data ΔE1 (K, I
) is stored in the dB difference register 66. Since the above data has been read, the calculations of equations (6) to (11) can be performed using the procedure described above. Mode, harmonic limit code, release address, time slot/envelope number table, PI, P
Since M and the like are required for each channel, registers for storing them are provided inside the address controller.

In FIG. 9, the harmonic limiting code ``M'' is a number from 1 to 20, and specifies that the envelope sample exceeds this number M and is 20 or less, and outputs zero. For this, (M
+1) to 2o, by applying a large negative number as ΔEi, a large negative number is set as ΔLEi, and by keeping the shift amount small, δi is set to a large negative number. By providing 36 pages, the cumulative value in the adder/subtractor 66 becomes a negative number.

On the other hand, in general, envelope samples may typically be zero or positive values. Therefore, when the calculation result of the adder/subtractor 66 is negative,
A control line 68 is provided to detect this and forcibly output zero. In this way, unnecessary envelope samples can be reduced to zero.

In FIG. 9, the time slot/envelope number table shows the dB difference data ΔE of the envelope of any time slot of time slots 1 to 20, (K, I), and other data ΔE with different I, ( When substituting K, I') (, It ~ engineering), it provides a correspondence table between engineering and I'. If we do this, ΔE, (K, I) becomes ■=
It is not necessary to have all of 1 to 2o, prepare ■ = 1 to 1o, and for I = 11 to 2o, select an appropriate one from I = + to 1o, or one with a similar shape. You can do it like this. For this purpose, in the calculation of ■=11 to 2o, an address conversion operation such as outputting the address where ΔE and (K, I) corresponding to ■=1 to 10 are stored may be performed. Such address conversion can be realized by operations similar to those of relative addresses and indirect addresses in microcomputers and minicomputers.

The data supplied to the tremolo modulation register 64 in FIG. 8 is a differential PCM data of periodically fluctuating waveforms.

- It is sufficient to read out the data stored in the ROM.

As described above, by using the sample arithmetic unit having the microprocessor structure shown in FIG. 8, a predetermined arithmetic operation can be performed by a program using a group of registers connected to a pass line, an adder/subtractor, and the like.

The procedure of formulas (6) to (11) is one example, and various embodiments can be constructed by omitting some data or changing the procedure.

Address controller 50. Timing pulse generator tS1. :Sequencer52. Since the instruction decoder 53 is already known in various microprocessors, its details will be omitted.

In the above explanation, if the key remains ON, a certain envelope sample will continue to be output before the 37 page read address RAD, but when it reaches RAD-1, it will be sent to an even earlier address after that. For example, as shown in FIG. 3(b), 86 to S1. The address may be manipulated repeatedly. Also, 86-S1. Instead of repeating S16 to S6 to S
It may be possible to jump to any address between 16 and 16. Such address manipulation can be realized by adding or subtracting a random code output from a pseudo-random sequence generator to or from the address.

As part of the release process, musical instruments require damping or high-speed minting. When such a request occurs, by setting the dB difference data to a large negative value, rapid attenuation can be achieved through accumulation. For this purpose, it is sufficient to create a procedure for writing a predetermined value as ΔE.

FIG. 10 is a diagram showing the timing of the embodiment of FIG. 8. Figure 10 (Ali) shows a sample 38 basis arrangement of a sine wave waveform, and the sampling period/d2oμB of one sine wave waveform.
This is an enlarged view of the inside, and there are 8×20=160 time slots and 160 samples. Each sample is processed in steps of 12 Sns. Channel 1 (cHl) has 20 samples. C
The same applies to H2 to H8. On the other hand, FIG. 10(C) shows (A
) is the timing to calculate the differential envelope sample ΔLE, . Channel time slots CH8 having a unit of 160 μs are provided from 1 to 8. In CH31, ΔLE of channel 1, (1,
The calculation of I) is performed, and the corresponding channel calculations are performed in the following order. 160X8=1280μs (1,2
The calculation of ΔLE for each channel is repeated every 8 m5). FIG. 10(D) shows the inside of each channel time slot CH8, with CH31 enlarged on the side.

In CH31, there are processing time slots PTS 1 to 32 in units of 5 μs. P T 5(I).

On page 39 I=1 to 20, 2゜゛ in channel 1
The difference envelope samples ΔLE, (K, I) corresponding to the spectra (sinusoidal waveforms) are calculated. And P.T.S.
At 2.5 μB in the first half of 21, the calculated 2o ΔLE, (K, I) values are 1 as shown in Figure 10 (F).
Difference envelope register 63 (Figure 8) in 25ns increments
Transfer to. The timing of this transfer differs between CH31-8. For example, CH35 is executed in the latter half of PST24. FIG. 10(E) shows each processing time slot),
This is an enlarged version of the contents of PT81-2o. PT81
~2o are instruction time slots T81~6, respectively.
It is divided into six parts. Each is 830n
It is the length of s. In these instruction time slots ITS, the instructions in formulas (6) to (11) are executed.

Between PT81 and PT2o, calculations centering on the adder/subtractor 61 are performed in the embodiment of FIG.

1.:'... Between PT821 and PT32, ΔlIMi (
K, I ), 5LOPE(K, I ), ΔE, (K, I
) to write new data mainly to data bus D.
This is done via B.

In the shape of the envelope shown in Figure 3, in the case of a percussive type, if the attenuation is an exponential function, ΔE can be a constant value regardless of i in the attenuation process.
It is sufficient to have a kind of ΔF as a representative value in the attenuation process, and a large amount of data compression can be achieved.

As a conversion characteristic of the logarithmic-linear converter 36 in FIG. 4, when the input Sn is small, for example, the ROM may be configured so that zero is output as LEn for an input code corresponding to -5 odB or less. Good 0 As described above, according to the present invention, the following excellent effects can be obtained.

(1) Since envelope samples are stored as digital data and interpolation calculations are performed based on this, smoothly continuous envelope signal data can be obtained based on sparse envelope samples.

(2) Since the differential PCM data is taken on the dB display scale of the envelope sample, it is exponential 41.

The attenuation process can be realized by adding and subtracting dB differences and does not require a multiplier.

(a) Although the envelope sample Si on the dB scale is subjected to log-linear transformation, the ROM is smaller in size than when using a multiplier.
Since linear interpolation is performed after that, the time change of musical tones can be made into a smooth polygonal line without discontinuities.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an electronic musical instrument adopting the present invention;
3 is a block diagram showing the basic configuration of the present invention, FIG. 3 is a diagram showing the envelope signal waveform handled by the envelope signal generator of the present invention, FIG. 4 is a block diagram of the main part of the embodiment of the present invention, 5 and 6 are diagrams showing an example of the data format used in the present invention, FIG. 7 is a diagram showing an address calculation register, FIG. 8 is a block diagram of another embodiment of the present invention, and FIG. 9 is a diagram showing an example of the data format used in the present invention. is a diagram showing an example of the format of the data, and FIG. 10 is a diagram showing the timing chart. 7... Memory device, 20... Sample calculator, 23... Interpolation calculator. Figure 5 Figure 6 JP-A-58-200294 (14) Figure 8 54 RPB
A”wplact
665 App 5laPr(kr) Must-ADR” APIwrrzθt25〆8 CDNrhL
74E I (K, EJAI) + ^10 67 A, , St ('' and 1) TPGr, ('hIp
rlr) 2Wp4tlt4 52 'SEQ request・'''''''55n 7th figure Apt ρct 1 Kingia 1pa
Its Tsuru6tluS Ra 1E4 (#, I l l
E, -ptcoprp acs 69ct WRr lE? A.S.
ρt'1B AC+λ cancer Iρti'i7
1CIIWPEG

Claims (1)

[Scope of Claims] (1) A digital storage device that stores envelope signals of musical tones, a sample calculator that sequentially reads envelope signals from the storage device and generates envelope samples, and the envelope sample an interpolation calculator that performs an interpolation calculation between adjacent ones, wherein the data stored in the storage device is a value obtained by logarithmically converting the envelope signal. (2. In the statement of claim 1, the storage device stores slope data corresponding to the slope in at least one of the rising and falling sections of the envelope signal, and the sample arithmetic unit stores slope data corresponding to the slope data in at least one of the rising and falling sections of the envelope signal. An envelope signal generator capable of generating a steep envelope signal by adding a specified slope value to the envelope sample in the rising and falling sections. (3) Claim 1. In the description, the envelope signal generating device has a variable generation cycle of envelope 2-page line samples and a variable interpolation calculation interval according to the generation cycle. (4) In the description of claim 1, Key?5Fy to read the digital data stored in the device.
Sometimes an envelope signal generator that jumps to the address of the release process. (6) In the description of claim 1, the digital data stored in the storage device is read out so that the address of the data changes randomly when the key is kept ON for a long time. envelope signal generator. (6) The envelope signal generating device as set forth in claim 1, wherein the sample arithmetic unit and the interpolation arithmetic unit are time-divisionally operated to generate a plurality of envelope signals.