JPH0573031B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal processing device that generates a musical waveform signal according to a microprogram.

[Background of the invention]

2. Description of the Related Art Conventionally, devices that perform various types of signal processing using digital technology have been developed. For example, many signal processing devices such as electronic musical instruments obtain musical tone signals using digital circuits. However, in conventional electronic musical instruments, it is common to provide circuits that perform unique processing for each function.

That is, for example, in order to generate a musical waveform signal, there is an addressing circuit that specifies the address of the waveform, an envelope control circuit that adds an envelope to the waveform information read from the waveform memory, and a circuit that generates multiple musical tones at the same time. The accumulation circuit for accumulating the waveform information generated from each channel and then converting it into an analog signal had to be constructed separately.

According to such conventional techniques, in order to execute complicated waveform generation processing, the amount of hardware required is enormous, and moreover, it lacks versatility as it can only perform specialized processing.

For example, in the case of an electronic musical instrument as a signal processing device, processes such as generating a musical sound waveform and adding an envelope to generate a musical sound signal can be performed using the same arithmetic circuit instead of providing separate circuits. It has been proposed to repeatedly perform calculations according to pre-stored data and a microprogram, but in order to generate fast-changing musical tone signals, each of these processes must be performed in an extremely short time, and it is difficult to follow the changes in the musical tone signal. become unable.

On the other hand, among various processes for musical tone signals, for example, envelope addition processing changes more slowly than musical waveform generation processing, so it only needs to be executed once while other processes are executed multiple times. If the processing is executed at the same cycle as the tone waveform generation processing, there is a problem in that there will be a lot of unnecessary processing and the overall calculation time will become longer.

One possible solution to this problem is to use the envelope addition process and the musical waveform generation process as interrupt process routines, and to start their execution at interrupt clocks of different cycles. However, not only does the configuration for performing address control to read out such an interrupt processing routine become complicated, but also the processing executed by the main processing routine is interrupted every time an interrupt clock occurs.
There was a problem that the processing time varied depending on the interrupt cycle.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a signal processing device that has a simple hardware configuration and does not perform unnecessary processing.

[Key points of the invention]

The present invention has a program memory means that stores a microprogram in which a plurality of types of processing are arranged in a predetermined order and each process has a different repetition interval, and the program memory means is read out sequentially from the beginning in a time-sharing manner. By doing this, a series of arithmetic instructions corresponding to each process are output at different cycles,
The present invention is characterized in that this series of arithmetic instructions is executed by combining arithmetic operations of a plurality of arithmetic means.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of this embodiment. When the processing executed by the circuit of this embodiment is summarized by function and equivalently diagrammed, it becomes as shown in FIG. Therefore, before explaining the circuit configuration of this embodiment in detail, the functional block diagram of FIG. 2 will be explained.

<Functional Block> In FIG. 2, reference numeral 1 is an interface circuit with a microprocessor (not shown), and is connected to the microprocessor via a data bus DB.

Via this interface circuit 1, the pitch envelope generator 2 is given information FRR and FRS for generating pitch envelopes.

That is, the pitch envelope generator 2 is
A signal having a slope specified by the information FRR is gradually generated up to the final value, that is, the information FRS. Information on the current value is hereinafter referred to as FRC. Therefore, this pitch envelope generator 2 performs FRC←FRC+FRR in one operation, and when FRC matches or exceeds FRS, an interrupt signal is generated.
Generates INT and instructs the microprocessor mentioned above to set the next information FRR and FRS.

As a result, Pitzi Envelope Generator 2
generates a polygonal pitch envelope signal. FIG. 3 shows the situation.

3 in the figure is an adder that adds the output FRC of the pitch envelope generator 2 and the information FC. The information FC determines the center value of the pitch of the output musical tone. If the output FRC of the pitch envelope generator 2 is zero, a musical tone with the pitch specified by this FC will be generated steadily. Become.

Then, the output of this adder 3 is converted into an exponential
It is given to the ROM 4 and converted into frequency information FI. That is, the information FC or FRC is cent-proportional information, and is information specifying the actual frequency in hertz.

This index conversion ROM4 also contains noise information.
In the case of NOISE or FM modulation, output waveform information O, which will be described later, is input as information OSC.

Therefore, the frequency is further modulated by this information OSC. In addition, index conversion ROM4
After the two pieces of information given to are added internally,
Exponential conversion is performed.

The output frequency information FI is accumulated by the phase angle information generator 5 to become phase angle information PA specifying a phase angle address, and is supplied to the multiplier/divider 6.

The multiplier/divider 6 is further supplied with modulation information MOD from a harmonic suppression circuit 7. That is, information WRR and information are sent to the wave envelope generator 8 via the interface circuit 1.
WRS is given. This information WRR specifies the slope of the envelope signal, and the information WRS determines the final value. Then, from this wave envelope generator 8, information giving the current value
WRC outputs.

That is, the wave envelope generator 8
executes WRC←WRC+WRR in one operation. When the information WRC matches or exceeds WRS, the wave envelope generator 8 generates an interrupt signal INT, instructing the microprocessor to set the next information WRR and WRS. This state is shown in FIG.

The output information WRC of the wave envelope generator 8 is then given to the adder 9 together with the information GLW output from the glow generator 10. This growl generator 10 is
It has a low frequency signal oscillator (LFO) function,
A signal, ie, information GLW, whose frequency is sufficiently lower than that of the output musical tone is generated.

The output of the adder 9 basically determines the content rate of harmonic components of the waveform, that is, the degree to which the waveform is distorted. However, if the waveform is extremely distorted, aliasing distortion of the spectrum occurs. In order to prevent this, the harmonic suppression circuit 7 processes the upper limit using the frequency information FI, and uses the multiplier/divider 6 as the modulation information MOD. is giving to The details of this harmonic suppression circuit 7 are disclosed in Japanese Patent Application No. 58-251738 (title of invention: ``Harmonic Limiting System for Electronic Musical Sounds'').

Then, the multiplier/divider 6 divides the phase angle information PA by the modulation information MOD or multiplies both pieces of information to produce a modified address signal whose rate changes in one waveform period, or a modified address signal whose rate changes in one waveform period. Generates a modified address signal that specifies an address over a period of time, and the phase angle constant PA changes repeatedly at a constant rate. Information that distorts it or changes the rate at a rate greater than 1. Generates ANG.

In addition, this article discloses in detail a technique for generating a rectangular wave or a serpentine wave by accessing a memory that stores a cosine wave, for example, with a modified address signal whose rate is non-uniform in one waveform period. , Patent Application No. 57-221266 (invention title: "Waveform generation method") is a modified address signal that specifies an address with a period greater than 1 in one waveform period.
For example, by accessing a memory that stores cosine waves, a multi-cycle waveform is obtained, and the waveform is further multiplied by a window function (envelope signal) within one cycle to obtain a resonance effect.
There is a Japanese Patent Application No. 57-225582 (title of the invention: ``Method for generating musical sounds for electronic musical instruments'').

The information output from this multiplier/divider 6
ANG is applied to a wave generator 11 to generate waveform information W, which is sent to a multiplier 12.

In the normal state, the multiplier 12 multiplies the input waveform signal by 1 by the window function signal and outputs the result. In other words, the multiplier 12 outputs the result without changing the input signal in any way, as described above. At the time of the resonance effect, the input waveform signal is multiplied by a window function that repeatedly takes a predetermined waveform every cycle and is output. Furthermore, during the ring modulation effect, it has a function of multiplying the waveform signal of the channel by the final output waveform signal of another channel.

That is, in this multiplier 12, in addition to the waveform information W, the window function information F is transmitted to the phase angle information generator 5.
, the final waveform information O is selectively given from the multiplier 13.

In this multiplier 12, the waveform designation circuit 14 designates what kind of operation is to be performed, for example, what kind of window function information F is to be multiplied by the waveform information W. It also has a function of specifying an output waveform by changing the arithmetic format executed in the multiplier/divider 6, and outputs information WAV. In this waveform designation circuit 14, a signal from the microprocessor is passed through the interface circuit 1, and a signal for designating the tone color and effect is preset.

In FIG. 2, reference numeral 15 is an amplitude envelope generator, which generates an envelope signal that determines the volume. Information ARR and ARS are given from the microprocessor via the interface circuit 1.

That is, this amplitude envelope generator 15
is the above-mentioned Pitzi envelope generator 2
Similarly to the Wave Envelope Generator 8, ARC←ARC+ARR is executed in one operation. When the information ARC matches or exceeds the information ARS, the amplitude envelope generator 15 generates an interrupt signal INT, which instructs the microprocessor to set the information ARR and ARS. This state is shown in FIG.

And the amplitude envelope generator 15
sends information ARC to adder 16.

Information TRM is also supplied to this adder 16 from a tremology generator 17 . That is, like the growl generator 10 described above, this tremolo generator 17 has the function of a low frequency oscillator (LFO) that generates a low frequency signal, and produces a tremolo effect in which the amplitude level repeatedly changes over time. It has the function of generating signals to obtain signals.

Then, the adder 16 adds the information ARC and the information
After adding the TRM, it is applied to the exponent conversion ROM 18. This exponential conversion ROM 18 performs linear/exponential function conversion.
outputs the exponentially transformed envelope information, that is, the information ARE, and supplies it to the multiplier 13.

The multiplier 13 receives the output information WF of the multiplier 12,
Multiply by the output information ARE of the index conversion ROM 18,
The output information O is given to the accumulator 19 at the final stage.

That is, in the functional block circuit of the present embodiment described above, for example, time division processing of eight channels can be realized, and the phase angle information generator 5, the pitch envelope generator 2, the wave envelope generator 8, and the amplitude envelope generator Each of the generators 15 performs time-division operation for 8 channels, and the output waveform information O obtained as a result is a maximum of 8 channels.
There are channels, which are accumulated to produce the final output information.
The accumulator 19 generates OSM and takes it as the final output DOUT.

Now, FIG. 6 shows a summary of the signal changes of the main processes among the processes of the functional blocks shown in FIG.

That is, among the blocks shown in FIG. 2, all of them do not execute processing at the same frequency, but the processing rate of the pitch envelope generator 2 is
If the rate is 5K, the processing by the wave envelope generator 8 is at a 10K rate, the processing by the amplitude envelope generator 15 is at a 20K rate, and the phase angle information generator 5 and multiplier/divider 6 operate to generate a waveform. , multiplier 12,
13th class processing will be at 40K rate.

Therefore, when performing waveform generation processing eight times, amplitude envelope processing only needs to be performed four times, wave envelope processing twice, and pitch envelope processing once.

The embodiment shown in FIG. 1 has a circuit configuration that converts the processing of each of the functional blocks shown in FIG. 2 to perform calculations according to a microprogram as shown in FIG. This was realized by taking the following. Note that the explanation of FIG. 6 will be given later.

<Configuration of Example> The configuration shown in FIG. 1 will be described below. In FIG. 1, the circuit can be divided into a circuit group centered on the arithmetic processing circuits ALU1 and ALU2, and other circuit groups.

The arithmetic processing circuit ALU1 includes DRAM21 and
SRAM22 is connected. That is, this DRAM2
The contents of SRAM 22 are stored in latch 23, which is read on clock _φD , and the contents of SRAM 22 are stored in latch 24, which is read on clock _φS . The output of the latch 23 is input to the A input terminal of the arithmetic processing circuit ALU1 via the gate _g1 .
Furthermore, a bus AB is connected to the A input terminal of the arithmetic processing circuit ALU1 via a gate _g2 .

Furthermore, the output of the latch 24 is the arithmetic circuit ALU1.
It is input to the B input terminal of the circuit, and is also applied to the latch 25 which performs a read operation with the clock φ _C , and is supplied to the DRAM 21 through the gate g ³ and further through the gate g ⁴ , and also through the gates g ³ and g ⁵ . Connected to bus AB.

The output from the O output terminal of the arithmetic processing circuit ALU1 is applied via a gate ^g6 to a latch (Acc) ₂₆ which performs a read operation with a clock φA1. Also, latch 2
The output of 4 is also supplied to this latch ²⁶ via gate g7. This latch 26 is then connected to the bus AB.

Further, the output of the latch 23 is connected to the bus EB via the gate GJ. A gate GK is further connected to this bus EB, and is supplied with the output of a latch 27 which performs a read operation with a clock _φE2 .

Furthermore, the output of latch 27 is passed through gate ^g8 .
It is given to the input terminal of SRAM22. This SRAM
22, the bus OB is connected via gate ^g9 ,
This bus OB is also connected to the DRAM via gate ^g10 . And the above arithmetic processing circuit
When it is detected that the calculation result satisfies a predetermined condition, the ALU 1 outputs an interrupt signal INT, which is supplied to a microprocessor (not shown).

In accordance with the output of the exponent conversion ROM 28, the output of a multiplier (internally including an adder) 29 for performing interpolation processing is applied to the latch 27. The A input terminal of this multiplier 29 is either the output of the latch 23 applied via the gate ^g11 or the gate
The output of the bus AB given via ^g12 is supplied, and the B input of the multiplier 29 is supplied with the output of the bus PB.

Then, the output of the bus AB is connected to the gate ^g8 or the gate GK via the gate ^g13 and further via the gate ^g14 . Also, the gate
g ¹³ and g ¹⁴ are connected to gate g ¹⁵ .

The latch 26 output to the above bus AB is the latch 3
0 with the clock _φN . This latch 30
, phase angle information obtained by accumulating frequency information is latched, and its output is supplied to a gate 31 that performs gate control differently depending on the shape of the output waveform, and is also supplied to a comparator 32. Supplied. The output of this comparator 32 is given to the gate 31 and also to the gate 31.
3 is also supplied. That is, this gate 33 appropriately gate-controls the modulation information stored in the latch 34 by the clock φ _M , and outputs the modulation information to the multiplier/divider 3.
Supply to 5.

Multiplier/divider 35 divides the phase angle information provided via gate 31 by the modulation information provided via gate 33, or multiplies both information and stores the result in latch 36. This latch 36 performs a read operation on clock _φw1 .

The output of this latch 36 is then given to a ROM 37 that stores, for example, cosine wave information, accesses the waveform information, and sends a clock signal to a latch 39 via an interpolation multiplier (internally including an adder) 38. Stored in φw ₂ .

The output of latch 39 is applied via gate ^g16 to the X input of a multiplier 40 according to Bou's algorithm. Moreover, at the Y input terminal of this multiplier 40,
Latch 41 whose reading operation is performed at clock _φw3
The output of latch ²⁶ is applied through gate g17, and the output of latch 26 is applied through gate ^g18 , and the multiplication result is output from the Z input and read into latch 42 at clock _φw3 . The output of this latch 42 is supplied to and stored in latch 41 upon generation of clock _φw3 , and read into latch 43 at clock _φU .

The output of this latch 43 is the gate GL
In addition to being connected to the bus EB via the gate G ¹⁹
It is also connected to gates g ¹⁵ , g ¹³ , and g ¹⁴ via .

The output from the gate GL above is the arithmetic processing circuit
It is also supplied to the A input terminal of ALU2. The output of the PRAM 45 is applied via a latch 46 to the B input terminal of the arithmetic processing circuit ALU2. This latch 46 is provided with a read clock _φP . and,
The output of this latch 46 is also supplied to a latch 47 which performs a read operation on clock _.phi.L . The output of latch 47 is latched via gate ^g20 into latch 48 by clock _φTR . Further, the signal is read from the O output terminal of the arithmetic processing circuit ALU2 into the latch (Acc) 49 via the gate ^g20 using the clock _φA2 .

Further, the output of the noise generator 44 is connected to this latch 49 via a gate ^g21 , and further to a gate ^g22.
given through. Further, the signal outputted via the gate ^g20 is also inputted to the B input terminal of the arithmetic processing circuit ALU2 via the gate ^g23 .

The output of the latch 49 is then read into a latch 50 which provides a final output to a DA converter (not shown) at the clock φ ₀ , and is also applied to the bus PB and to the gate g ²⁴ . Also the gate
Also given to g ¹⁴ and g ¹⁹ .

The output of this latch 49 is gate g ²⁵
In addition to being supplied to the latch 48 via the gate
It is also stored in the PRAM 45 via ^g26 . Further, the contents stored in latch 48 via gate ^g27 are
Also given to gates g ²⁵ and g ²⁶ . And above
The signal supplied via the bus OB is supplied to the PRAM via the gate ^g28 .

Reference numeral 51 in FIG. 1 is an interface circuit, and data supplied from the microprocessor is outputted to the bus OB via gate ^g30 . The various control signals are also supplied to the instruction decoder 52. and,
In order to control the operation of the circuit shown in FIG. 1 in a predetermined order (sequence), the program counter 53
As will be described later, the upper counter of the program counter 53 takes 32 steps from 00 to 1F, and the basic arithmetic routine ends with the processing of these 32 steps.

This program counter 53 has a hexadecimal counter as a middle counter, and a counter with a rate twice that of the middle counter (28
There is a

The outputs of these program counters 53 are given to the ROM 54, where various microinstruction codes are read out and
The instruction decoder 52 is provided with instruction signals such as individual commands, opening/closing commands for gates ^g1 to ^g30 , GJ, GK, and GL, and address designation for the RAM.

In the circuit configuration shown in FIG. 1, the index conversion ROM 4 and the index conversion ROM 18 in the functional block diagram shown in FIG.
This corresponds to the ROM 28 and the multiplier 29. As will be described later, in FIG. 1, one circuit is used to realize both the functions of frequency conversion and envelope index conversion, thereby saving hardware.

Similarly, the multiplier/divider 6 in FIG. 2 corresponds to circuits 30 to 36 in FIG. 1, and the wave generator 11 in FIG. 2 corresponds to circuits 37 and 3 in FIG.
This corresponds to 8.39 circuits.

In FIG. 2, multiplier 12 and multiplier 13
However, in FIG. 1, the multiplier 40 based on the Booth's algorithm is configured to time-divisionally perform two operations for one waveform operation, and in this respect, the hardware is We are working to reduce this.

Other functional blocks are the arithmetic processing circuit ALU
1 and an arithmetic processing circuit ALU2, and their detailed correspondence will be explained later.

<Memory map> Next, SRAM22, DRAM21, PRAM45
The memory map will be explained with reference to FIGS. 7 to 9.

First of all, each SRAM22 has 8 channels (ch0~
ch7) 10 types of data are stored. For example 1
One type of data in one channel consists of 16 bits. Note that the other memories have similar bit configurations.

The SRAM 22 contains information FRR and FRS for generating a pitch envelope (already explained in Fig. 2; the same applies hereinafter), information WRR and WRS for generating a wave envelope, and information for generating an amplitude envelope. ARR and ARS are memorized. In addition, information FC specifying the center frequency, information WAV specifying the waveform shape, etc., frequency information FI,
The exponentially converted amplitude envelope information ARE is stored in this SRAM 22.

In addition, as shown in FIG. 8, the DRAM 21 has
Four types of data of 8 channels (ch0 to ch7) are stored. In other words, the current value information FRC of the pitch envelope, the current value information of the wave envelope
WRC, amplitude envelope current value information ARC, and phase angle information PA that specifies the phase angle are in this DRAM21.
is memorized. Note that each piece of information is as shown in FIG.

FIG. 9 shows the memory contents of PRAM45.
Information BL for channel harmonic suppression, 8
Modulation information MOD for channels, 4
Growl information GLW and tremolo information TRM for each channel are stored.

Note that when applying a growl effect or a tremolo effect, different effects are added to each of the two channels, so four types of information are sufficient.

In addition, there are 5 information OSCs for performing FM modulation or noise modulation, and odd channels
Channels 1, 3, 5, and 7 are basically not modulated, so the information OSC7 that is 0 is equal, and the even channels
ch0 is OSC0, ch2 is information OSC1, ch4 is information OSC
2, ch6 corresponds to information OSC3.

In addition, the cumulative information OSM of the final output is for one piece (OSM4), and the information α that determines the standard of the modulation level, which will be described later, is for two pieces (α5 is odd channel ch1,
Corresponds to 3, 5, 7, α6 is even channel
corresponding to ch0, 2, 4, 6), and these are
It is stored in PRAM45.

<Instruction> Next, these SRAM22, DRAM21,
Instructions output to perform various operations on the contents of PRAM 45 will be explained.

That is, these instructions are
First, instructions related to the arithmetic processing circuit ALU1 will be explained.

(a) D+S→Acc This means that the contents of the DRAM 21 are applied to the A input terminal of the arithmetic processing circuit ALU1 via the latch 23 and further through the gate ^g1 , and the contents of the SRAM 22 are applied to the A input terminal of the arithmetic processing circuit ALU1 via the latch 24. B input terminal, and after adding the contents of each input terminal,
It is set in the latch (Acc) 26 via the gate ^g6 , and specific instructions include FRC+FC→Acc, PA+FI→Acc.

(b) D±S→Acc This is to add and subtract the contents of DRAM 21, the contents of SRAM 22, and the sign (±) of SRAM 22, and store it in the latch 26. As a concrete instruction, has FRC+FRR→Acc WRC+WRR→Acc ARC+ARR→Acc.

(c) S→Acc This is to store the contents of the SRAM 22 in the latch 24, open the gate ^g7 , and store it in the latch 26. A specific instruction is ARE→Acc.

(d) D→Acc This transfers the contents of the DRAM 21 to the latch 26 in the same way, by opening the gates g ¹ and g ⁶ and transferring and storing them via the arithmetic processing circuit ALU 1. A specific instruction is PA→Acc.

(e) Acc-S→D This transfers the contents of the latch 26 to the arithmetic processing circuit ALU by opening the gate ^g2 and closing the gate ^g1 .
1, the contents of SRAM22 are applied to the B input of arithmetic processing circuit ALU1, and when the subtraction result matches or exceeds the contents of SRAM22, the contents of SRAM22 are latched φ _C and gate g ³
write to DRAM21 via gate ^g4 ,
Also, the subtraction result is latch 26, that is, the value of Acc.
If the value does not exceed the contents of SRAM22, Acc
Open gate g ⁵ and connect DRAM through gate g ⁴
Write to 21. This specific instruction is Acc-FRS→FRC Acc-WRS→WRC Acc-ARS→ARC, which is output when calculating each envelope.

(f) Acc→D This writes the contents of the latch 26 to the DRAM 21 via gates ^g5 and ^g4 , and specifically there is an instruction called Acc→PA.

The above are the main instructions regarding the arithmetic processing circuit ALU1. Next, the arithmetic processing circuit
I will explain the instructions for ALU2.

(g) P+GJ→Acc This transfers the contents of PRAM45 to latch 46, applies it to the B input terminal of arithmetic processing circuit ALU2, and opens gate GJ on bus EB.
Information from DRAM21 is applied to the A input terminal, and the addition result is latched (Acc) via gate ^g20 .
49. Specifically, there is an instruction such as GLW+GJ→Acc, and at that time, the gate
The information given via GJ is WRC.

(H) P+GK→Acc This similarly applies the contents of PRAM45 to the B input terminal of the arithmetic processing circuit ALU2, opens the gate GK, applies the information on the bus EB to the A input terminal, and outputs the result of the operation. It is stored in the latch 49.

Specifically, the command is α+GK→Acc, and at this time, what is given via gate GK is frequency information FI (output of latch 27).

(li) P+GL→Acc This converts the contents of PRAM45 to the arithmetic processing circuit.
At the same time, the gate GL is opened and the information on the bus EB is transferred to the arithmetic processing circuit ALU2.
2, the information on both sides is added and stored in the latch 49.

Specifically, the command is OSM+GL→Acc, and at this time, it is the waveform information of the latch 43 that opens the gate GL and inputs it.

(NU) P→Acc This latches the contents of PRAM45 (Acc).
This is done by opening gate ^g23 .

in particular, MOD→Acc TRM→Acc OSC→Acc There is an instruction.

(ru) Acc-P→TR This opens the gate ^g24 and applies the content Acc of the latch 49 to the A input terminal of the arithmetic processing circuit ALU2,
The contents of PRAM45 are given to the B input terminal of the arithmetic processing circuit ALU2, and both pieces of information are subtracted, and the value of Acc is
If the value of PRAM 45 is not exceeded, the value Acc is stored in latch 48, and if not, the value of PRAM 45 is stored in latch 48.

At that time, if the value of latch 49 is to be transferred to latch 48, gate ^g25 is opened, and if the content of latch 46 is to be transferred to latch 48,
The signal is transferred once to latch 47, gate ^g29 is opened, and the signal is transferred. A specific instruction for this is Acc-BL→TR.

(w) TR→P This is to transfer the contents of the latch 48 to the PRAM 45, and is performed by opening the gates ^g27 and ^g26 .
A specific instruction for this is TR→MOD.

(W) Acc→P This is to store the contents of the latch 49 in the PRAM 45, and transfer the contents of the latch 49 by opening the gate ^g26 . This specific instruction is Acc→OSM Acc→BL.

(f) GL→Acc This opens gate GL (gate g ²¹ ) and inputs the contents of bus EB to latch 49 via gate g ²² . Specifically, the waveform information stored in latch 43 or the noise output of noise generator 44 is stored in latch 49.

(Y) Acc→P This is to write the contents of the latch 49 to the PRAM 45, and the contents of the latch 49 are written to the PRAM 45 through the gates g ²⁵ and g ²⁶ .
Supply to 5. Specifically, there is an instruction called Acc→OSC.

Next, the processing of each rate will be explained with reference to FIG.

<5K rate calculation> First, when calculating the pitch envelope,
For each 5K rate, the above-mentioned arithmetic processing circuit
In ALU1, information FRC of DRAM21 and SRAM
22 information FRR is added and subtracted, and the result is stored in the register 26 (FRC+FRR→Acc).

Then, it is determined whether this calculation result information exceeds the information FRS of the SRAM 22, and if it is less than that, this information FRC is stored in the DRAM 21. If it is detected that the information FRS has been exceeded by the above judgment, it means that the calculation of the polyline of one phase of the pitch envelope has been completed, and the arithmetic processing circuit ALU1 generates the interrupt signal INT and outputs the information FRS. It is stored in the DRAM 21 as information FRC (Acc-FRS→FRC).

Then, in the arithmetic processing circuit ALU1,
DRAM21 information FRC and SRAM22 information
FC and stored in latch 26.

The output of latch 26 is then applied to the A input terminal of multiplier 29 via bus AB. At the same time, on the side of the arithmetic processing circuit ALU2, the PRAM45
The information OSC transferred from the latch 49 to the latch 49 (OSC→Acc) is applied to the B input terminal of the multiplier 29 via the bus PB.

After the two pieces of information are added, they are exponentially converted using an exponential conversion ROM 28, and a multiplier 29 executes interpolation multiplication to increase the calculation accuracy, and the calculation result, that is, the frequency information FI. ,
It is stored in SRAM22 through gate ^g8 (SRAM _WRITE ), and is also stored on the bus through gate GK.
It is applied to the A input terminal of the arithmetic processing circuit ALU2 via EB.

At the same time, the information α stored in the PRAM 45 is also applied to the B input terminal of the arithmetic processing circuit ALU2, and the addition result is stored in the latch 49 (α+GK→Acc). And then latch 4
The output of No. 9 is stored in the PRAM 45 as harmonic suppression information BL.

Through the above processing, it is possible to generate pitch envelope information, generate frequency information FI in accordance with the pitch envelope information, and obtain harmonic suppression information BL in accordance with the frequency information FI.

<10K rate calculation> In the calculation processing circuit ALU1, the information WRC stored in the DRAM 21 and the information WRR stored in the SRAM 22 are added and set in the latch 26 (WRC+WRR→Acc). Next, it is determined whether the output Acc of this latch 26 exceeds the WRS stored in the SRAM 22, and if it does not, the contents of the latch 26 are transferred to the DRAM 21.
If it exceeds the WRC, an interrupt signal is generated from the arithmetic processing circuit ALU1, and the information WRS is sent to the DRAM21 as the information WRC.
(Acc-WRS→WRC).

In addition, the information WRC of DRAM21 above is the gate
Arithmetic processing circuit via GJ and bus EB
It is applied to the A input terminal of ALU2, and at the same time PRAM4
5 to the information GLW supplied to the B input terminal,
Store it in Latch 49 (GLW+GJ→Acc).

And next, the output Acc of this latch 49,
A comparison is made with the information BL stored in the PRAM 45, and if the information Acc does not exceed the information BL, the information Acc is set to the latch 48, and if the information Acc exceeds the information BL, the information Set BL to latch 48 (Acc-BL→TR). Then, the contents of this latch 48 are transferred and stored in the PRAM 45 as information MOD.

Through the above processing, the wave envelope calculation is executed, the result is compared with the harmonic limit information BL, and the appropriate value information is used as the modulation information.
It will be calculated as MOD.

<20K rate calculation> In the calculation processing circuit ALU1, the output of DRAM21
ARC and the output ARR of the SRAM 22 are added and subtracted and stored in the latch 26 (ARC+ARR→
Acc). Then, the output of this latch 26,
A comparison judgment is made with the output ARS of the SRAM 22, and if the information Acc does not exceed the information ARS,
When the information Acc is stored in the DRAM 21 as the information ARC and exceeds the information ARS, it means that the phase of a certain envelope has ended, and the arithmetic processing circuit ALU1 generates an interrupt signal INT.
And the information ARS is stored in the DRAM 21 as the information ARC (Acc-ARS→ARC).

Further, the information ARC is applied to the A input terminal of the multiplier 29. On the arithmetic processing circuit ALU2 side,
After the content TRM of PRAM45 is transferred to the latch 49 (TRM→Acc), it is transferred to the multiplier 2 via the bus PB.
9's B input terminal.

In the multiplier 29, the information input to the A input terminal,
After adding the information input to the B input terminal, execute processing for exponent conversion, and convert the output ARE to
Store it in SRAM22 (SRAM _WRITE ).

In this way, an amplitude envelope is generated,
After adding it to the tremolo information, an exponential conversion is performed to generate envelope information ARE.

<40K rate calculation> In the calculation processing circuit ALU1, the contents of DRAM21
PA and the content FI of the SRAM 22 are added to generate new phase angle information PA, which is stored in the latch 26 (PA+FI→Acc), and the content is read again.
Input to DRAM21 (Acc→PA).

This phase angle information PA is then stored in latch 30 via bus AB. Also, PRAM4
5, information MOD is read out and stored in latch 49 (MOD→Acc), and then stored in latch 34 via bus PB.

Then, the multiplier/divider 35 and the gates 31 and 3
3. The comparator 32 performs the specified calculation on the phase angle information PA and modulation information MOD, and then sets it in the sending latch 36 as information ANG. The ROM 37 and the multiplier 38 operate according to this information ANG, and the waveform information W is stored in the latch 39.

And the contents of this latch 39 are gate g ¹⁶
At the same time, the information PA of the DRAM 21 is transferred to the latch 26 (PA→Acc) at the Y input terminal of the multiplier 40 via the bus AB. Information F is provided via gate ^g18 .

Then, from the Z output terminal of this multiplier 40, the result information WF obtained by multiplying the window function F and the waveform information W is
It is output and latched by latch 42, and further latched by latch 41.
After being latched, the signal is applied again to the X input terminal of the multiplier 40.

Then, this time, after the output ARE of the SRAM 22 is temporarily stored in the latch 26 (ARE→Acc), it is sent to the multiplier 4 via the bus AB and further via the gate ^g18 .
It is given to the Y input terminal of 0.

That is, envelope information is given to this Y input terminal, and this envelope information is multiplied by the waveform information of latch 41 in multiplier 40, and then transmitted through latches 42 and 43 and further through gate GL. It is applied to the A input terminal of the arithmetic processing circuit ALU2. At the same time, the contents of PRAM45 are added to OSM and stored in latch 49 (OSM+GL
→Acc).

And the contents of this latch 49 are again
At the same time as being stored in the PRAM 45 (Acc→OSM), for example, a clock φ ₀ is output every time all waveform calculations of 8 channels are completed, and the contents of the latch 49 are transferred to and stored in the latch 50, becoming the final output. .

Next, open the gate GL and store the waveform information on the bus EB, or open the gate ^g21 and store the noise information in the latch 49 (GL→Acc).
It is stored in the PRAM 45 as information OSC and used for FM modulation or noise modulation.

In this way, the waveform generation process is executed.
The above has explained the operation specifically limited to a single channel, but in reality, different processes for eight channels are performed in a time-sharing manner in a predetermined sequence. Refer to and explain.

As mentioned above, the program counter 53 is
The upper counter takes 32 steps (00 to 1F), the middle counter takes 14 steps between one step of the upper counter, and the lower counter takes the middle 1 of the counter of
The steps are divided into two and counted.

Then, while the upper counter advances by 4 steps,
Waveform information O ₀ to O ₇ of 8 channels (ch0 to ch7) is generated once (please refer to the gate GL column). Therefore, if you focus on one specific channel, the upper counter When it goes around,
New waveform generation processing is performed eight times.

This is a 40K rate calculation. Therefore, in a 20K rate calculation, one channel is processed four times while the upper counter completes one cycle, and in a 10K rate calculation, it is processed twice, and a 5K rate calculation is processed twice. The calculation is performed once.

In other words, when trying to generate the final waveform information, different weights are given to the frequency of pitch envelope generation processing, the frequency of wave envelope generation processing, and the frequency of amplitude envelope generation processing. .

Now, for example, the step speed of the upper counter is 1/5K (H ^Z )/32 = 6.25 x ^{10 -6} seconds (160KHz), and the step speed of the middle counter is 1/5K (H ^Z )/( 32×14) = 4.46×10 ^-7 seconds (2240K Hz), and the step speed of the lower counter is 1/5K (H ^Z )/(32×14×2) = 2.23×10 ^-7 seconds (4480KHz) becomes.

<5K rate calculation> First, the calculation for calculating the pitch envelope will be explained for channel O.

When the upper and middle counters (the same applies below) of the program counter 53 are 01 and B, the SRAM 22
information FRR ₀ (the subscript indicates channel 0, and the same applies hereinafter) from the DRAM21.
After reading FRC ₀ and setting them in latches 24 and 23, the arithmetic processing circuit ALU1 adds them and inputs them into latch 26.

Then, the output of the latch 26 and the SRAM 22
Information read from FRC ₀ and the above arithmetic processing circuit
Comparative detection is performed in ALU ₁ , and appropriate information is set in DRAM 21 based on the output.

Then, this information FRC ₀ is read out again from the DRAM 21 when the program counter 53 is 03, D, is added to the information FC ₀ read out from the SRAM 22 at the same time, and is set in the latch 26.

Further, the information OSC ₀ read out from the PRAM 45 at that time is set in the latch 46, transferred to the latch 49, and then supplied to the B input terminal of the multiplier 29.

Then, it is added together with the information supplied to the A input terminal, and the multiplier 29 performs exponential conversion to obtain frequency information.
FI becomes ₀ . Now, in this Figure 10, frequency information
Since the operation after FI ₀ is latched to the latch 27 is not shown, the operation after the frequency information FI ₇ of the other channel, that is, channel 7, is obtained when the program counter 53 is 00, 3 will be explained. do.

That is, this frequency information FI ₇ is applied to the A input terminal of the arithmetic processing circuit ALU2 via the gate GK, and at the same time, the information α ₅ read from the PRAM 45 is applied to the A input terminal of the arithmetic processing circuit ALU2.
is added and latched by the latch 49 when the clock φ _A2 is output, and then stored in a predetermined area of the PRAM 45 as harmonic suppression information BL.

In this way, pitch envelope information is generated. Note that the same applies to other channels.

<10K rate calculation> Next, the calculation for determining the wave envelope will be explained with reference to FIG. The calculation of channel O starts when the program counter 53 is 00,B, and information is input from the SRAM 22.
WRR ₀ is transferred to latch 24, information WRC ₀ from DRAM 21 is transferred to latch 23, and the resulting information is set in latch 26 at the output of clock φ _A1 .

Then, a comparison is made between the information of this latch 26 and the information WRS ₀ output from the SRAM 22.
As a result, appropriate information is set in the DRAM 21. Further, this information WRC ₀ is supplied to the A input terminal of the arithmetic processing circuit ALU2 via the gate GJ.

Then, the growl information GLW ₀ read from the PRAM 45 is locked in the latch 46 at the output of the clock _φP .
, and is applied to the B input terminal of the arithmetic processing circuit ALU2, where it is added. The result of the calculation is set in the latch 49, and the information BL read out from the PRAM 45 is then set in the latch 46.
The information is compared in the arithmetic processing circuit ALU2,
As a result, the appropriate information is loaded into latch 48, which then loads modulation information into PRAM 45.
It will be stored as MOD ₀ .

In addition, for channel 0, growl information
GLW ₀ corresponds, but growl information GLW ₂ corresponds to channel 1, growl information GLW ₁ corresponds to channel 2, growl information GLW 3 corresponds to channel ₃ , and similarly, growl information GLW 3 corresponds to channel 4. corresponds to growl information GLW ₀ , channel 5 corresponds to growl information GLW ₂ , channel 6 corresponds to growl information GLW ₁ , and channel 7 corresponds to growl information GLW ₃ .

The above description has been about channel 0, but the same procedure can be applied to other channels in a predetermined sequence.

<20K rate calculation> Next, regarding the calculation to obtain the amplitude envelope,
The explanation will focus on channel 0.

When the program counter 53 is 00,3
Information ARR ₀ is output from the SRAM 22, information RC ₀ is output from the DRAM 21, the operation result output is obtained from the arithmetic processing circuit ALU1, this result information is compared with the information ARS ₀ read out from the SRAM 22 again, and an appropriate Information is applied to the A input of multiplier 29.

Then, the tremolo information _TRM4 read from the PRAM 45 into the latch 46 at the clock _φP is stored in the latch 49 at the _{clock φA2} , and then applied to the B input terminal of the multiplier 29 via the bus PB.

Then, the amplitude envelope information _ARE0 , which has been exponentially converted from the multiplier 29, is set in the latch 27 at the clock _φE2 when the program counter 53 is 00, A (see the column EXP in FIG. 10).

And this output ARE ₀ is passed through gate g ⁸
It is set in SRAM22.

The above is for channel 0, but similar processing is performed for other channels in a predetermined sequence, so that envelope information
ARE ₁ to ARE ₇ are calculated.

<40K rate calculation> When the upper and middle counters of the program counter 53 are 00, 6~00, 8~00, 9, the SRAM2
Read information FI ₀ from 2 and latch 2 with clock _φS.
A predetermined instruction is generated from the instruction decoder 52 to set the number to 4.
At the same time, information is sent from DRAM21 to latch 23.
Enter PA ₀ .

Then, the information FI ₀ and PA ₀ are given to the arithmetic processing circuit ALU1, where the arithmetic operation PA ₀ +FI ₀ →Acc is performed, and this information is again set in the DRAM 21 and read into the latch 30 by the clock _φN . (See the φ _N column of the multiplier/divider MPY/DIV). At the same time, the latch 34 contains modulation information.
MOD ₀ is read from the PRAM 45 into the latch 46 at the clock φ _P (see the φ _P column of the arithmetic processing circuit ALU 2), and is then read into the latch 49 at the clock φ _A2 and then applied.

Also, at this time, information WAV ₀ that determines the timbre stored in the SRAM 22 is read out, and is also applied to this multiplier/divider 35 to designate an operation.

And according to the information MOD ₀ , PA ₀ , WAV ₀ ,
When the program counter 53 reaches 01.6, the information ANG ₀ is read into the latch 36 at the clock φ _W1 . Then, according to the contents of this latch 36, the ROM 37 and the multiplier 38 operate to generate waveform information.
Outputs W ₀ , then the program counter 53
01,E, it is read into the latch 39 by the clock _φW2 .

During normal performance, the output of the program counter 53 is given to the X input terminal of the multiplier 40 of the booth when it is 02, 3, and at the same time, the output of the program counter 53 is given to the Y input terminal ( (Refer to the φ _D and φ _A1 columns of the arithmetic processing circuit ALU1) Information PA ₀
is converted as appropriate and given as window function information F ₀ .

Then _, when the multiplication output WF 0 of this information W ₀ and F ₀ is 02 and 8 on the program counter 53, the multiplier 4
It outputs from 0 and is latched at clock φ _W3 .
2, then latched by the latch 43 and applied again to the X input terminal of the multiplier 40 (when the program counter 53 is 02, E).

At this time, at the Y input terminal of the multiplier 40,
The information ARE ₀ read from the SRAM 22 is given (see the columns φ _S and φ _A1 of the arithmetic processing circuit ALU 1), and the results of the operation are generated from the program counter 53 at 03 and 4. That is, in the multiplier 40, WF ₀ ×A ₀
=0 ₀ operation is executed and its output is clock φ _W3
It is stored in the latch 42 at the clock _φU , and output to the latch 43 at the clock φU.

Then, this output 0 ₀ is given to the arithmetic processing circuit ALU2 via the gate GL (refer to the GK column of the arithmetic processing circuit ALU2) and is used as the other input to provide information.
After OSM4 is given and the operation is performed, latch 4
9, and then stored in the PRAM 45, and when this arithmetic processing circuit ALU2 adds up the waveform information _O0 to _O7 for all channels, the final output information is latched in the latch 50 at the clock _φO . It will be output to the outside.

Then, the gate GL (or g ²¹ ) opens again,
Waveform information or noise information is input to the latch 49, which is input to the PRAM 45 as information OSC.

The waveform generation operation for channel 0 (ch0) has been described above, but the same applies to other channels. Further, in the above example, the operation during normal waveform generation processing has been described, but when ring modulation is added, the operation of the Booth multiplier 40 becomes different.

That is, the operation of channel 0 will be explained below again. During ring modulation, when the output of the program counter 53 is 02, 3, the multiplier 40
Waveform information W ₀ is given to the X input end of the , and output information O ₅ of channel 5 is given to the Y input end.

That is, this information _O5 is obtained by performing the calculation on channel 5, and the Booth multiplier 40 performs the calculation on the program counter 5.
It starts when 3 is 00,B. i.e. W ₅
×F ₅ =WF ₅ is first calculated, and the program counter 53 starts multiplying this information WF ₅ by the amplitude envelope information A ₅ from 01 and 8, and as a result, information O ₅ is set in the latch 41. Ru.

Then, this multiplication result W ₀ O ₅ and channel 0
is multiplied again by the multiplier ₄₀ and the multiplication result W ₀ A ₀ O ₅ is obtained in the latch 43 by the clock φ _U , which is the output waveform information.
Arithmetic processing circuit ALU ₂ through gate GL as O ₀
is supplied to

In this way, the waveform output _O5 of channel 5 is given to the waveform calculation of channel 0, thereby achieving a ring modulation effect. Similarly, channel 7 is combined for channel 2, channel 1 is combined for channel 4, and channel 3 is combined for channel 6, resulting in a total of up to 4 ring modulation sound effects. .

One embodiment of the present invention has been described above, but in this embodiment, a plurality of calculations with different calculation rates are executed in a predetermined sequence according to the output of the program counter 53. The circuit is capable of executing all of the multiple operations for waveform generation.

In addition, in the above embodiment, the pitch envelope,
Wave envelope and amplitude envelope respectively
Although the rates are 5K rate, 10K rate, and 20K rate, the ratios can be changed as appropriate.The point is to increase the rate of calculation of factors that should change frequently over time for waveform generation.

Furthermore, the computation for waveform generation does not necessarily have to be performed using the three types of envelopes described above.

In addition, the circuit configuration is an adder/subtractor (ALU)
The present invention is not limited to the circuit configuration of the above embodiment, as long as it performs calculations according to a predetermined sequence by combining a plurality of multipliers, multipliers, dividers, etc.

〔Effect of the invention〕

As described above, according to the present invention, the program memory means stores a microprogram in which a plurality of types of processing are arranged in a predetermined order and each processing is arranged at different repetition intervals, and the program memory means is programmed from the beginning. By repeatedly accessing data in a sequential time-sharing manner, a series of arithmetic instructions corresponding to each process are executed at different cycles, so processing of slowly changing data is performed every time other processes are executed multiple times. Since the processing is executed only once per cycle, unnecessary processing is not executed, and the overall processing time is shortened. Furthermore, since the program memory means only needs to be accessed sequentially from the beginning, there is no need for a complicated hardware configuration such as conventional interrupt control.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a diagram showing its circuit configuration, FIG. 2 is a diagram showing its functional blocks, FIG. 3 is a diagram showing a pitch envelope, and FIG. 4 is a diagram showing a wave envelope. 5 shows the amplitude envelope, FIG. 6 shows the operation of the same embodiment, FIG. 7 shows the contents of the SRAM in FIG. 1, and FIG. 8 shows the contents of the SRAM in FIG. FIG. 9 is a diagram showing the contents of the PRAM in FIG. 1, and FIG. 10 is a diagram showing the time chart of the same embodiment. ALU1, ALU2... Arithmetic processing circuit, 21...
DRAM, 22...SRAM, 28...exponential conversion
ROM, 29...multiplier, 35...multiplier/divider,
38... Multiplier, 40... Multiplier, 45...
PRAM, 52...Instruction decoder,
53...Program counter, 54...ROM.

Claims (1)

[Scope of Claims] 1. Program memory means storing a microprogram in which a plurality of types of processing are arranged in a predetermined order and each processing at different repetition intervals; an access means that repeatedly accesses the microprogram in a predetermined order from the access means; an instruction decoder means that uses the access means to decode the microprogram and sequentially sends out a series of arithmetic instructions for performing each of the plurality of processes; a data memory means that stores data necessary for a plurality of processes; and a data memory means that performs corresponding operations on the data from the data memory means in response to a series of operation instructions based on each process from the instruction decoder means. A signal processing device comprising: a plurality of arithmetic means for execution;