JP2649910B2 - Tone signal generation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a tone signal by a predetermined operation method such as a frequency modulation operation or an amplitude modulation operation. The present invention relates to a method in which units are connected in a predetermined manner, and a tone signal is generated according to the connection manner.

[Conventional technology]

A method of synthesizing a musical tone of a desired timbre by frequency modulation in an audio frequency band is disclosed in Japanese Patent Application Laid-Open No. 50-126406. In such a method, in order to obtain a tone signal having sufficient harmonic components, it is necessary to introduce a complex modulation equation such as multiplex or polynomial.
The device scale becomes large. In view of this point, a method for synthesizing a tone signal having many overtone components with a simple configuration is disclosed in Japanese Patent Application Laid-Open No. 55-7773 or 55-77.
No. 34. In this case, the output of the modulation operation circuit is fed back to its own modulation signal input side, or the outputs of a plurality of modulation operation circuits are sequentially fed to the next-stage modulation signal input to form a ring-shaped feedback loop as a whole. Is shown.

[Problems to be solved by the invention]

However, the above-described conventional method has a limitation that a feedback circuit is formed only in its own modulation operation circuit, or a feedback circuit is formed only in a ring shape.
Therefore, the number of harmonic components obtained is limited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to provide a tone signal generating method capable of generating a tone signal containing a large number of harmonic components with a simple configuration.

[Means for solving the problem]

According to the present invention, a plurality of operation units for performing a predetermined waveform generation operation using a phase signal or a waveform signal applied to one or a plurality of inputs as a parameter are prepared, and outputs and inputs of these operation units are set in a predetermined mode. In a tone signal generating method for generating one tone signal in accordance with the connection mode, the output of a predetermined arithmetic unit is added to the input of the unit and one or more arithmetic units preceding the unit. Are formed, and the feedback level of each feedback signal is set to 0 by independently multiplying each of the feedback signals input through the respective feedback paths by a variable coefficient including 0. Independently controlling each of the variable units, the output of the predetermined arithmetic unit is arbitrarily selected from the unit and one or a plurality of arithmetic units at the preceding stage. The connection mode is set so that a plurality of feedback paths to be added to the input of the knit are formed, and thus the feedback signals, which are independently level-controlled, are used as modulation signals in the respective arithmetic units, and are input from other inputs. A modulation operation for modulating a phase signal or a waveform signal is performed.

[Action and effect of the invention]

According to the present invention, basically, one arithmetic unit performs a predetermined waveform generation calculation using a phase signal or a waveform signal applied to one or a plurality of inputs as a parameter, that is, a predetermined calculation unit. A plurality of such arithmetic units are prepared, and the outputs and inputs of these arithmetic units are connected to each other in a predetermined manner, and one musical tone signal is formed in accordance with the connection manner. The outputs and inputs of a plurality of arithmetic units, each of which can independently perform a predetermined waveform generation operation, are connected to each other in a predetermined manner. The result of the generated operation is taken into the input signal of the operation unit at the next stage, and a complicated waveform generation operation can be performed.

In particular, a feature of the present invention is that a plurality of feedback paths for adding the output of a predetermined arithmetic unit to the input of the unit and one or more arithmetic units at the preceding stage are formed, and each of these return paths is formed. In this configuration, each of the feedback signals input through the inverter is independently multiplied by a variable coefficient including 0, and the feedback level of each feedback signal is independently adjusted within a variable range including 0. And the connection mode is set such that a plurality of feedback paths are formed to add the output of a predetermined arithmetic unit to the input of the arbitrary unit of the unit and one or more arithmetic units in the preceding stage. The phase signal or waveform signal input from another input using the feedback signal thus independently controlled in level as a modulation signal in each arithmetic unit. In that to carry out the modulation operation of modulation.

Due to this feature, first, a signal that is fed back as an operation parameter via the feedback path contains a complex harmonic component, and further modulation operation is performed using this. Since the connection mode is set so that a plurality of such feedback paths are formed, complicated modulation can be realized by a relatively simple configuration, and therefore, the number of arithmetic units can be increased. In addition, the present invention has an excellent effect that a tone signal including a large number of harmonic components can be generated with a relatively simple configuration.

Secondly, since the feedback levels of signals that are fed back and input through a plurality of feedback paths are independently controlled by coefficients, a more versatile musical tone can be obtained in combination with the formation of the plurality of feedback paths. An excellent effect that control becomes possible is achieved.

Third, independent control of the feedback level of each feedback signal is 0
Is performed by multiplying each coefficient by a variable coefficient including the coefficient. Therefore, no feedback is practically performed on the feedback path in which the coefficient is set to 0. It can be easily variably controlled by setting the value. Therefore, it is possible to easily set / change the form of the return path network including the plurality of return paths, and thus, it is possible to easily realize more various tone control / tone change. , Which is an excellent effect.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing an embodiment of the present invention, in which three arithmetic units OP1 to OP3 are connected in cascade. Each arithmetic unit OP1~OP3 includes an input P _in for phase signals, the input W _in1, W _in2 for waveform signal has each of these input P _in, W _in1, W _in2 to the applied phase A predetermined waveform generation calculation is performed using the signal or the waveform signal as a parameter. The output of the operation unit OP1 is the operation unit O
Applied to the input W _in1 of P2, the output of the arithmetic unit OP2 is applied to the input W _in1 arithmetic unit OP3, basically three arithmetic units OP1~OP3 is set to aspects cascaded. Here, the output of the arithmetic unit OP3 and feedback path applied to the input W _in2 self unit OP3, a feedback path is added to the input W _in2 before one stage unit OP2, an input W _in2 two stages before the unit OP1 The connection mode of each of the units OP1 to OP3 is further set so that three return paths, ie, additional return paths, are formed. That is, the output of the arithmetic unit OP3 is temporarily stored in the feedback register FR, the output of the register FR is applied to the input W _in2 of each unit OP1~OP3 via respective multipliers ML1~ML3 for feedback ratio control.

The register FR is provided to delay the output signal of the operation unit OP3 by at least one sampling time and feed it back to the input side of each unit. In order to prevent an oscillation phenomenon due to the feedback, the register FR has at least one sampling time in the feedback path. This is to set a delay. Feedback level data FL1 to FL3 for independently setting feedback rates are input to multipliers ML1 to ML3 provided in each feedback path. Also, the input of each operation unit OP1 to OP3
Phase data P1~P3 are respectively input to the P _in. The phase data P1 to P3 periodically change at a frequency related to the pitch of the musical tone to be generated. The frequency corresponds to the frequency

The basic arithmetic expressions in the arithmetic units OP1 to OP3 are, for example, common. Simply connecting the units OP1 to OP3 in cascade simply incorporates the operation result of the unit OP1 into one parameter in the operation expression of the unit OP2,
Only a multiplex operation expression in which the operation result of OP2 is incorporated into one parameter in the operation expression of the unit OP3 is realized. However, by providing a plurality of feedback paths as in the present invention, it is possible to realize not only a multiplex operation expression but also a multiple feedback operation expression, and even more complicated operations can be performed without increasing the number of operation units. It will be done substantially.

The basic arithmetic expressions executed by the arithmetic units OP1 to OP3 include a frequency modulation operation and an amplitude modulation operation.
When the frequency modulation operation is performed, the configuration of one operation unit OP can be as shown in FIG. 2, for example. Adder 1
Adds the waveform signal supplied to the input W _in1 and phase data applied to the input P _in (this corresponds to the modulation signal), modulated by a waveform signal input W _in1 phase data input P _in I do. The adder 2, the adder 1 outputs the input W waveform signal applied to _in2 (which also corresponds to the modulated signal) and adding the further modulated by a waveform signal input W _in2 the modulated phase data . The output of the adder 2 is a sine wave memory 3
And the sine waveform sample point amplitude data stored in the memory 3 is read out according to the modulated phase data. The output of the memory 3 is given to a multiplier 4 for controlling the envelope level, and its amplitude level is controlled according to the envelope level data EL.
Phase data applied to the input P _in .omega.t, input W _in1, W _in2 to join waveform signal (i.e. modulated signal) (M1), (M
Assuming 2), the operation executed by the operation unit OP is EL · sin {ωt + (M1) + (M2)}, and frequency modulation is performed.

Figure 3 is shows a configuration example of the arithmetic unit OP for performing amplitude modulation operation reads the sine wave memory 5 by the phase data ωt applied to input P _in, the input W _in1, W
waveform signal applied to _in2 (modulated signal) (M1), (M
2) is added by the adder 6, and the cosine wave memory 7 is read out based on the added output. The output of the memories 5 and 7 is multiplied by the multiplier 8 to perform amplitude modulation of the sine wave signal sinωt. The output of the multiplier 8 is provided to the multiplier 9, and its amplitude level is controlled according to the envelope level data EL. Thus, the operation executed by the operation unit OP is EL と な り cos ｛(M1) + (M2)｝｝ sinωt, and the amplitude modulation operation is executed.

The connection form shown in FIG. 1 is merely an example, and various other forms are possible. Further, by setting the values of the feedback level data FL1 to FL3 to zero, a specific feedback path can be substantially cut off. Further, all the arithmetic units OP1 to OP3 may be different from each other instead of having the same configuration. For example, one arithmetic unit may perform a frequency modulation operation and another arithmetic unit may perform an amplitude modulation operation. Further, in order to prevent a hunting phenomenon due to feedback, the portion of the feedback register FR in FIG. 1 may be replaced by an averaging circuit as shown in FIG. In this case, the register 11 stores a signal one sampling time before the waveform signal stored in the register 10 and outputs the signals from the registers 10 and 11 (that is, the waveform signal at a certain sampling time and the waveform signal one sampling time before the sampling signal). )
Are added by the adder 12, and the addition result is shifted by half to obtain an average value. The hunting phenomenon can be prevented by calculating the average value of the waveform amplitudes of adjacent sample points and feeding back the average value.

FIG. 5 schematically shows the entire structure of an electronic musical instrument embodying the present invention. A tone signal generating method according to the present invention is employed in a tone signal forming circuit 13. The tone signal forming circuit 13 includes six arithmetic units OP1 to OP6, and the connection mode between the units can be selectively switched. In this embodiment, the tone signal forming circuit 13 is provided with one arithmetic unit OP in terms of hardware, and this is used as six arithmetic units OP1 to OP6 by using time division in six time slots. .

The keyboard circuit 14 includes a key switch corresponding to each key of the keyboard, and outputs a key code KC of the pressed key and a key-on signal KON. The phase data generating circuit 15 generates phase data P1 to P6 corresponding to the key code KC in a time-division manner corresponding to each of the operation units OP1 to OP6. The envelope generating circuit 16 generates envelope level data EL1 to EL6 corresponding to each of the arithmetic units OP1 to OP6 in a time division manner based on the key-on signal KON.

The parameter generation circuit 17 generates various parameters in accordance with the tone selected by the tone selection circuit 18, and generates these parameters in a time-division manner corresponding to the time slots of the operation units OP1 to OP6. I do. These parameters are input to the phase data generating circuit 15, the envelope generating circuit 16, and the musical tone signal forming circuit 13. The parameters input to the phase data generation circuit 15 are
Coefficient K of phase data P1 to P6 generated corresponding to OP1 to OP6
Are independently set, and if the phase data determined according to the key code KC is ωt, the phase data P1 to P6 having the content of kωt are generated according to this parameter. The parameters input to the envelope generating circuit 16 are for setting various envelope waveform parameters such as the attack rate and the attack level of the envelope level data EL1 to EL6 generated corresponding to each of the arithmetic units OP1 to OP6. The parameters input to the tone signal forming circuit 13 are other appropriate parameters used for the waveform generation calculation in the calculation unit. For example, arithmetic unit
OP1 to OP6 are divided into a plurality of streams and arranged in parallel, and if a connection mode in which outputs of the respective streams are added can be selected, a level for correcting the volume bleed according to the number of added streams is selectable. The correction data LC is included in such parameters. The feedback level data FL1
~ FL6 is also included in such parameters.

The control signal generation circuit 19 generates a control signal for setting the connection mode of the arithmetic units OP1 to OP6 in the tone signal formation circuit 13 according to the tone color selected by the tone color selection circuit 18.

Based on the data P1 to P6, EL1 to EL6, parameters and control signals given from the circuits 15 to 17, 19, the tone signal forming circuit 13 performs calculations for each of the arithmetic units OP1 to OP6 in a time-division manner and This calculation is performed in a state where the calculation units are connected according to the set connection mode. The tone signal thus formed is converted into an analog signal by the digital / analog converter 20 and supplied to the sound system 21.
Note that a crop pulse φ is given to each of the circuits 13, 15 to 17, and 19 in order to set a time-division time slot corresponding to each of the arithmetic units OP1 to OP6.

FIG. 6 shows an example of the internal configuration of the tone signal forming circuit 13, in which a frequency modulation operation is performed. Operation unit OP includes an adder 22 for modulating the phase data P1~P6 applied to the input P _in, sine wave table 23 which stores the sample value of the sine wave in a logarithmic representation data format
And an adder 24 for controlling the amplitude level, a logarithmic / linear conversion circuit 25, and an adder 26 for adding the modulation signals applied to the inputs _Win1 and _Win2 . The adder 22 adds the phase data P1 to P6 provided in a time-division manner corresponding to the time slots of the operation units OP1 to OP6 and the waveform signal (that is, the modulation signal) provided from the adder 26, and performs phase modulation. Is what you do. The adder 24 converts the logarithmic sine wave sample value data read from the sine wave table 23 according to the output of the adder 22 into envelope level data EL1.
ELEL6 and the level correction data LC are added.
Data EL1 to EL6, LC shall also be given in logarithmic expression format,
The addition of the logarithms in the adder 24 substantially multiplies the amplitude coefficient. The log / linear conversion circuit 25 converts the output of the logarithmic expression adder 24 into linear expression data.

The operation unit connection mode setting circuit 27
, The output of the feedback register FR, the one-stage shift register SR, the memories M1, M2 and the accumulator AR, the selector 28 to which the outputs of the register SR and the memories M1, M2 and the accumulator AR are input, and the output of the feedback register FR. Feedback Regis FL (FL1-FL6)
, And a latch circuit 30 for latching the output of the accumulator AR. The output of the latch circuit 30 is
Is output as a tone signal formed by

The feedback register FR, the memories M1, M2, and the latch circuit 30 have a load input L and a reset input R, and the control signal generated from the control signal generating circuit 19 receives these inputs.
In addition to L and R, it controls loading and resetting of data. The accumulator AR has an accumulate enable input AC and a reset input R, and the control signal is applied to these inputs AC and R to control the accumulation and reset of data. The control signal is also applied to a select control input of selector 28 to control which input from which data to select. The output of the selector 28 and the shift circuit 29 is applied to the adder 26 via a modulated signal input W _in1, W _in2 arithmetic unit OP, where they are summed.

The feedback register FR, like the feedback register FR of FIG. 1, stores waveform signal data as a result of operation of a predetermined operation unit to be fed back to its own operation unit or a preceding operation unit. A signal "1" is supplied to the load input L in a time slot in which the operation result of the predetermined operation unit is output from the operation unit OP. As is apparent, the path from the feedback register FR to the adder 26 via the shift circuit 29 corresponds to the above-mentioned feedback path. The feedback level data FL1 to FL6 indicate appropriate values in the time slot of the arithmetic unit where the feedback path is to be formed, and the output signal of the register FR shifted according to the value is supplied to the adder 26. In a time slot of an arithmetic unit in which a feedback path is not provided, the feedback level data FL1 to FL6 have contents corresponding to level 0, the shift circuit 29 is cut off, and the output is set to 0.
To It is more preferable that the feedback register FR be constituted by an averaging circuit as shown in FIG.

The shift register SR shifts according to the clock pulse φ, and outputs the operation result in a certain time slot in the next time slot.
This is for holding a calculation result in an arbitrary time slot. The accumulator AR is provided for each operation unit OP
The output signal of one or more arbitrary units among 1 to OP6 is added, and a signal "1" is given to the accumulation enable input AC in a time slot corresponding to the unit to be added. The selector 28 is connected to each operation unit OP1
As an arithmetic unit waveform signal to be supplied to the input W _in1 of the OP in each time slot corresponding to ～OP6 (modulation signal), the register SR, the memory M1, M2, by selecting an appropriate output signal of the accumulator AR, predetermined The interconnection of each of the arithmetic units OP1 to OP6 according to the connection mode (1) is realized. In the latch circuit 30, a signal "1" is given to the load input L at the end of one operation cycle in which the time slots of all the operation units OP1 to OP6 make one round, and based on this, the output of the accumulator AR is latched. Thus, each operation unit OP
One sample value data of a tone signal obtained as a result of performing an operation by connecting 1 to OP6 in a predetermined connection manner is latched by the latch circuit 30.

As an example, a case where six arithmetic units OP1 to OP6 are connected as shown in FIG. 7 will be described. In this connection mode, OP4 is selected as a predetermined operation unit to which an output signal is to be fed back to itself or another operation unit. The output signal of this operation unit OP4 is stored in a feedback register FR, and the output of this register FR is output. The signal is fed back to the input side of its own unit OP4 and the preceding units OP5 and OP6, and is also input to another series of units OP1 and OP2 provided in parallel with its own unit OP4. Is also input to the unit OP3 in the subsequent stage. Data FL1 to FL6 input as multipliers to multipliers (shift circuits) provided on the paths for leading the outputs of the registers FR to the units OP1 to OP6 are feedback level data corresponding to the arithmetic units OP1 to OP6. Note that the output signal of the register FR applied to the operation units OP1 to OP3 is not a feedback signal to these units OP1 to OP3. A connection mode to be added to the unit is also feasible.

FIG. 8A shows the time-division time slots corresponding to each of the operation units OP1 to OP6. Six time slots 1 to 6 in one operation cycle corresponding to one sampling time are calculated in the order of time. Unit OP6 to OP1
It corresponds to. Therefore, in each of the time slots 1 to 6, the phase data P6 corresponding to each of the arithmetic units OP6 to OP1
.About.P1, envelope level data EL6 to EL1, and feedback level data FL6 to FL1 are supplied as shown in FIG. 8 (a).

In the case of realizing the connection of FIG.
The destination of the output signal of the operation unit OP in No. 6 is the eighth
As shown in FIG. 8B, the selection by the selector 28 is made as shown in FIG. 8C.

First, in the time slot 1, nothing is selected by the selector 28, and only the output of the shift circuit 29 is input to the adder 26 of the operation unit OP. If the output signal of the predetermined operation unit OP4 from the feedback register FR to the shift circuit 29 one sampling time before is indicated by (−1), the operation result of the operation unit OP6 performed in this time slot is as follows. .

OP6 output = EL6 · sin {P6 + FL6 · (-1)} This output signal is taken into accumulator AR.

Even in time slot 2, the selector 28 does not make a selection, and the operation result of the operation unit OP5 is as follows.

OP5 output = EL5 · sin {P5 + FL5 · (-1)} This output signal is taken into the accumulator AR, and the output of the accumulator AR is “OP6 output plus OP5 output”.

In time slot 3, the selector 28 selects the output of the accumulator AR. This allows the operation unit OP4
Is as follows.

OP4 output = EL4 · sin [P4 + FL4 · (-1) + EL5 · sin ｛P5 + FL5 · (-1)｝ + EL6 · sin ｛P6 + FL6 · (-1)｝] This output signal is taken into the feedback register FR.

In time slot 4, the selector 28
Output of SR (that is, the above OP in the previous time slot 3)
Select (4 outputs). In this time slot 4, level correction data LC is also given as needed. Thus, the operation result of the operation unit OP3 is as follows.

OP3 output = LC · EL3 · sin ｛P3 + FL3 · (-1) + “OP4 output”｝ This OP3 output signal is taken into the accumulator AR, but the accumulator AR resets the old contents “OP5 output + OP6 output” before resetting. Take in the OP3 output signal.

In time slot 5, nothing is selected by the selector 28, and the operation result of the operation unit OP2 is as follows.

OP2 output = EL2 · sin {P2 + FL2 · (-1)} In time slot 6, the selector 28 shift register
Output of SR (ie, the above OP in previous time slot 5)
Select 2 outputs). Further, level correction data LC is also given as needed. As a result, the operation result of the operation unit OP1 is as follows.

OP1 output = LC / EL1 / sin {P1 + FL1 / (-1) + "OP2 output"} This OP1 output is taken into the accumulator AR and added to the already taken OP3 output. Output signal of this accumulator AR (that is, "OP1 output + OP3 output")
Is latched by the latch circuit 30 at the rise of the next time slot 1, and immediately thereafter, the contents of the accumulator AR are reset.

Thus, the arithmetic expression of the tone signal finally latched in the latch circuit 30 is: OP1 output + OP3 output = LC EL1 sin [P1 + FL1 (-1) + EL2 sin {P2 + FL2 (-1)}] + LC EL3 · sin [P3 + FL3 · (-1) + EL4 · sin [P4 + FL4 · (-1) + EL5 · sin {P5 + FL5 · (-1)] + EL6 · sin {P6 + FL6 · (-1)}].

The tone signal forming circuit 13 shown in FIG. 6 is not limited to the connection mode shown in FIG. 7, but may be realized in any other connection mode. The connection mode is
In FIG. 5, the tone is determined according to the tone selected by the tone selection circuit 18. However, the present invention is not limited to this.
The connection mode may be freely set by the player using the connection combination variable setting means as shown in No. 1789.

Further, in FIG. 7, the output of the feedback register FR can be given to all the arithmetic units, but the present invention is not limited to this. Further, the arithmetic unit that feeds back the output signal is not limited to OP4 and may be any unit. Further, the number of arithmetic units (number of time slots) to be used is not limited to six, but may be any number.

Although the embodiment of FIG. 5 shows a single sound generation, a double sound generation type may be provided by providing a key assigner in connection with the keyboard circuit 14. In the case of the time division multiple sound generation method, the registers FR, SR and memory M shown in FIG.
1, M2 and the accumulator AR may be one that stores data for a plurality of channels.

In the embodiments of FIGS. 5 and 6, the tone signal is generated by the frequency modulation operation, but this may be an amplitude modulation operation.

As is clear from the above-described embodiment, according to the present invention, it is possible to perform operations with complicated contents as compared with the number of operation units, to generate a tone signal including a large number of harmonic components, and Complex tone control is also possible by controlling the harmonic components of. For example, the arithmetic expression of the tone signal obtained according to the connection mode shown in FIG. 7 is “OP1 output + OP3 output” described above.
Where (-1) contained therein consists of an arithmetic expression as shown in the above-mentioned "OP4 output", which can be normally realized by the six arithmetic units OP1 to OP. A much more complex arithmetic expression is substantially executed. Further, when the output of the arithmetic unit OP4 is fed back only to its own input, or when it is simply fed back in a ring shape (eg, OP
It can be understood from the above equation that it is possible to execute a much more complicated equation as compared with (the output of 4 is fed back only to OP6).

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of an arithmetic unit in FIG. 1 in the case of performing a frequency modulation operation, and FIG. FIG. 4 is a block diagram showing an example of an arithmetic unit in FIG. 1, FIG. 4 is a block diagram showing an example of an averaging circuit which can be substituted for the feedback register of FIG. 1, and FIG. 5 is an example of an electronic musical instrument embodying the present invention. FIG. 6 is a block diagram showing an example of an internal configuration of the tone signal forming circuit in FIG. 5, FIG. 7 is a schematic diagram showing an example of a connection mode of six arithmetic units, and FIG. 8 is a timing chart showing time division timing in the circuit of FIG. 6 and control signal generation timing for realizing the connection mode of FIG. 7; OP, OP1 to OP6 …… Calculation unit, 1,2,6,12,22,24,26 ……
Adder, ML1, ML2, ML3, 29 ... Multiplier or shift circuit, 4,
8, 9 ... multiplier, 3, 5 ... sine wave memory, 7 ... cosine wave memory, 13 ... tone signal forming circuit, FR ... feedback register, FL1 to FL6 ... feedback level data,
P1 to P6: Phase data, EL1 to EL6: Envelope level data.

Claims (5)

(57) [Claims] An arithmetic unit for performing a predetermined waveform generation operation using a phase signal or a waveform signal applied to one or a plurality of inputs as a parameter is prepared, and the outputs and inputs of these operation units are set to a predetermined value. A tone signal generating method for generating one tone signal according to the connection mode, wherein an output of a predetermined arithmetic unit is added to an input of the unit and one or more arithmetic units preceding the unit. A plurality of feedback paths are formed, and the feedback level of each feedback signal is reduced to 0 by independently multiplying each of the feedback signals input through the respective feedback paths by a variable coefficient including 0. And the output of the predetermined arithmetic unit is controlled by the unit and its preceding stage.
Alternatively, the connection mode is set so that a plurality of feedback paths to be added to the inputs of arbitrary plural units among the plural arithmetic units are formed, and thus the feedback signals which are independently level-controlled are modulated signals in the respective arithmetic units. And performing a modulation operation for modulating a phase signal or a waveform signal inputted from another input. 2. The arithmetic unit according to claim 1, wherein said arithmetic unit includes an adder for adding a signal given to said one or more inputs, and a waveform memory for reading a waveform signal in accordance with an output of said adder. 2. A method for generating a tone signal according to claim 1. 3. The tone signal generating method according to claim 1, wherein said predetermined waveform generation operation to be performed by said operation unit is a frequency modulation operation. 4. The tone signal generating method according to claim 1, wherein said predetermined waveform generation operation to be performed by said operation unit is an amplitude modulation operation. 5. The arithmetic unit according to claim 1, further comprising an input for receiving a phase signal that changes with time in accordance with a frequency of a waveform signal to be generated, and a plurality of inputs for receiving a plurality of waveform signals as a modulation signal. A method for generating a tone signal according to claim 1.