JP2988065B2 - Music signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone signal generator for forming and outputting a tone signal by modulation operation such as FM operation and AM operation.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus has been disclosed in, for example,
As disclosed in Japanese Patent Application Laid-Open No. 3-42276, a signal having a first input terminal, a second input terminal, and an output terminal is supplied from the outside to the first input terminal. Modulation operation means for executing a modulation operation for modulating the other waveform signal with one of the waveform signals fed back to the two input terminals and outputting a modulated waveform signal from the output terminal; And delay means interposed in a feedback path from the output terminal to the second input terminal for delaying the waveform signal output from the output terminal by a predetermined time slot. A waveform signal having a wave component is generated as a tone signal.

[0003]

In the above-mentioned conventional apparatus, when it is desired to delicately change the timbre of the generated tone signal, the waveform signal supplied from the outside to the first input terminal of the modulation calculating means is changed. It is necessary to change the ratio of each harmonic component formed by the modulation operation, that is, the harmonic composition. However, although there is a certain correspondence between the type of the harmonic component formed by the modulation operation and the waveform signal supplied from the outside, this correspondence is difficult for humans to perceive sensuously, and It is difficult to generate a tone signal of a desired tone by such tone change. SUMMARY OF THE INVENTION The present invention has been made to address the above-described problem, and an object of the present invention is to provide a tone signal generating apparatus capable of easily generating a tone signal of a desired tone.

[0004]

In order to achieve the above object, the constitutional features of the invention according to claim 1 include a plurality of features .
Repeat each modulation operation in the operation time slot
Signal generator that forms a single tone signal
Te, the first input terminal, has a second input and output ends
Ri, a waveform signal from the external is <br/> supplied for each operation time slot in the first input end, the same second input from the output end each
One of the operation data and then performs modulation operation waveform signal modulated from the output terminal for modulating the other waveform signal waveform signal with Shin Namikata that is fed back to each calculation time slot
Modulation operation means for outputting each time slot, and a modulation operation means interposed in a feedback path from an output end of the modulation operation means to a second input end.
Calculating one of the plurality of calculation time slots
Waveform obtained by modulation operation in time slot
Modulation of the signal in another computation time slot
The waveform signal output from the output terminal for each operation time slot <br/> for each operation time slot
From the output terminal of the modulation operation means.
The delay means is interposed in the return path to the second input terminal.
Some parts are shared, and according to external control signals
A filter whose frequency characteristic can be changed .

According to a second aspect of the present invention, in the tone signal generating apparatus according to the first aspect of the present invention, the delay means is configured to determine a waveform signal input thereto in advance.
First delay means for delaying the input waveform signal by
Select the delay time by selectively holding and outputting the signal
And a second delay means that can be dynamically changed,
The filter is connected to the first delay means in a predetermined manner.
And a third delay means for delaying the waveform signal by the time
It has been constituted by .

[0006]

According to the first aspect of the present invention, each operation time slot is externally provided.
Waveform signals supplied for each operation and each operation via delay means
The waveform signal fed back for each time slot is subjected to modulation operation for each operation time slot by the modulation operation means, and one musical tone signal composed of a waveform signal rich in harmonics is converted to a plurality of performance signals.
It is formed by a modulation operation using an arithmetic time slot . On the other hand, since the frequency characteristic of the filter is changed in response to an external control signal, the ratio of the harmonic component of the waveform signal rich in the harmonic is changed and controlled in accordance with the external control signal. In this case, since the relationship between the frequency characteristic of the filter and the ratio of each harmonic component (harmonic composition) is simple and clear, the tone of the tone signal can be easily and subtly changed, and the tone signal of the desired tone can be changed. Can be easily obtained. In the present invention, the filter is usually
Section has a delay means, but this delay means
Shares part of the delay means provided in the return path
Therefore, apart from the delay means in the feedback path,
Eliminates the need for delay means, making the filter easier
Can be configured.

Further, in the invention according to claim 2 configured as described above, the delay means includes a first and a second delay unit.
Means, and the second delay means receives the input waveform signal.
Selectively hold and output to select delay time
Can be changed to multiple calculation time slots.
Modulation operation in one operation time slot
The waveform signal obtained by the
Can be selectively used for the modulation operation in. Accordingly
Therefore, the modulation operation results in a plurality of operation time slots are
Selectively variously combined to form various tone signals
I will be able to.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electronic musical instrument provided with a tone signal generating apparatus utilizing FM operation according to the present invention.

This electronic musical instrument has a key switch group 11 composed of a plurality of key switches provided for each key of a keyboard.
And a tone color selection switch group 12 including a plurality of tone color selection switches for selecting a tone color, an effect, a modulation mode, and the like. The key switch group 11 and the tone color selection switch group 12 are connected to a microcomputer 15 via interface circuits 13 and 14, and the computer 15 scans the key switch group 11 and the tone color selection switch group 11. This detects the pressed state of each key and the selection state of the tone and the like, executes the allocation process of the depressed key to the tone signal forming channel, and also sets the tone to be generated in relation to the allocation. A control signal for controlling pitch, timbre, volume and the like is output to the tone signal generator 10.

In this case, the control signal is a pitch parameter PP that changes in proportion to the pitch of a depressed key, a microcode MC for controlling the mode of the FM operation in the tone signal generator 10, the FM operation And a key-on signal KO representing a key press and release key, and these signals PP, MC, EP, KO are used as the tone signal generator 10. M * n (6 in this example)
(4) operation time slots. Here, m represents the number of tone signal forming channels of the tone signal generator 10 (corresponding to the number of tones that can be produced simultaneously), and n represents the number of operation time slots assigned to each tone signal forming channel. (The number of operators), and these numbers m and n are changed according to the selection of the tone color and the selection of the modulation mode.

A detailed description of the tone signal generator 10 will be described later, and the generator 10 will be described with reference to the signals PP, MC, EP, K
1 consisting of m * n operation time slots according to O
In each operation cycle, each instantaneous value of the tone signal formed in a time-division manner in each tone signal forming channel is added and synthesized,
The result of the synthesis is output to the D / A converter 16. The D / A converter 16 converts a supplied digital signal into an analog signal and outputs the analog signal. A sound system 17 is connected to the D / A converter 16. The sound system 17 includes an amplifier and a speaker, and generates a musical tone corresponding to the supplied analog signal.

Next, the tone signal generator 10 will be described in detail.
A is provided.

As shown in FIG. 2, the FM operation circuit 10A includes an adder 21, a sine wave table 22, an adder 23, and a logarithmic / linear conversion table 24 which are connected in series.
It has M operation units. The adder 21 adds a phase signal PD composed of a sawtooth wave which is supplied from the outside and repeatedly changes from 0 to 2π with time and a waveform signal XD circulating through the arithmetic unit, and outputs the result. The sine wave table 22 stores data representing the instantaneous value of a sine wave logarithmically displayed for a linear input. The adder 23 adds an envelope signal AD, which is supplied from the outside and expresses a modulation index or an amplitude envelope of a generated musical tone signal in an FM operation by a logarithm, and a waveform signal from the sine wave table 22 and outputs the result. The logarithmic / linear conversion table 24 stores a linear value for an input logarithmic value. As a result, this FM
The operation unit executes the operation of the following equation 1 on the input signals XD, PD, and AD and outputs a waveform signal YD.

[0014]

YD = AD * sin (XD + PD) The adder 21, sine wave table 22, adder 2
Delay circuits 25 to 28 are connected to the subsequent stages of the logarithmic / linear conversion table 24 and 3 respectively. These delay circuits 25 to 28 are controlled by a clock pulse φ to delay the input waveform signal by one operation time slot and output it.

The clock pulse φ is output from the timing control signal generator 10B (FIG. 1).
As shown in FIG. 6, the period of each of m * n operation time slots is defined. As shown in FIGS. 5 and 6, the timing control signal generator 10B repeatedly outputs the first to fourth slot timing signals φS1 to φS4 having one operation time slot width every four operation time slots.

The output of the FM operation unit is supplied to a subtractor 31,
Multiplier 32, adder 33 and shift registers 34, 3
5 is connected to the digital filter. This digital filter constitutes a low-pass filter, and its cutoff frequency is controlled by a filter control signal FC supplied to the multiplier 32 from outside. The shift registers 34 and 35 are composed of 52-stage and 12-stage registers controlled by the clock pulse φ, respectively, and output the input waveform signal after delaying them by 52 and 12 operation time slots, respectively. In this case, a subtractor 31 as an input circuit of the digital filter
It should be noted that the waveform signal input from the delay circuit 28 is delayed by 64 operation time slots constituting one operation cycle by the shift registers 34 and 35 and input to the subtractor 31 and the adder 33. is there.

The output of the digital filter, that is, the output of the shift register 34, is connected to a selector 36, a register 37, a selector 38, a shift register 41, an OR circuit group 42, a delay circuit 43 and a shifter 4 connected in series.
4 is connected to the adder 21. Selector 36
Is the temporary write signal supplied to the selection control input
Controlled by TW, the same signal TW is high level
When "1", the output waveform signal YD from the FM operation unit via the digital filter is selectively output to the input of the register 37, and when the signal TW is at the low level "0", the signal fed back from the register 37 is used as the same register. The selector 37 selectively receives and outputs a signal by a clock pulse φ. The selector 36 and the register 37 output the output waveform signal.
A temporary register for temporarily storing the YD and delaying and outputting one operation time slot is constituted.

The output of the register 37 is connected to one input of a selector 38. The selector 38 receives a 2-bit register selection signal RSEL supplied to its selection control input.
Is "10", the waveform signal from the register 37 is selectively output to the shift register 41, and when the selection signal RSEL is "01", the signal supplied to the other input is selectively output to the shift register 41, and When the selection signal RSEL has other values "00" and "11", neither input is selected and output. The shift register 41 has seven stages, and the capture and output of signals at each stage are controlled by a clock pulse φ. The register 41 delays an input waveform signal by seven operation time slots. Output.

The OR circuit group 42 has first to third input terminals, and a waveform signal supplied to the first input terminal from the shift register 41 and each waveform signal supplied to the second and third input terminals. Are ORed for each bit, the number of bits of each waveform signal is equal to the number of bits of each waveform signal, and the signals of each bit constituting each waveform signal are ORed and output. However, in this case, as described later, a plurality of waveform signals are not supplied to the first to third input terminals at the same time.
Virtually, each waveform signal supplied to the first to third input terminals is output to the delay circuit 43 as it is. The delay circuit 43 is controlled by the clock pulse φ, delays the input waveform signal by one operation time slot, and outputs the delayed signal to the shifter 44. The shifter 44 shifts the input waveform signal upward or downward by a predetermined bit in accordance with the shift control signal SHIFT supplied to its control input terminal, and outputs it. Accordingly, the input waveform signal shift control signal SHIFT amount only ... ^2-2 represented by, 2 ^-1, is outputted 1,2,2 ² ... multiplied by to.

In the circulating path of the waveform signal subjected to the FM operation configured as described above, the waveform signal is
28 delays four operation time slots, shift register 34 delays 52 operation time slots, and register 37, shift register 41 and delay circuit 43 delay nine operation time slots. Therefore, in order for the waveform signal subjected to the FM operation to circulate once, 65 operation time slots larger by "1" than the 64 operation time slots constituting one operation cycle are required. The delay process of the waveform signal is shown in the time chart of FIG. 5 with reference to point A in FIG. 2 and corresponding to points A to G.

In the FM operation circuit 10A, an adder 45, a selector 46, a register 47 and a selector 48 are provided in parallel with the selector 36, the register 37 and the selector 38.

The adder 45 adds the output signal of the shift register 34 and the output signal of the selector 48 and outputs the result.
The selector 46 is controlled by an accumulator write signal AW supplied to its selection control input.
Is high level "1", the output waveform signal of the adder 45 is selectively output to the input of the register 47, and when the signal AW is low level "0", the waveform signal fed back from the register 47 is output to the register 47. Select output to input. Register 4
The adder 45, the selector 46, and the register 47 constitute an accumulator for accumulating the output waveform signal into the output waveform signal of the selector 48. .

The output of the accumulator, that is, the output of the register 47, is connected to the other input of the selector 38 and to one input of the selector 48. The other input of the selector 48 is connected to the output of the register 37. The selector 48 generates a 2-bit accumulator selection signal ASEL supplied to its selection control input.
Is "10", the waveform signal is selectively output from the register 37 to the adder 45, and when the selection signal ASEL is "01", the register 47 is output.
Is selected and output to the adder 45, and when the selection signal ASEL is another value "00" or "11", none of the input waveform signals is selected and output.

In the accumulator adder 45, the selector 46, the register 47, and the selector 48 thus configured, when the delay circuits 25 to 28, the shift registers 34, 41, and the delay circuit 43 are combined, a waveform is obtained. One circulation of the signal requires 65 operation time slots. And also in this case,
The process of delaying the waveform signal is the same as in the above case. (See FIG. 5.) Further, in the FM operation circuit 10A, the selectors 36 and 46, the registers 37 and 47, the selector 3
8, 48 and the shift register 41 are provided with two feedback paths for feedback FM calculation in parallel. The one feedback path includes a delay circuit 51, latches 52 and 53, a shift register 54, an adder 55, a latch 56, and a gate 57 connected in series, as shown in FIG. The other feedback path, including the delay circuit 51, includes latches 58 and 61, a shift register 62, an adder 63, a latch 64, and a gate 65 connected in series.

The delay circuit 51 is controlled by the clock pulse φ, delays the input waveform signal from the adder 45 (FIG. 2) by one operation time slot, and outputs it to the latches 52 and 58. The latches 52 and 58 are controlled by the first and second feedback write signals FBW1 and FBW2,
1. When the FBW2 arrives, each waveform input signal is captured and simultaneously output to the latches 53 and 61, respectively. Latch 53,
Numeral 61 is controlled by the first slot timing signal φS1 to take in each input waveform signal upon the arrival of the signal φS1, and at the same time, shift registers 54 and 62 and adder 5
5 and 63, respectively. Each of the shift registers 54 and 62 is composed of 16 stages. Each stage takes in the input waveform signal in synchronization with the third slot timing signal φS3 and also takes in the received waveform signal in synchronization with the first slot timing signal φS1. Output from each shift register 54,
Reference numeral 62 delays the input signal by 64 operation time slots (one operation cycle) and outputs it to the other inputs of the adders 55 and 63, respectively. The adders 55 and 63 add the two input signals and output the signals to the latches 56 and 64, respectively.

The latches 56 and 64 are controlled by a fourth slot timing signal φS4. When the signal φS4 arrives, the latches 56 and 64 take in respective input signals and supply them to the inputs of the gates 57 and 65, respectively. The gates 57 and 65 are controlled to be conductive / non-conductive by the first and second feedback selection signals FBSEL1 and FBSEL2 supplied to the gating control terminal, and are input when each of the selection signals FBSEL1 and FBSEL2 is at the high level “1”. The waveform signal is output to the second and third inputs of the OR circuit group 29, and when the selection signals FBSEL1 and FBSEL2 are at low level "0", the output of the waveform signal is inhibited.

As described above, one cycle of the waveform signal including each feedback path for the FM feedback operation constituted by the circuits 51 to 65 includes the delay circuits 25 to 28, the shift register 34, and the delay circuit 43 described above. Including 1 or 2
64 or 128 operation time slots constituting the operation cycle are required. The delay process of the waveform signal is shown in the time chart of FIG. 6 corresponding to the points A, B, H to J, E, F in FIGS. In addition,
Again, the reference is point A.

The output of the FM operation circuit 10A thus configured, that is, the output of the shift register 34, is connected to an output accumulator 10C as shown in FIG. The output accumulator 10C clears the accumulated storage data every operation cycle by a clear signal CL (see FIGS. 5 and 6) from the timing control signal generator 10B, and outputs the operation output transfer signal OP
Each time T arrives, the output signal of the FM operation circuit 10A is fetched, and the fetched signal is sequentially accumulated. A latch 10D is connected to the output accumulator 10C, and the latch 10D is connected to the timing control signal generator 10C.
Output accumulator 1 based on output latch signal OL output from B
The accumulated storage data of 0C is latched and output. This output latch signal 0L is, as shown in FIGS.
L is supplied to the latch 10D at the same time as L, so that the accumulated data in the output accumulator 10C is stored in the latch 10D before the accumulated storage data in the output accumulator 10C is cleared at the next timing by the clear signal CL. Has become.

Further, the tone signal generating device 10 includes a microcode register circuit 10E. The microcode register circuit 10E includes a selector 71 and a shift register 72 as shown in FIG. The selector 71 supplies the microcomputer 15 with the selection control input.
From the microcode write signal MCWT (high level)
1 "), the microcode MC supplied to the first input from the computer 15 is selectively output to the first stage of the shift register 72. Otherwise, the last stage of the shift register 72 is output. Selectively outputs the microcode MC supplied to its second input to the first stage of the register 72. In this case,
The microcode write signal MCWT output from the microcomputer 15 is synchronized with the clock pulse φ, that is, each operation time slot. The shift register 72 has 6
The register 72 delays the input signal by 64 operation time slots corresponding to one operation cycle. The register 72 delays an input signal by 64 clock times. . Thereby, 64 microcodes MC (corresponding to 64 operation time slots constituting one operation cycle) supplied from the microcomputer 15 are cyclically stored in the selector 71 and the shift register 72 in synchronization with each operation time slot. . However, in this case, the output timing of the shift register 72 is set based on the output timing (point B) of the shift register 34 in FIG.

Each microcode MC has a 2-bit input select instruction signal ISEL1, ISEL0, a 2-bit feedback operation instruction signal FB1, FB0, a 3-bit accumulation operation instruction signal ACC2, ACC1, ACC0, and a 1-bit Temporary register indication signal TR and 1-bit operation output indication signal
It is composed of a total of 21-bit signals including OUT, a 4-bit shift instruction signal SHIFT, and an 8-bit filter control signal FC.

The input select instruction signals ISEL1 and ISEL0 indicate the types of input waveform signals that are fed back to the FM operation as shown in the following. No input waveform signal is indicated by ISEL1 and ISEL0 = "00". By ISEL1 and ISEL0 = “01”, a waveform signal accumulated by the adder 45, the selector 46, and the register 47 of FIG. The waveform signals temporarily stored by the selector 36 and the register 37 in FIG. 2 are represented by ISEL1, ISEL0 = "10". ISEL1 and ISEL0 = “11” represent waveform signals that have been delayed by the circuits 51 to 65 of FIG. 3 for feedback FM operation.

The input instruction signals ISEL1 and ISEL0
Is supplied as a register selection signal RSEL to the selection control input of the selector 38 in FIG. 2 through 1-bit delay circuits 73 and 74 which are transfer-controlled by the clock pulse φ, and is fed back via AND 75 F
It is used to form a control signal for the M operation. The feedback calculation instruction signals FB1 and FB0 are used to form a control signal for the feedback FM calculation, and the lower order bits FB0
Indicates a first feedback FM operation system by "0" and indicates a second feedback FM operation system by "1". The signal of the lower bit FB0 is supplied via an inverter 76 to the other input of the AND 77 whose one input is connected to the output of the AND 75, and the output of the AND 75 is supplied to one input. It is supplied directly to the other input of the connected AND 78. And 7
7 and 78 are supplied to first outputs via 7-bit delay circuits 81 and 82, each of which is transfer-controlled by a clock pulse φ.
And the second feedback selection signals FBSEL1 and FBSEL2 are supplied to the respective control inputs of the gates 57 and 65 in FIG.

On the other hand, feedback calculation instruction signals FB1, F
The upper bit FB1 of B0 indicates "1" to input to the first and second feedback FM operation systems, and "0"
Indicates the prohibition of the input. The signal of the upper bit FB1 is supplied to the other input of the AND 83 having one input connected to the output of the inverter 76, and the signal of the lower bit FB0 is directly supplied to one input. The other input of AND 84 is supplied to the other input. The outputs of the ANDs 83 and 84 are passed through 1-bit delay circuits 85 and 86, each of which is transfer-controlled by a clock pulse φ.
The first and second feedback write signals FBW1 and FBW2 are supplied to the respective latch control inputs of the latches 52 and 58 in FIG.

A 3-bit accumulation calculation instruction signal AC
Lower two bit signals ACC1, ACC0 of C2, ACC1, ACC0
Represents the type of a waveform signal added to the waveform signal from the digital filter in the accumulation operation by the adder 45, the selector 46, and the register 47 in FIG. ACC1, ACC0 = "00", "11" indicate no added waveform signal. ACC1 and ACC0 = "01" represent the accumulated waveform signals in the register 47 of FIG. ACC1 and ACC0 = "10" represent the temporarily stored waveform signal in the register 37 of FIG.

The lower two-bit signals ACC1, AC
C0 is supplied as an accumulator selection signal ASEL to the selection control input of the selector 48 of FIG. 2 via 1-bit delay circuits 87 and 88 which are transfer-controlled by the clock pulse φ.

On the other hand, the most significant bit signal ACC2 of the three-bit accumulation calculation instruction signals ACC2, ACC1, ACC0
Indicates that data is updated in the accumulator including the adder 45, the selector 46 and the register 47 in FIG. 2 by "1", and that the update is prohibited by "0". The signal ACC2 of the most significant bit is supplied to the selection control input of the selector 46 as an accumulator write signal AW.

As for the temporary register instruction signal TR, "1" instructs the acquisition of the waveform signal from the digital filter into the temporary register including the selector 36 and the register 37 of FIG. 2, and "0" inhibits the acquisition. Instruct. The temporary register signal TR is supplied to the selection control input of the selector 36 as a temporary write signal TW.

The operation output instruction signal OUT instructs the output of the result of the FM operation.
To the output accumulator 10C.

The 4-bit shift instruction signal SHIFT controls the input signal level to the FM operation unit.
It is supplied to the control input of the shifter 44 in FIG. 2 via an 8-bit delay circuit 91 which is transfer-controlled by the clock pulse φ.

The 8-bit filter frequency control signal FC is supplied to the multiplier 32 of the digital filter shown in FIG. 2 to set the cutoff frequency of the filter, and is a 12-bit delay circuit which is transfer-controlled by the clock pulse φ. 9
2 to the multiplier 32. It should be noted that the delay times of the various control signals output from the microcode register circuit 10E are different from the above-described F code.
This is in order to match the operation timing of each circuit position in the M operation circuit 10A.

Returning to the description of FIG. 1, the tone signal generator 10 further includes a pitch parameter register circuit 10F and an envelope parameter register circuit 10G.
And a key-on register circuit 10H. These circuits 10F to 10H are provided with the selector 71 and the shift register 7 of the microcode register circuit 10E.
2, each having a 64-stage circular storage circuit (the number of bits differs depending on the application), and stores a pitch parameter PP, an envelope parameter EP, and a key-on signal KO supplied together with a write control signal from the microcomputer 15. The data is cyclically stored in synchronization with the 64 operation time slots described above.

A phase data generator 10I is connected to the pitch parameter register circuit 10F.
0I is supplied with the 64 cyclically stored pitch parameters PP sequentially and repeatedly in synchronization with the clock pulse φ. The phase data generator 10I has a built-in accumulator that accumulates and outputs the 64 pitch parameters PP in a time-division manner in synchronization with the clock pulse φ, and outputs the accumulation result in a sawtooth waveform over 0 to 2π. It is supplied to the adder 21 of FIG. In the accumulation, the key-on signal KO supplied from the key-on register circuit 10H causes the phase signal PD to be initialized to "0" at the start of generation of a musical tone (when a new key is pressed on the keyboard). Has become.

An envelope generator 10J is connected to the envelope parameter register circuit 10G and the key-on register circuit 10H.
The 64 cyclically stored envelope parameters EP and key-on signal KO are sequentially and repeatedly supplied in synchronization with the clock pulse φ. Based on the 64 envelope parameters EP and the key-on signal KO, the envelope generator 10J generates 64 envelope waveforms for controlling the modulation index or the amplitude of the tone signal in the FM operation in synchronization with the clock pulse φ. An arithmetic unit that divides and forms the data is output, and the arithmetic result is supplied to the adder 23 of FIG. 2 as an envelope signal AD. The phase signal PD and the envelope signal AD are added to the adder 21 in the circulating circuit of FIG.
23 are set in accordance with the calculation timing.

Next, the operation of the embodiment constructed as described above will be described. As an example, the number m of musical tones that can be simultaneously generated (the number of musical tone signal forming channels) m is 16 and 1
A case in which the number n of operation time slots assigned to the tone signal formation channel is four will be described. Hereinafter, these four operation time slots are particularly referred to as first to fourth time slots.

These numbers m and n are determined by the tone color selection and the modulation mode selection in the tone color etc. selection switch group 12, and among them, various operation modes are selected. As shown in the connection diagram of FIG. A description will be given of a calculation mode as represented. In the connection diagram of FIG. 7, OP1 to OP4 in the same tone signal forming channel are used.
Represents the FM operation for each of the first to fourth time slots, and the filters 1 to 4 represent the filtering operation for each of the first to fourth time slots. Each FM operation and filtering operation indicate that the operation result of the preceding stage is input to the operation of the subsequent stage in the direction indicated by the arrow, and OP4 having a feedback path represents a feedback FM operation, and one musical tone signal Each FM operation in the formation channel is performed in the order of OP4 → OP1. In this case, by the timbre selection and the modulation mode selection in the timbre etc. selection switch group 12, the microcomputer 15 sends the microcode to the microcode register circuit 10E as shown in FIG. Are supplied to the first to fourth time slots, and the register circuit 10E supplies the FM signal to each of the first to fourth time slots.
The operation mode of the operation circuit 10A is time-divisionally controlled.

In this arithmetic control state, when any key is pressed and released on the keyboard and the key switch corresponding to the key of the key switch group 11 is opened / closed, the microcomputer 15 When the key is opened and closed, the opened and closed key is assigned to one of the 16 tone signal forming channels, and the key is depressed and released in synchronization with the first to fourth time slots belonging to the assigned channel. A pitch parameter PP, an envelope parameter EP and a key-on signal KO related to a key are stored in a pitch parameter register circuit 10F, an envelope parameter register circuit 10
G and output to the key-on register circuit 10H. Then, the phase data generator 10I and the envelope generator 10J time-divisionally output the phase signal PD and the envelope signal AD to the FM arithmetic circuit 10A in synchronization with the first to fourth time slots belonging to the assigned channel. The assignment of each tone signal forming channel on the time axis and the assignment of the first to fourth time slots belonging to the same channel on the time axis are performed as shown in the time charts of FIGS. 4 → 1FM operation, 4 → 1
Filtering operations (corresponding to the first to fourth time slots) are sequentially assigned.

In this case, in the first time slot,
Shift register 7 of microcode register circuit 10E
2 (FIG. 4) outputs the respective instruction signals shown in the column of OP4 in FIG. That is, the microcode register circuit 10E to the FM operation circuit 10A supply the first feedback selection signal FBSEL1 of high level "1", the first feedback write signal FBW1 of high level "1", and the accumulator write signal of high level "1". AW, shift amount
A shift control signal SHIFT representing FBL1 and a filter control signal FC representing cutoff frequency FC4 are supplied. Therefore, the latch 52 and the gate 5 of the FM operation circuit 10A
7 (FIG. 3) is supplied with a high-level signal "1",
The waveform signal in the time slot is supplied to a feedback path for the first feedback FM operation (lats 52 and 53, a shift register 54, an adder 55, a latch 56 and a gate 57),
It circulates through the FM operation unit and the digital filter. The circulation of this waveform signal requires one operation cycle (64 operation time slots), the circulated waveform signal is shift-controlled by the shift amount FBL1 by the shifter 44, and the filter control signal is output by the multiplier 32.
In the first time slot, a waveform signal is formed by feedback FM calculation while the modulation index is controlled by the shift amount FBL1, and the frequency characteristic of the waveform signal is controlled by the cutoff frequency FC4. (See OP4 and filter 4 in FIG. 7).

In the first time slot, the accumulator write signal is supplied to the selector 46 (FIG. 2).
AW is supplied. On the other hand, since the accumulator selection signal representing "00" is supplied to the selector 48, the adder 4
5 passes the waveform signal from the shift register 34 as it is, and the waveform signal subjected to the feedback FM operation and the filtering operation is stored in a register 47 constituting an accumulator.

Next, at the second operation time slot,
Shift register 7 of microcode register circuit 10E
2 (FIG. 4) output the respective instruction signals shown in the column of OP3 in FIG. That is, the microcode register circuit 10E is supplied with the high level "1" temporary write signal TW and the filter control signal FC representing the cutoff frequency FC3 from the microcode register circuit 10E to the FM arithmetic circuit 10A. Accordingly, in the second time slot, no input signal is supplied to the OR circuit group 42, and the circuit group 42 outputs a signal representing "0". An FM operation using only the signals PD and AD is executed to form a waveform signal, and the frequency characteristic of the waveform signal is changed by a filtering operation according to the cutoff frequency FC3 (OP3 and filter 3 in FIG. 7). reference). In this case, since the high level "1" is supplied to the selector 36, the waveform signal subjected to the above-mentioned FM operation and subjected to the filtering operation is stored in the register 37 constituting the temporary register.

When the third time slot is reached, the shift register 72 of the microcode register circuit 10E outputs each instruction signal shown in the column of OP2 in FIG. That is, the microcode register circuit 10
From E to the FM operation circuit 10A, a register selection signal RSEL representing "10", an accumulator selection signal ASEL representing "01",
An accumulator write signal AW of high level "1", a shift control signal SHIFT indicating a shift amount OPIL2, and a filter control signal FC indicating a cutoff frequency FC2 are supplied.
Therefore, a selection signal representing "10" is supplied to the selector 38 (FIG. 2) of the FM operation circuit 10A, and the waveform signal calculated in the second time slot and stored in the register 37 is transmitted to the shift register 41, OR circuit group 4
2. The signal is supplied to the FM operation unit via the delay circuit 43 and the shifter 44. Thus, in the third time slot, the operation result of the second time slot is used as a modulation signal, and the exponent of the modulation signal is controlled by the shift amount OPIL2.
A waveform signal is formed by an FM operation using D and AD. Then, the frequency characteristic of the formed waveform signal is changed by a filtering operation according to the cutoff frequency FC2 (see OP2 and filter 2 in FIG. 7).

In the third time slot, the selector 48 is supplied with the selection signal representing "01" and, at the same time, the selector 46 is supplied with the high-level signal "1". In addition, the filtered waveform signal and the waveform signal (the operation result of the first time slot) previously stored in the register 47 are added by the adder 45 and newly stored in the register 47 constituting the accumulator. .

Next, in the fourth time slot, each instruction signal shown in the column of OP1 in FIG. 8 is output from the shift register 72 of the microcode register circuit 10E. That is, the microcode register circuit 10
The register selection signal RSEL representing "01" and the high-level "1" operation output transfer signal OPT are supplied to the FM operation circuit 10A from E.
Are supplied with a shift control signal SHIFT indicating a shift amount OPIL1 and a filter control signal CF indicating a cutoff frequency FC1. Therefore, the selector 38 of the FM operation circuit 10A
(FIG. 2) is supplied with a selection signal representing "01", and the waveform signal calculated in the third time slot and stored in the register 46 is transferred to the shift register 41, the OR circuit group 42, and the delay circuit 43. , And supplied to the FM operation unit via the shifter 44. Thus, in this fourth time slot, the operation result of the third time slot is used as a modulation signal, and the exponent of the modulation signal is controlled by the shift amount OPIL1, and each external signal
A waveform signal is formed by an FM operation using PD and AD. Then, the frequency characteristic of the formed waveform signal is changed by a filtering operation according to the cutoff frequency FC1. (See OP1 and Filter 1 in FIG. 7). In this case, since the high-level "1" signal is supplied to the output accumulator 10C, the operation result of the fourth time slot is taken into the output accumulator 10C.

On the other hand, the output accumulator 10C is cleared by the clear signal CL every one operation cycle (64 operation time slots), so that each tone signal supplied during one operation cycle is formed. The output waveform signal from the FM operation unit for each channel via the digital filter is accumulated every time the operation output transfer signal OPT arrives.
The accumulation result for each operation cycle is taken into the latch 10D by the output latch signal OL immediately before the clearing. The fetched signal is converted into an analog signal by a D / A converter 16 and supplied to a sound system 17, which generates a tone corresponding to the analog signal.

As described above, according to the above-described embodiment, the FM signal is obtained by using the waveform signal circulating in the circulation path including the FM arithmetic unit and the digital filter and the external waveform signal.
In addition to performing the calculation, the waveform signal subjected to the FM calculation is subjected to a filtering process using a digital filter to form an output tone waveform signal. And F
Using a simple waveform signal input from the outside by M operation to form a waveform signal with abundant harmonics,
A digital filter that can intuitively understand the control state of the harmonic component ratio is used to modify the formed waveform signal to create a sound, so that the tone of the musical tone signal can be easily and subtly changed. It is possible to easily obtain a tone signal of a desired tone. Further, since the shift register 34 serving as delay means in the digital filter is also used as delay means constituting a part of the circulation path, the configuration of the circulation path or the digital filter can be simplified.

In the above embodiment, the number m of musical tones that can be simultaneously generated (the number of tone signal forming channels) is set to 16, and the number n of operation time slots assigned to one tone signal forming channel is set to four. However, by changing the microcode supplied from the microcomputer 15 to the microcode register circuit 10E by the tone color selection and the modulation mode selection in the tone color etc. selection switch group 12, the numbers m and n are obtained. Is variously changed. For example, the number m of musical tones that can be simultaneously generated (the number of musical tone signal forming channels) m may be eight, and the number n of operation time slots allocated to one musical tone signal forming channel may be eight.

In the above embodiment, the sine wave table 22 is prepared for the modulation operation. Instead of the sine table 22, a table storing a square wave, a triangular wave, or any other waveform is prepared. You may do so.
Also, an instantaneous value of a waveform may be calculated and output by an arithmetic unit instead of a table.

In the above embodiment, a low-pass filter is used as a digital filter, but a high-pass filter or a band-pass filter may be used as the digital filter instead of or in addition to the low-pass filter. Further, this digital filter is not limited to the connection position in the above-described embodiment, and can be provided at a desired position in the circulation path of the waveform signal. Further, the filter control signal FC supplied to the digital filter may be fixed in time, or may be changed in time from generation of the tone signal to stop.

In the above embodiment, the feedback path of the FM operation unit delays the signal by one operation time slot more than one operation cycle. 66,6 more than slot
7... The signal may be delayed by the operation time slot. In this case, the operation time slots constituting one tone signal formation channel may be configured so as to be spaced by 1, 2,...

Further, the signal delay time of the first and second feedback operation systems of the above embodiment is not equal to 64 operation time slots (without taking into account the shift registers 54 and 62), but is 128, which is an integral multiple of 64. 192... It may be the number of operation time slots.

In the above embodiment, the tone signal is formed by the FM operation. However, the present invention provides a tone signal generating apparatus using various modulation operations such as the AM operation instead of the FM operation. Can also be applied. In this case, the FM operation unit in the above embodiment may be configured by a modulation operation unit that performs the various modulation operations.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an entire electronic musical instrument provided with a tone signal generating device according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram showing a part of the musical sound signal generator.

FIG. 3 is a detailed block diagram showing another portion of the musical tone signal generating device.

FIG. 4 is a detailed block diagram of the microcode register circuit of FIG. 1;

FIG. 5 is a time chart for explaining the operation of the musical sound signal generator.

FIG. 6 is a time chart for explaining the operation of the musical sound signal generator.

FIG. 7 is a connection diagram illustrating an example of a calculation mode of the musical sound signal generation device.

FIG. 8 is a data format of microcode for executing the same operation mode.

[Explanation of symbols]

10 ... tone signal generator, 10A ... FM arithmetic circuit, 10
B: timing control signal generator, 10C: output accumulator,
10E: microcode register circuit, 10F: pitch parameter register circuit, 10G: envelope parameter register circuit, 10H: key-on register circuit, 1
0I: phase data generator, 10J: envelope generator, 21, 23, 33, 45, 55, 63 ... adder, 2
2: Sine wave table, 24: Log / linear conversion table,
25 to 28, 43, 51: delay circuit, 31: subtractor, 3
2. Multiplier, 36, 38, 46, 48 ... Selector, 3
7, 47 ... register, 34, 35, 41, 54, 62 ...
Shift register, 42: OR circuit group, 44: shifter,
57, 65 ... Gate.

Claims (2)

(57) [Claims] 1. Each modulation in a plurality of operation time slots
A musical tone signal that repeats the operation to form one musical tone signal
In Patent generator, the first input terminal, Ri Na has a second input and output ends, and a waveform signal supplied to each operational time slot from the outer <br/> unit in the first input, Each operator is connected from the output terminal to the second input terminal .
One of each operation Times a running modulation operations waveform signal modulated from the output terminal for modulating the other waveform signal waveform signal with Shin Namikata that is fed back for each time slot
Modulation operation means for outputting for each lot , and interposed in a feedback path from an output end of the modulation operation means to a second input end, and
Obtained by the modulation operation in one operation time slot.
Waveform signal in another operation time slot.
From the same output terminal for each calculation time
Delay the waveform signal output for each lot to calculate each
Delay means for feeding back to each slot, the modulation from the output terminal of the operational means to the second input feedback path
And a part of the delay means is shared.
Frequency characteristics can be changed according to external control signals
A tone signal generator comprising: a filter . 2. A tone signal generating apparatus according to claim 1, wherein said delay means is provided when the input waveform signal is determined in advance.
A first delay means for delaying the input waveform signal by
Selectively hold and output to selectively set delay time
A second delay means which can be changed, and wherein the filter is provided with the first delay means in a predetermined manner.
And a third delay means for delaying the waveform signal by the time
Music signal generator composed of