JPH0560118B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a musical tone signal generating device used in a device that electrically generates musical tones, such as an electronic musical instrument. [Prior Art] A major challenge in electronic musical instruments is how to generate musical tones that are close to the musical tones of natural musical instruments. Various methods are known for forming musical sound shapes in electronic musical instruments, but among them, one method involves sequentially sampling each instantaneous value of a musical sound waveform of a natural musical instrument and storing it in a memory, and then using the stored sampling data. The method of reading out and generating musical tone signals (called the PCM (Pulse Code Modulation) method) is excellent because it can generate musical tones that are closest to natural musical tones. Note that this method is
It is disclosed in Publication No. 52-121313 (title of invention: electronic musical instrument). [Problems to be Solved by the Invention] The sound waveforms of natural musical instruments vary slightly depending on the pitch, range, etc. of the same instrument. For example, in the case of a piano, the musical sound waveform differs for each key, albeit slightly. Note that, of course, the period differs for each key, but the shape of the waveform itself other than the period also differs. Therefore, in order to generate musical sounds that are truly close to those of natural instruments using the PCM method, it is necessary to memorize instrument waveforms for each instrument and, if necessary, for each pitch. Memory capacity becomes extremely large. That is,
The PCM method is extremely superior in that it can generate musical tones close to those of natural instruments, but the memory capacity problem mentioned above has been a hindrance, preventing its practical application. Note that DPCM (Differential Pulse Code) is a method to reduce the amount of data stored in memory.
Modulation), ADPCM (Adaptive Differential
However, these methods still do not reduce the amount of data sufficiently, and furthermore, these methods have the disadvantage that they cannot faithfully reproduce the original waveform. be. This invention was made in view of the above circumstances,
The purpose of this device is to create a musical tone signal generator that memorizes each instantaneous value of the musical sound waveform of a natural musical instrument.Moreover, it can significantly reduce the memory capacity compared to conventional methods, and can faithfully reproduce the original waveform. An object of the present invention is to provide a musical tone signal generating device that can reproduce musical tone signals. [Means for Solving the Problems] This invention obtains residual data as the difference between sampling data obtained by sampling a musical sound waveform and predicted data calculated from a plurality of sampling data, and calculates residual data itself. , or data corresponding to this residual data is stored in memory. Then, when a musical tone signal is generated, data in the memory is read out, and sampling data is reproduced based on the read data to obtain a musical tone signal. Here, at the beginning when a musical tone signal is generated, a plurality of initial sampling data are set in the reproduction means. [Operation] According to the present invention, not the sampling data itself, but the residual data that is the difference between the sampling data and the predicted data, or the data corresponding to this residual data, is stored in the memory. In this case, the residual data or data corresponding to the residual data has a much smaller value than the sampling data, and therefore the number of bits is also much smaller than the sampling data. Furthermore, in the present invention, since the initial sampling data is set in the reproducing means, accurate musical tone signals can be reproduced even at the beginning of musical tone signal generation. [First Embodiment] FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. 1 shows a musical tone signal generating device that reads out data from the internal memory and generates a musical tone signal. In Figure 1A, code 1 is an ADC (analog/
It is a digital converter) that sequentially samples the musical tone signal F(t) of a natural musical instrument at the timing of the clock pulse φ, and converts this sampled data (analog data) into digital sampling data F.
(n) and gradually become the mainstay. The predicted data generation circuit 2 generates predicted data FY(n) based on the sampling data F(n) and outputs it to the subtraction circuit 3. Here, the prediction data FY(n) is created based on the formula, for example, FY(n)={F(n-1)+F(n+1)}/2 (1). That is, if the curve shown in FIG. 2 is the musical tone signal F(t), the times t(n-1), t(n), t(n+1), t(n+
2), sampling data F(n-1), F(n), F(n+1), F(n+2) from ADC1, respectively.
)
are output respectively. The predicted data generation circuit 2 generates sampling data F at time t(n+1).
(n-1) and the sampling data F(n+1) supplied at that point are added, and the addition result is divided by "2" to create predicted data FY(n) and output. Similarly, at time t(n+2), sampling data F(n) and F(n+2)
Predicted data FY(n+1) is created from this and output. The subtraction circuit 3 delays the sampling data F(n) by one bit time of the clock pulse φ, and subtracts the predicted data FY(n) from the delayed data to create residual data D(n). That is, at time t(n+1), this subtraction circuit 3 creates and outputs residual data D(n) by the calculation D(n)=F(n)-FY(n) (2). Here, the residual data D(n) has a much smaller value than the sampling data F(n), as is clear from FIG. ) requires fewer bits than that of ). Therefore, the residual data D(n) mentioned above is stored in the memory M
are sequentially written within. Next, in FIG. 1B, reference numeral 5 denotes a sampling data reproducing circuit that reads residual data D(n) from the memory M and reproduces sampling data F(n) based on the read data D(n). be. This circuit 5 will be explained below. The above equation (1) can be transformed into
By substituting into equation (2), the following equation is obtained: D(n)=F(n)-{F(n-1) +F(n+1)}/2...(3). By transforming this equation (3), the following equation can be obtained: F(n+1)=2{F(n)−D(n)} −F(n−1) (4). The sampling data reproducing circuit 5 reproduces the sampling data F(n) based on this equation (4). That is, the sampling data F(n) is now stored in the sampling data reproducing circuit 5.
It is assumed that initial values F(0) and F(1) of are stored in advance. The reproduction circuit 5 first sets the initial value F(0)
and F(1) are sequentially output according to the clock pulse φ, and the residual data D read out from the memory M.
Calculate equation (4) based on (1). In other words, subtract data D(1) from data F(1), multiply this subtraction result by 2, and use this multiplication result to obtain data F(0).
Subtract. Through the above calculation, sampling data F(2) is obtained. The reproducing circuit 5 sets the sampling data F(2) obtained in this way to an initial value F.
(0) and F(1), and then output to a DAC (digital/analog converter) 6. Next, when one bit time of the clock pulse φ has elapsed, the reproducing circuit 5 performs the calculation of equation (4) based on the residual data D(2) read from the memory M, and uses the sampling data obtained thereby. Output F(3) to DAC6. Thereafter, the process is repeated in the same manner, whereby the sampling data F(n) is sequentially supplied to the DAC 6. The DAC 6 converts the sequentially supplied sampling data F(n) into an analog signal and outputs it.
In this way, a signal identical to the musical tone signal F(t) (however, a quantization error exists) is output from the DAC 6. The specific configurations of the predicted data generation circuit 2 and the sampling data reproduction circuit 5 will be easily understood from the configuration of the second embodiment described below. The details of the embodiment shown in FIG. 1 have been described above. According to this embodiment, the storage capacity of the memory M can be significantly reduced compared to the conventional one, and moreover, the sampling data F(n) can be reproduced as is in the sampling data reproduction circuit 5. [Second Embodiment] FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. 3A shows the configuration of a data write circuit for writing data into the memory M.
FIG. 3(b) shows the configuration of a musical tone signal generation circuit which reads data in the memory M and generates musical tone signals. The second embodiment is a further improvement of the first embodiment described above, and the improvements include the following two points. First point: The sound waveforms of natural musical instruments have periodicity. The first improvement was made by focusing on this periodicity. In the first embodiment, the residual data D(n) was stored as is in the memory M, but this second improvement was made by focusing on this periodicity.
In the embodiment, the memory M stores the difference between the residual data D(n) and the residual data D(n) from one cycle before (hereinafter referred to as residual data E(n)). ing. This will be explained in detail below. Let us now assume that the waveform shown in FIG. 4 is the waveform of the musical tone signal F(t) of a natural musical instrument, and let time t(00) be the musical tone generation start time. In this case, the sample point time t(K) ₁ with the first period T1
and _the residual data D(n) ₂ at a sample point time t(K) ₂ (of the same phase) corresponding to time t(K) ₁ in the second period T2. The difference is extremely small. Similarly, residual data D(K) ₂ at time t(K) ₂ and residual data D(K) ₃ at time t(K) ₃
The difference is also extremely small. Therefore, in the second embodiment shown in FIG. 3, the residual data D(n) at the corresponding sampling point one cycle before is subtracted from the calculated residual data D(n), and the result of this subtraction, i.e. , residual difference data E(n) are written into the memory M (see FIG. 4). Note that in the first period T1, the residual data D(n) from one period before does not exist, so the residual data E(n) ₁ is the same data as the residual data D(n) ₁ . Therefore, the value of the residual difference data E(n) is much smaller than the value of the residual data D(n), and therefore the amount of data stored in the memory M can be further reduced than in the first embodiment. . In addition, the residual difference data E
To reproduce sampling data F(n) from (n),
This can be realized by a simple circuit as described later. Second point: The second point of improvement is the method of calculating the predicted data FY(n). That is, in the first embodiment, the predicted data FY(n) was calculated from the two sampling data F(n-1) and F(n+1), but (see equation (1)), this In the second embodiment,
The predicted data FYa(n) is divided into four sampling data F(n-2), F(n-1), F(n+1), (n+
It is calculated from 2). This calculation method will be explained below using FIG. 5. First, sampling data F(n-2), F(n
-1), predicted data P(n-1) from sampling data F(n-1) and F(n+1), and sampled data F(n+
1) Calculate predicted data P(n+1) from F(n+2). This calculation is based on the following formula. P(n-1)=F(n-1) +{F(n-1)-F(n-2)} ...(5) P(n)={F(n-1) +F(n+1)} /2...(6) P(n+1)=F(n+1) +{F(n+2)-F(n+1)}...(7) Next, these predicted data P(n-1), P(n),
P(n+1) is multiplied by weighting coefficients of "1", "2", and "1" and then added, and the result of this addition is "4".
Find the predicted data FYa(n) by dividing by FYa(n)={P(n-1)+2P(n)+P(n+1)}/4...(8) The above is the basic idea of the method for calculating the prediction data FYa(n). Substituting Equations (5) to (7) above into Equation (8) above and rearranging, we get FYa(n)={-F(n-2)+3F(n-1)+3F(n
+1)-F(n+2)}/4...(9) The formula is obtained. That is, in the second embodiment, the predicted data FYa(n) is calculated based on this equation (9).
is calculated. Therefore, according to the calculation method described above, it is possible to calculate prediction data FYa(n) that is closer to the actual sampling data F(n) compared to the calculation method of prediction data FY(n) in the first embodiment described above. Therefore, the value of the residual data D(n) becomes smaller, and the number of bits can be reduced. In addition,
The above-mentioned weighting coefficient is based on the sampling data F
(n) and the predicted data FY(n) is minimized,
For example, it may be determined using least squares prediction. The above are the improvements in the second embodiment. Next, the specific structure of this second embodiment will be explained with reference to FIGS. 3A and 3B. First, in Figure 3 A,
The musical tone signal F(t) of a natural musical instrument is converted into sampling data F(n) by the ADC 1 and supplied to the residual data generation circuit 11. Residual data generation circuit 1
1. This corresponds to the predicted data generation circuit 2 and the subtraction circuit 3 in FIG. That is, D(n)=F(n)−FYa(n) (10) is calculated and output. Substituting the above equation (9) into this equation (10) and rearranging, we get D(n)={F(n-2)-3F(n-1) +4F(n)-3F(n+1)+F( n+2)}/4...(11) The following equation is obtained. The residual data generation circuit 11 is
The residual data D(n) is calculated by calculating this equation (11) and output. That is, in the residual data generation circuit 11,
Reference numerals 12 to 16 are DFFs (delay flip-flops) each triggered by a clock pulse φ.
The sampling data F(n) is sequentially read into these DFFs 12 to 16 in accordance with the clock pulse φ. The output of each DFF12 to 16 is
It is supplied to multipliers 17 to 21, and the output signals are "1/4" and "-".
3/4'', ``1'', ``-3/4'', and ``1/4'' are multiplied, and each multiplication result is added in the adder 22,
It is output as residual data D(n). Note that the multipliers 17 to 21 can be easily constructed using data shift circuits, adders, and the like. Therefore, at sampling time t(n+2), DFF12 to 1
6 contains sampling data F(n+2) and F
(n+1), F(n), F(n-1), and F(n-2) are read, and therefore, the residual data D(n) of equation (11) is output from the adder 22. Ru. The configuration of this residual data generation circuit 11 is the same as that of a linear phase FIR filter, which is a type of digital filter. Next, the residual data D output from the adder 22
(n) is supplied to the input terminal of the subtracter 23. The subtracter 23 subtracts the data supplied to its input terminal from the data supplied to its input terminal, and outputs the result of this subtraction as residual difference data E(n). In other words, the subtracter 23 is a circuit that subtracts the residual data D(n) from one cycle (one cycle of the musical tone signal F(t)) from the residual data D(n) output from the adder 22. ,
The output data of the shift register 24 is supplied to its input terminal via an AND gate 25. The shift register 24 is a register for holding the residual data D(n) for one period, and has stages equal to the number of sample points in one period, and the residual data D(n) supplied at the input terminal IN is clocked. Read sequentially based on φ. The read data D(n) is sequentially shifted within the shift register 24 and output from the output terminal Q after one cycle has elapsed. Thus, in the first period T1 (see FIG. 4) of the musical tone signal F(t), the signal IC becomes a "1" signal.
As a result, the inverter 27 outputs a “0” signal, and the AND gate 25 outputs data “0”. As a result, the residual data D(n) ₁ output from the adder 22 is directly output from the subtracter 23 as residual difference data E(n) ₁ . This residual difference data E(n) ₁ is sequentially written into the memory M and is also supplied to the adder 28. Adder 28
adds the residual difference data E(n) ₁ (=D(n) ₁ ) and the output data "0" of the AND gate 25, and sequentially shifts this addition result, that is, the residual data D(n) ₁ It is supplied to the input terminal IN of the register 24. This residual data D(n) ₁ is sequentially read into the shift register 24. Next, in the second period T2, the signal IC is “0”
Fall at the signal. Note that the signal IC continuously maintains the "0" signal state from then on. When the signal IC becomes a “0” signal, the AND gate 25 becomes open, and the residual data D(n) ₁ in the shift register 24 is sent to the input terminal of the subtracter 23 and the adder 28 via the AND gate 25. Supplied to the input end. As a result, the second
In period T2, the subtracter 23 outputs residual difference data E(n) ₂ as follows: E(n) ₂ = D(n) ₂ −D(n) ₁ ...(12), and this data E(n ) ₂ is written into memory M, and adder 28
From, E(n) ₂ +D(n) ₁ = D(n) ₂ −D(n) ₁ +D(n) ₁ = D(n) ₂ …(1
3) Data, that is, residual data D(n) ₂ is output, and this residual data D(n) ₂ is sent to the shift register 24.
are read sequentially within. The same process is repeated, and as a result,
Residual difference data E(n) ₁ , E(n) ₂ , . . . are sequentially written into the memory M. Note that the circuit in the lower half of FIG. 3A can also be configured as shown in FIG. 6. According to the configuration shown in FIG. 6, the adder 28 in FIG. 3A can be omitted. Next, in FIG. 3B, the residual difference data E(n) read from the memory M is supplied to one input terminal of the adder 31. Note that reading from the memory M is of course performed at the timing of the clock pulse φ. The adder 31 and the shift register 32 are for returning residual difference data E(n) to residual difference data D(n). That is, first, at the timing when data E(n) ₁ (=D(n) ₁ ) is read out from the memory M for each residual difference of the first period T1, the signal IC becomes a "1" signal, and therefore A “0” signal is output from the inverter 33, and data “0” is output from the AND gate 34.
is output. This data “0” is then supplied to the other input terminal of the adder 31. As a result, residual data D(n) ₁ is output from the adder 31 and supplied to the sampling data reproducing circuit 35 and the shift register 32. The shift register 32 has the same structure as the shift register 24 described above (FIG. 3A), and sequentially reads and shifts the supplied various difference data D(n) ₁ , and outputs it from the output terminal Q after one cycle. Next, at the timing when each residual difference data E(n) ₂ of the second period T2 is output from the memory M, the signal IC becomes a "0" signal. From now on, this signal
The IC continues to have a “0” signal state. When the signal IC becomes a "0" signal at the above timing, the AND gate 34 becomes open, and the residual data D(n) ₁ in the shift register 32 passes through the AND gate 34 to the other input terminal of the adder 31. Supplied sequentially. As a result, from the adder 31, E(n) ₂ +D(n) ₁ =D(n) ₂ -D(D ₁ )+D(n) ₁ =D(n) ₂
...(14), that is, residual data D(n) ₂ is output, and this residual data D(n) ₂ is supplied to the sampling data reproducing circuit 35 and sequentially read into the shift register 32. Thereafter, similar operations are repeated, whereby residual data D(n) ₁ , D(n) ₂ , . . . are sequentially supplied to the sampling data reproducing circuit 35. The sampling data reproducing circuit 35 is a circuit that reproduces sampling data F(n) from residual data D(n). The residual data D(n) is created based on the above-mentioned equation (11). Transforming this equation (11), F(n+2)=-F(n-2)+3F(n-1)
The following formula is obtained: -4F(n)+3F(n+1)+4D(n)...(15). The sampling data reproducing circuit 35 reproduces the sampling data F(n) based on this equation (15). To explain in detail below, in the sampling data reproducing circuit 35, numerals 36 to 39 are DFFs, and 40 to 39 are DFFs.
44 is a multiplier, and 45 is an adder. Now, consider the point in time when the adder 31 outputs the residual data D(2). Also, at this point, the initial values F(0), F(1), and
Assume that F(2) and F(3) are each stored. In this case, the coefficients "-1", "3", "-" are applied to the above-mentioned initial values F(0) to F(3) in multipliers 44 to 41, respectively.
4" and "3" are multiplied, and this multiplication result is sent to adder 4.
5. Further, the residual data D(2) is multiplied by a coefficient “4” in the multiplier 40, and the result of this multiplication is supplied to the adder 45. As a result, at the time when the residual data D(2) is output from the adder 31, the output data of the adder 45 is -F(0)+3F(1)-4F(2)+3F(3)+4D(2 )…(16) becomes. As is clear from equation (15), this data is sampling data F(4). That is, when the residual data D(2) is output from the adder 31, the sampling data F(4) is output from the adder 45 and supplied to the input ends of the DAC 46 and the DFF 36. Next, when the residual data D(3) is output from the adder 31 after one bit time of the clock pulse φ, at this point, each of the data F
Since (4) to F(1) are read, from the adder 45, the data becomes -F(1)+3F(2)-4F(3)+3F(4)+4D(3)...(17), i.e. Sampling data F(5) is output. Below, the residual data D from the adder 31
(4), D(5)... are sequentially output from the adder 45 in the same manner as in the above case.
(6), F(7)... are sequentially output and supplied to the DAC 46. As a result, a signal identical to the musical tone signal F(t) of a natural musical instrument is obtained as the output of the DAC 46.
The sampling data reproducing circuit 35 described above has the same configuration as an IIR filter, which is a type of digital filter. The above are the details of the second embodiment. Note that in the first embodiment described above, the prediction data FY(n) is divided into past data F(n-1) and future data (n
+1), and in the second embodiment, the predicted data FYa(n) is calculated from the past data F(n-
2), F(n-1) and future data F(n+
1), the prediction data is obtained from the bottom (n+2), but this prediction data may be obtained only from past data, for example. In addition, in the explanation of FIG. DFF during playback
39 to 36 may be reset respectively. In this case, the sampling data F(n) cannot be correctly reproduced for the rising edge data, but the subsequent data can be correctly reproduced. In addition, in the above embodiment, the residual data E
(n) is obtained by calculating the difference between the residual data D(n) of each period and the residual data D(n) of one period before, but the method is not limited to this. , 2 cycles or 1/2 cycle ago). For this purpose, the number of stages of the shift registers 24 and 32 in FIGS. 3A and 3B may be set in accordance with the number of sample points within a predetermined period. In this case, the shift register 24,
32, a memory such as a RAM may be used to delay the residual data D(n). By the way, in the first and second embodiments described above, the amount of data to be stored in the memory M can be further reduced by adding a special circuit. That is, the residual data D(n) or the residual difference data E(n) to be stored in the memory M is further stored in Shannon.
- It is sufficient to convert it into a Fano code or a Huffman code and store it in the memory M. Below is a brief explanation of Huffman codes. For example, in the first embodiment, the residual data D
The probability of occurrence of each type of (n) (0, ±1, ±2...) is different. The Huffman code is a code that focuses on the probability of occurrence, and assigns a code with a small number of bits to data with a high probability of occurrence. Note that the Shannon-Fano code is based on the same idea. Table 1 shows the residual data D
3 is a table showing an example of the relationship between the value of (n) and the Huffman code HC.

[Application example]

Next, an application example of the musical tone signal generating device according to the first embodiment described above will be explained. FIG. 7 is a block diagram showing an example of the configuration of an electronic musical instrument to which the musical tone signal generating device is applied. In this figure, the residual memory M stores the residuals of the entire waveform of the musical tone signal F(t) from the rise to the end, for example, for each tone (piano tone, flute, etc.) and for each pitch type. Difference data D
(n) is memorized. When one of the timbres is selected by the timbre selection section 50, the output data TC of the timbre selection section 50 causes the memory M in which the residual data D(n) corresponding to that timbre is stored.
storage area is specified. Next, when any key on the keyboard 51 is pressed, the key press detection section 52 detects this and outputs the key code KC of the pressed key and a key-on signal KON.
This key-on signal KON continues to be a "1" signal while the key is pressed. The address generator 53 is
The key code KC output from the key press detection unit 52 is converted into the corresponding address data AD1 and output to the residual memory M, and after the key-on signal KON rises to the “1” signal, the key code KC is changed to 0, 1. , 2 . . . address data ADD which changes sequentially is output to the residual memory M. When the address data AD1 is supplied to the residual memory M, the address data in the storage area specified by the data TC mentioned above is
The area corresponding to AD1 is specified. This area is
It has a tone selected by the tone selection section 50,
This is an area where the residual data D(n) of the musical tone signal F(t) having the pitch of the key code KC output from the key press detection section 52 is stored. Then, when the address data ADD is supplied to the residual memory M, the residual data D(n) in the relative address 0 of the area is sequentially read out and sequentially supplied to the sampling data reproducing circuit 5. As a result, sampling data F(n) is sequentially output from the sampling data reproduction circuit 5, and the output data F(n) is converted into a musical tone signal (analog signal) by the DAC 6 and supplied to the sound system 54. . sound system 5
4 amplifies the supplied musical tone signal and produces a musical tone from a speaker. Note that if pitch changes such as vibrato are to be added to the generated musical tone, the output timing of the address data ADD may be changed. In this case, data processing within the sampling data reproducing circuit 5 is also synchronized with the output timing of the address data ADD. Also, instead of storing residual data D(n) for each pitch, one set of residual data D(n) is stored for all pitches, or one set for each pitch is stored. When storing residual data D(n), address data
The output timing of ADD may be set to a speed corresponding to the key code KC. [Effects of the Invention] As explained above, according to the present invention, residual data or data corresponding to the residual data is stored in a memory in advance, and while an initial value is set in the reproduction means, the data in the memory is Since the musical tone signal is generated (formed) by reading out the data, it is possible to significantly reduce the memory capacity compared to conventional methods while maintaining the real-time performance required of electronic musical instruments, and moreover, it faithfully reproduces the original waveform. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a diagram for explaining predicted data FY(n) and residual data D(n) in the same embodiment, and FIG. The figure is a block diagram showing the configuration of a second embodiment of the present invention, FIG. 4 is a diagram for explaining the residual difference data E(n) in the same embodiment, and FIG. 5 is the predicted data in the same embodiment. A diagram for explaining FYa(n), Figure 6 is a block diagram showing other configuration examples of the circuit shown in Figure 3 A, and Figures 7 and 8 are experiments of the circuit shown in Figure 3 A. FIG. 9, a diagram showing an example of the results, is a block diagram showing the configuration of an electronic musical instrument to which the first embodiment shown in FIG. 1 is applied. 5, 35...Sampling data reproduction circuit, M
……memory.

Claims (1)

[Claims] 1 (a) Residual data that is the difference between sampling data obtained by sampling a musical sound waveform and predicted data calculated from a plurality of said sampling data, or data corresponding to this residual data (b) reproducing means for reproducing the sampling data by reading data in the memory and adding the read data to predicted data calculated based on previously read data; In the musical tone signal generation device, the musical tone signal generation device is configured to generate a musical tone signal based on the sampling data reproduced by the reproduction means, wherein a plurality of initial sampling data are set in the reproduction means when starting musical tone reproduction. . A musical tone signal generating device, wherein the reproduction means calculates the predicted data from the plurality of initial sampling data. 2. The musical tone signal generating device according to claim 1, wherein the data corresponding to the residual data is a difference between the residual data at the sampling point and the residual data at the sampling point a predetermined period before.