JPS6190198A - Musical sound signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a musical tone signal generating device used in a device that electrically generates musical tones, such as an electronic musical instrument.

[Prior art]

A major challenge for electronic musical instruments is how to generate musical tones that are close to those of natural musical instruments. Various methods are known for forming musical tones in electronic musical instruments, but among them, there is a method in which each instantaneous value of a musical sound waveform of a natural musical instrument is sequentially sampled and stored in a memory, and the stored sampling data is CPCM (Pulse Code Modula)
tion> method) is superior in that it can generate musical tones that are closest to natural musical tones. This method is disclosed in Japanese Unexamined Patent Publication No. 121313/1983 (title of invention:
electronic musical instruments).

(Problem to be solved by the invention) The sound waveforms of natural musical instruments differ slightly depending on the pitch or range, etc., even for the same instrument.For example, in the case of a piano,
Although slightly different, the sound waveform for each key is different. Note that, of course, the period of the waveform differs for each key, but the shape of the waveform itself other than the period also differs. Therefore, in order to generate musical sounds that are truly close to those of natural instruments using the PCM method, the instrument waveform must be stored for each instrument and, if necessary, for each pitch, resulting in an extremely large memory capacity. It becomes huge. In other words, the PCM method is extremely superior in that it can generate musical sounds close to those of natural instruments, but the problem of memory capacity mentioned above becomes a bottleneck.
Practical application was hindered.

Note that as a method to reduce the amount of data stored in memory, DPCM (DiHeretical Pulse
Code Modulation), ADPCM (A
adaptive DiHeretical Pu
1se Code Modulation), but these methods still do not sufficiently reduce the amount of data, and furthermore, these methods have
It has the disadvantage that it cannot faithfully reproduce the original waveform.

The present invention was made in view of the above circumstances, and its purpose is to provide a musical tone signal generator that generates each instantaneous value of a musical sound waveform of a natural musical instrument. It is an object of the present invention to provide a musical tone signal generating device that can reduce the number of waveforms and faithfully reproduce the original waveform.

(Means for Solving the Problem) This invention obtains residual data as the difference between sampling data obtained by sampling a musical sound waveform and predicted data calculated from a plurality of sampling data, and this residual data itself, Alternatively, data corresponding to this residual data is stored in the memory.Then, when the Tomei signal is generated, the data in the memory is read out, and based on this read data, the sampling data is reproduced to generate the musical tone signal (q). .

[Effect]

According to this invention, instead of the sampling data itself, the residual data that is the difference between the sampling data and the predicted data, or the data corresponding to this residual data, is stored in the memory. In this case, the residual data or the data corresponding to the residual data has a much smaller value than the sampling data, and therefore the number of bits is also much smaller than the sampling data.

[First Embodiment] FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. ) indicates a musical tone signal generating device that reads data in the memory M and generates musical tone signals.

In Fig. 1 (A), reference numeral 1 is an ADC (Analog/Digital Converter), which converts the musical tone signal F ([) of a natural musical instrument.
is sequentially sampled at the timing of the clock pulse φ, and this sampled data (analog data) is converted into digital sampling data F (n) and is sequentially used as main power. The predicted data generation circuit 2 generates predicted data FY (n) based on the sampling data F(n), and outputs it to the subtraction circuit 3. Here, the predicted data FY(
n) - As an example, F, Y (n) = (F (n-1) + F (n +
1))/2...(1) It is created based on the following formula. That is, if the 1° curve shown in FIG. 2 is the musical tone signal F (t), then the times t (n-1), t (n), t (
sampling data F(n-1), F(n), F(n+1) from ADCl at t(n+1) and t(n+2), respectively.
), F (n +2) are output. At time t(n+1), the predicted data generation circuit 2 adds the sampling data F(n-1> and the limbling data F(n-+l) supplied at that time, and converts the addition result into "2". Prediction data FY (n) is created and output by dividing by The subtraction circuit 3 delays the sampling data F(n) by one bit time of the clock pulse φ, subtracts the predicted data FY(n) from this delayed data, and outputs the residual data D(n). In other words, this subtraction circuit 3 creates D (n) −F (n) −FY (n)−< at time t (n+1).
2) The residual data D(n') is created and output by the following calculation. Here, the residual data D (n) has a much smaller value than the sampling data F (n), as is clear from FIG. The number of bits is less than the number of bits.

Therefore, the residual data D (n) described above is stored in the memory M
are sequentially written within.

Next, in FIG. 1(b), reference numeral 5 reads the residual data D (n) from the memory M, and the read data D
(n) based on the sampling data F (n)
This is a sampling data reproducing circuit that reproduces. below,
This circuit 5 will be explained. By substituting the above-mentioned equation (1) into equation (2), we get D(n)=F(n)−(F(n
-1> +F (n +1>)/2... (3) is obtained. If we transform this equation (3), we can obtain F (n
+1)=2 (F(n)-D(n))-F
(n-1)...(4) The following formula is obtained. The sampling data reproducing circuit 5 is
Based on this equation (4), sampling data F(+1
) is played. That is, it is now assumed that initial values F(0) and F(1) of sampling data F (n) are stored in advance in the sampling data reproducing circuit 5. First, the reproducing circuit 5 initializes the initial values F(0) and F(1
) are sequentially output according to the clock pulse φ, and the (4th
) performs the calculation of the expression. That is, data D(1) is subtracted from data F(1), this subtraction result is multiplied by 2, and data F(0) is subtracted from this multiplication result.

By the above calculation, the sampling data F(2) becomes 19
It will be done. The reproducing circuit 5 converts the thus obtained sampling data F(2) into initial values F(0) and F(1).
Subsequently, the signal is output to a DAC (digital/analog converter) 6. Next, the reproduction circuit 5 receives 1 of the clock pulse φ.
When the pit time has elapsed, the calculation of equation (4) is performed based on the residual data D(2) read from the memory M, and the sampling data F(3) obtained thereby is
Output to AC6. The same process is repeated thereafter, and the sampling data F (n) is sequentially transferred to the DAC6.
supplied to The DAC 6 converts the sequentially supplied sampling data F (n) into an analog signal and outputs it. In this way, a signal (
However, a quantization error exists) is output from the DAC 6. The specific configurations of the predicted data generation circuit 2 and the sampling data reproduction circuit 5 will be easily understood from the configuration of the second embodiment described below.

The details of the embodiment shown in FIG. 1 have been described above. According to this embodiment, the storage capacity of the memory M can be significantly reduced compared to the conventional one, and moreover, the sampling data F (n) can be reproduced as is in the sampling data reproduction circuit 5.

[Second Embodiment] FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. Figure 3 (b)
is in charge of the configuration of a musical tone signal generation circuit that reads data in memory M and generates musical tone signals.

The second embodiment is a further improvement of the first embodiment described above, and the improvements include the following two points.

First point: The sound waveforms of natural musical instruments have periodicity. The first improvement was made by focusing on this periodicity, and in the first embodiment, the residual data D (n) is stored in the memory M.
However, in this second embodiment, the difference between the residual data D (n) and the residual data D (n) one cycle before (hereinafter referred to as residual data) is stored in the memory M. E(n)) is stored. This will be explained in detail below. Now, the waveform not shown in FIG. 4 is the waveform of the musical tone signal F (t) of a natural instrument, and the time t (00)
Let be the musical sound generation start time. In this case, residual data D(
The difference between the residual data D(K)2 at the sample point time t(K)2 (of the same phase) corresponding to time j(K)+ in the second period T2 is extremely small. . Similarly, residual data D(K)2 at time L(K)2
The difference between the residual data D(K)3 at time j (KHz) is also extremely small.

Therefore, in the second embodiment shown in FIG. 3, the residual data D (n) at the corresponding sampling point one cycle before is subtracted from the calculated residual data D (n), and the result of this subtraction, i.e. , residual difference data E(n) are written into the memory M (see FIG. 4). Note that in the first period T1, the residual data D(n) from one period before does not exist, so the residual data E(rl)+ is the same data as the residual data D(rl)+.

Therefore, the value of the residual difference data E (n) is much smaller than the value of the residual data D (n), and therefore, the amount of data to be stored in the memory M can be made even smaller than in the first embodiment. Note that reproducing the sampling data F(n,) from the residual data E(n) can be realized by a simple circuit as described later.

Second point: The second improvement is the method of calculating the prediction data FY (n). However, in the first embodiment, the prediction data FY (n) is divided into two sampling data F(
n-1) and F(n+1>) ((1st)
(see formula), and in this second embodiment, the prediction data FY
a(n) as four sampling data F (n-2),
It is calculated from F(n-1>, F(n+1>, (n+2>). This calculation method will be explained below using FIG. 5.

First, sampling data F(n-2>, F(n-1>
, the predicted data P (rl-1> is obtained from the sampling data F (n-1), F (n +1>), and the predicted data P is obtained from the sampling data F (n-1), F (n +1>
(n), and the sampling data F (n +1)
, F (n+2) to calculate predicted data P(n+1>, respectively. This calculation is based on the following equation.

P(n-1)-F(n-1) +(F(n-1)-F(n-2)l...(5)P(n)
=(F(n-1) +F(n+1)')/2...
(6) P (n +1>=F (n +1) −(F(n+2)−F(n+1))・ (7) Next, these predicted data P(n−1>, , P(n), P(n+
1) is weighted by rIJ, r2J, and rIJ, respectively, by multiplying them by coefficients, and dividing this addition result by "4" to obtain predicted data FYa(n).

FYa (n)=(P(n-1)+2P(n)+P
(n+1))/4...(8) The above is the basic idea of the calculation method of the prediction data FYa(n). Substituting the above equations (5) to (7) into the above equation (8) and rearranging, FYa (n) = (-F (n -2) +3
F (n -1> +3F (n +1) -F (
n + 2) )/4... (9) The following formula is obtained. In the second embodiment,
The predicted data "Ya(n)" is selected based on this equation (9).

According to the above calculation method, the predicted data FYa(n) which is closer to the actual sampling data F(n) is calculated compared to the method of ejecting the predicted data FY(n) in the first embodiment described above. Therefore, the value of the residual data D (n > is smaller, and the number of bits can be reduced. J3.11) The weighting coefficient described in J3.11 is ) and the predicted data FY(n) may be determined using, for example, least squares prediction or the like.

The above are the improvements in the second embodiment. Next, the specific configuration of this second embodiment is shown in FIG. 3(a).

This will be explained with reference to (b). First, in FIG. 3(A), the musical tone signal F([) of a natural musical instrument is converted into lean-pulling data F (n) by ADCl, and is supplied to the residual data generation circuit 11. Residual data generation circuit 11
corresponds to the predicted data generation circuit 2 and the subtraction circuit 3 in FIG.
(n) to the aforementioned predicted data FYa (n)
Residual data D(n) after subtracting , that is, D(n)=F(n)−FYa(n
) ・Calculate and output (10). Substituting the above equation (9) into this equation (10) and rearranging, we get D(n)-(F(n-2>-3F(n-1)+4F (
n ) -3F (n +1) +F (n +2)
)/4...(11) The following formula is obtained. The residual data generation circuit 11 calculates the residual data D(n) by calculating the equation (11), and outputs the residual data D(n).

That is, in the residual data generation circuit 11, the code 12
~16 are each D triggered by a clock pulse φ
These are FFs (delay flip-flops), and sampling data F (n) is sequentially read into these 0FFs 12 to 16 in accordance with a clock pulse φ. Each DFF
The outputs of I2-16 are supplied to Dongfengki 17-21, respectively, and the outputs are "1/4J.

r-3/4J, rlJ, r-3/4J, r
1/4J is set to 1, and each multiplication result is Q-added in an adder 22 and output as residual data D (n).

Note that the multipliers 17 to 21 can be easily constructed using data shift circuits, Q adders, and the like. Therefore, at numbering time t(n+2>, DFFI 2 to 16
respectively have sampling data F(n +2) and F(
n +1), F (n >, F (n -1), F
(n-2) is read, and therefore, the adder 22 outputs the residual data D (n) of equation (11). The configuration of this residual data generation circuit 11 is the same as that of a linear phase FIR filter, which is a type of digital filter.

Next, the residual data D(n) output from the adder 22 is supplied to the input terminal (2) of the subtracter 23. The subtracter 23 subtracts the data supplied to the θλ input terminal from the data supplied to the ■ input terminal, and converts this subtraction result into residual difference data E (
n).

This subtracter 23 calculates one period (musical tone signal F (n) from the residual data D (n) output from the adder 22).
This is a circuit for subtracting the residual data D (n) one period before t), and the output data of the shift register 24 is supplied to its e input terminal via an AND gate 25. The shift register 24 is a register for holding the residual data D (n) for one cycle, and has stages equal to the number of sample points in one cycle, and holds the residual data D (n) supplied to the input terminal IN. Read sequentially based on clock pulse φ. The read data D(0) is transferred to shift register 2.
4, and after one period, the output terminal Q
is output.

Therefore, the first period T1 (fourth period T1) of the musical tone signal F (t)
(see figure), the signal IC becomes a "1" signal.

As a result, the inverter 27 outputs a “0” signal, and the AND gate 25 outputs data rOJ. As a result, the residual data D(n) output from the adder 22
+ is directly output from the subtracter 23 as residual data E(n)+. Then, this residual difference data E (n
)+ are sequential memories M1. :I and is also supplied to the adder 28. The adder 28 adds residual difference data E (
n )+ (=D (11)+ ) and AND gate 2
5 is added to the output data "0", and the addition result, that is, the residual data D(n)+ is sequentially supplied to the input terminal IN of the shift register 24. This residual data D (n)l
are sequentially read into the shift register 24.

Next, in the second period T2, the signal IC falls as the "OII times signal".
Maintain signal status. When the signal IC becomes a "0" signal, the AND gate 25 becomes open, and the residual data D(n)+ in the shift register 24 is passed through the AND gate 25 to the O input terminal of the subtracter 23 and the adder 28. is supplied to the input terminal of As a result, in the second period T2, the subtracter 23
From, E(n)2=D(n)2−D(n)+−(12>
Residual difference data E(n)2 is output, and this data E
(n)z is written to memory M and also from adder 28: E(11)2 +D(n)I=D(n>2 D(
n)+ +[) (n)+ =D (n
)2-(13), that is, the residual data D(
n)z is output, and this residual data D(n>2) is sequentially read into the shift register 24.

Thereafter, the same process is repeated, and as a result, the memory M
Residual difference data E(n)+, E(n)2, . . . are sequentially written within.

Note that the circuit in the lower half of FIG. 3(A) can also be configured as shown in FIG. 6. According to the configuration shown in FIG. 6, the adder 28 in FIG. 3(a) can be omitted.

Next, in FIG. 3(b), the residual difference data E (n) read from the memory M is supplied to one input terminal of the adder 31. Note that reading from the memory M is of course performed at the timing of the clock pulse φ. The adder 31 and the shift register 32 are for returning residual difference data E (n) to residual difference data D (n'). That is, first, each residual difference data E of the first period T1 is stored from the memory M.
At the timing when (n>+(=D(n)1) is read out, the signal IC becomes the ``1'' signal, so the inverter 33 outputs the ``O'' signal, and the AND gate 3
Data "0" is output from 4. This data “0” is then supplied to the other input terminal of the adder 31. As a result, residual data D(II)+ is output from the adder 31 and supplied to the sampling data reproducing circuit 35 and the shift register 32. The shift register 32 has the same configuration as the shift register 24 described above (FIG. 3 (a)), and sequentially reads each supplied residual data D (n) +, shifts it, and outputs it from the output terminal Q after one cycle. do. Next, each residual difference data F(n) of the second period T2 is stored in the memory M.
At the timing when 2 is output, the signal IC becomes “OII
It becomes a double signal. Thereafter, this signal IC continues to be in the II OII signal state. At the above timing, the signal IC is
``When the signal comes, Antogame]・34 becomes open,
The residual data D(n)+ in the shift register 32 is sequentially supplied to the other input terminal of the adder 31 via the AND gate 34.

As a result, from the adder 31, E (n)2 +D (n)I =D
(n)2-D (n+)10D (n
)+ =D (n)z ・=(14), that is, residual data D(n)2 is output, and this residual data D(n>2 is output to the sampling data reproducing circuit 3.
5 and sequentially read into the shift register 32. Thereafter, the same operation is repeated, and as a result, the residual data D(n)+ is sent to the sampling data reproducing circuit 35.
, D(n)2, . . . are sequentially supplied.

The sampling data reproducing circuit 35 generates residual data D (
This circuit reproduces sampling data F (n ) from F (n ). The residual data D (n) is the aforementioned (
11) It is created based on Eq. Transforming this equation (11), we get F (n +2) = -F (n -2) +3F (
n −1)=4F (n) +3F (n +1 >
+4D (n) (15) The following formula is obtained. The sampling data reproducing circuit 35 reproduces the sampling data F (
n).

To explain in detail below, in the sampling data reproducing circuit 35, 36 to 39 are DFFs, 40 to 44 are multipliers, and 45 is an adder. Now, consider the point in time when the adder 31 outputs the residual data D(2). Also, at this point, lean pulling data F (
n) initial values F(0), F(1), F(2)
, F (3) are respectively stored. In this case, each of the above-mentioned initial values F(0) to F(3) is
4 to 41, coefficients r-IJ, r3J, r-41, r
3j is multiplied by the frequency, and the multiplication result is supplied to the adder 45. Further, the residual data D(2) is multiplied by a coefficient “4” in the multiplier 40, and the result of this multiplication is supplied to the adder 45. As a result, the residual data D(2) is transferred to the adder 3.
'1, the output data of the adder 45 is -F(0)+3F(1)-4F(2)+3F(3,)
+4D (2>...(16). As is clear from equation (15), this data is cloud numbering data F(4). That is, the residual data D(2) is 31, sampling data F(4) is output from the adder 45, and the DAC 46 and DFF3
6 input terminal. Next, 1 of the clock pulse φ
When residual data D(3) is output from the adder 31 after the bit time, data F(4) to F(1) are read into 0FFs 36 to 39 at this point, so the adder 4
From 5, -F (1) +3F (2) -4F (3) +3F
(4)+4D (3)...(17) Data, that is, sampling data F(5) is output. Below, the residual data D(4) from the adder 31,
When D(5)... are sequentially output, the adder 45 outputs the sampling data F(6),
F(7)... are sequentially output and supplied to the DAC 46. As a result, a signal identical to the musical tone signal F(t) of a natural musical instrument is obtained as the output of the DAC 46. Note that the above-described sampling data reproducing circuit 35 has the same configuration as an IIR filter, which is a type of digital filter.

The above is the details of the second embodiment. In addition, in the first implementation 1-1 described above, the prediction data FY(n) is transformed into the past data F(n-1)J5 and the future data F (11
-1-1>, and in the second embodiment above -
(The child III redata FYa (n) was obtained from the past data F (n-2), F (n-1>) and the future data F (n-1-1>, F (n +2>), but this For example, the predicted data may be obtained only from past data.

In addition, in the explanation of FIG. 3(b), initial values F(O) to F(3) of sampling data F(n) are recorded in DFFs 39 to 36, respectively, at the start of musical tone reproduction.
However, when playing music, DFF3
9 to 36 may be reset respectively.

In this case, the sampling data F(0) cannot be correctly reproduced for the rising edge data, but the subsequent data can be correctly reproduced.

Furthermore, in the above embodiment, the residual data E(n) is obtained by calculating the difference between the residual data D (n) of each cycle and the residual data D (n) of one cycle before. However, the present invention is not limited to this, and it may be determined from the difference from the residual data D(n) from an arbitrary cycle before (for example, two cycles yA or 1/2 cycle before). For this purpose, the number of stages of the shift registers 24 and 32 in FIGS. 3(a) and 3(b) may be set in accordance with the number of sample points within a predetermined cycle.

In this case, instead of shift register 24.32, RA
The residual data D (n) may be delayed using a memory such as M or the like.

By the way, the above-mentioned 1. In the second embodiment, the amount of data to be stored in the memory M can be further reduced by adding a special circuit.

That is, the residual data D (
n ) or residual difference data E (+1) for another 5 ha.
nnon -F ar+6m1-de or Huffm'
It is sufficient to convert it into an=+- code and store it in the memory M.

The Huffman code will be briefly explained below. For example, in the first embodiment, the probability of occurrence of each value (0, ±1, ±2, . . . ) of the residual data D(n) is different. The toll uffman code is a code that takes into account the probability of occurrence, and is designed to allocate a code with a small number of bits to data with a high probability of occurrence.

Note that the 5hannon-Fano code is based on the same idea. Table 1 is a size table showing an example of the relationship between the residual data D(n)(7) value and Hunman:+-do HC.

Table 1 In Table 1, "probability of occurrence" is a value measured using a musical tone signal of a certain natural musical instrument as a model.

In addition, "other" means the case where the residual data D (n) is +4 or more, or -4 or less; in this case, @
Add the actual residual data D(n) (for example, 8 pits) to the uffman coat HC "○○01".

Therefore, when applying this Huffman code to the first embodiment, an encoder is inserted at the position of the broken line H1 shown in FIG. After converting to code HC, it is written to memory M. In addition, a decoder is inserted at the position of the broken line H2 shown in FIG.
Return to Figure 3 (a).

The same applies to (b). In addition, this HLlffI
By using the Ilan code, memory M1. :fi The amount of data to be loaded can be reduced to about 3/8.

Next, the experimental results of the circuit shown in Fig. 3 (A) will be explained. Figs. 7 (A) to (C) show the musical tone signal F(t)
Pipe organ trumpet sound (8'-G4:
392Hz), the frequency of the clock pulse φ, that is, the sampling frequency, is 35KHz, and the sampling data F(n) (12 pits), residual data D(n), and residual difference data E(n) It is a diagram in which changes in values are sequentially displayed in response to clock pulses φ. As is clear from this figure, the residual data D (n
) is much smaller than the value of the sampling data F (n), and the value of the residual difference data E (11>) after the second cycle day is even smaller than the value of the residual data D (n). FIG. 8 is a diagram showing the generation state of each of the residual error data E(+1) shown in FIG. It shows the number of occurrences of each of the residual data E (n) that occurred between 512 sample points. For example, E (n) = O is 33 times,
E(n)-1 is 40 times, E(n)-2 is 34 times,
E(n)=-1 is 58 times, E(n)-1 is 28 times
It has occurred twice. Also, in this figure, fields of +10 or more or -10 or less are values that occur on the first cycle day of the musical tone signal F ([), and such large value data E (+1) occurs on and after the second cycle day. It rarely occurs. Note that the reason why the residual difference data E(0) takes a relatively large value of 1hi1 on the first cycle day is because, as mentioned above, there is no previous cycle on the first cycle day.
This is because the residual data D(n) is directly used as the residual data E(n).

Note that the DFF1s 2 to 16 in FIG. 3(a) are reset to the initial state. In addition, the reason why the trumpet sound of a pipe organ was used as the subject of the experiment is that it contains many harmonic components and has many changes in waveform.

[Application example]

Next, an application example of the musical tone signal generating device according to the first embodiment described above will be explained. FIG. 7 is a block diagram showing an example of the configuration of an electronic musical instrument to which the musical tone signal generating device is applied. In this figure, the residual memory M stores, for example, each tone (piano tone,
The musical tone signal F(t
) residual data D(n) for all waveforms from the rise to the end are stored. When one of the timbres is selected by the timbre selection section 50, the output data TC of the timbre selection section 50 causes the memory of the memory M in which the residual data D(n) corresponding to that timbre is stored. Area is specified. Next, when any key on the keyboard 51 is pressed, the key press detection section 52 detects this and outputs the key "-do KC" of the pressed key and also outputs the key-on signal KON. Ru. This key-on signal KON continues to be a "1" signal while the key is pressed. The address generator 53 converts the key code KC output from the key press detection unit 52 into address data AD1 corresponding to λ·j and outputs it to the residual memory M.
``After one revolution, the address data ADD that changes sequentially as 0, 1, 2, etc. is output to the residual memory M. When the address data AD1 is supplied to the residual memory M/\, the above-mentioned The area corresponding to the address data ADI in the storage area specified by the data TO is designated. This is the area in which the residual data D (n) of the musical tone signal F ([) with the key code KC outputted is stored.Then, the address data ADD is transferred to the residual memory M. When supplied, the residual data D (
n), and are sequentially supplied to the sampling data reproducing circuit 5. As a result, the sampling data F (n) is sequentially output from the sampling data reproducing circuit 5, and the output data "(n) is converted into a musical tone signal (analog signal) by the DAC 6 and supplied to the sound system 54.Sound The system 54 amplifies the supplied musical tone signal and produces a musical tone from a speaker.

In addition, when adding a pitch change such as vibrato to the generated musical tone, the output timing of the address data ADD may be changed. In this case, the sampling data reproducing circuit 5
The data processing within is also synchronized with the output timing of address data ADD. Also, instead of storing residual data D(n) for each pitch, one set of residual data D(n) is stored for all pitches, or one set for each pitch is stored. When storing the residual data D (n), the output timing of the address data ADD is set using the key code K.
You can use ``quick melon'', which corresponds to ``C'' and ``J''.

〔Effect of the invention〕

According to the present invention, the residual data or the data corresponding to the residual data are recorded in advance in the memory as described above.
03U, the data in this memory is read out and a musical tone signal is generated (formed), so the memory capacity can be significantly reduced compared to the conventional method, and the original waveform can be faithfully reproduced. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, and FIG. 2 is a block diagram showing predicted data FY in the same embodiment.
(n) and residual data D(0), FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. 4 is a diagram for explaining the residual data D(0). FIG. 5 is a diagram for explaining the difference data E (n), FIG. 5 is a diagram for explaining the predicted data FYa (n >) in the same example, and FIG. 6 is a diagram for explaining the other circuit shown in FIG. 3 (A). A block diagram showing a configuration example, FIGS. 7 and 8 are diagrams showing an example of experimental results of the circuit shown in FIG. 3 (A), and FIG. 9 is a block diagram showing an example of the circuit shown in FIG. 1. It is a block diagram without showing the configuration of the electronic musical instrument. 5.35... Sampling data playback circuit, M
······memory. Figure 1 Figure 3 C) Figure 3 C111J Figure 4 Figure 5 11-+ + c e -5c Figure 8 Figure 9 Pull 5 M

Claims (2)

[Claims] (1) (a) A memory in which residual data, which is the difference between sampling data obtained by sampling a musical sound waveform and predicted data calculated from a plurality of said sampling data, or data corresponding to this residual data, is stored. and (b) reproducing means for reading data in the memory and reproducing the sampling data based on the read data, and generating a musical tone signal based on the sampling data reproduced by the reproducing means. A musical tone signal generating device constructed as follows. (2) The musical tone signal generating device according to claim 1, wherein the data corresponding to the residual data is the difference between the residual data at the sampling point and the residual data at the sampling point a predetermined period before. .