JPS6190523A - Waveform processor - Google Patents

Abstract

PURPOSE:To output sampling data while being compressed into a very less bit number by converting the sampling data into residual data and converting it into residual difference data for output. CONSTITUTION:A waveform shown in figure A is taken as a music signal F(t) of a natural musical instrument and a time (00) is taken as a music generating start time. In this case, a difference between the residual data D(K)1 at a sample point time t(K)1 of the 1st period T1 and a residual data D(K)2 at a sample point time t(K)2 corresponding to the time t(K)1 of the 2nd period T2 is very slight. Then a residual data D(n) at a sample point before one period is subtracted from the calculated residual data D(n), the result of subtraction, that is, a residual difference data E(n) is written in a memory M. The residual difference data E(n) is far smaller than the residual data D(n), and then the data amount to be stored in the memory M is decreased far less than that of a conventional circuit.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention converts digital 1 numbering data representing a waveform that determines periodicity, such as a musical sound waveform, into digital data with fewer pitches than the sampling data. The present invention relates to a waveform processing device used for processing.

[Prior Art] Techniques for sampling waveforms such as voice waveforms and musical sound waveforms, converting them into digital sampling data, and processing the data are widely used in fields such as voice synthesis, electronic musical instruments, and data communications.

[Problems to be solved by the invention] The biggest problem with all processing technologies is that the amount of data required is enormous.For example, natural musical instruments (BI) ) When converting the raku high waveform into gage digital sampling data and storing it in a memory, the capacity of this memory becomes extremely large. Therefore, various /j methods for compressing the number of hits of sampling data have been considered in the past, such as the DM (delta modulation) method, the ADM (adaptive delta modulation) method, and the DPCM (differential pulse code modulation) method. It is being

It is an object of the present invention to provide a waveform processing device that can further compress data than the above-mentioned conventional methods, especially when processing waveforms having periodicity such as musical tone waveforms.

[Means to solve the problem]

The first invention obtains residual data as the difference between sampling data obtained by sampling a waveform and predicted data extracted from a plurality of sampling data, and further calculates residual data from a sample point before a predetermined period of the waveform. By calculating the difference between the residual data and the residual data indicated by -F, compressed digital data of the sampled data indicated by -F is obtained.

The second invention is constituted by a converting means corresponding to the first invention, and an inverse converting means for converting the compressed digital data back to the original sampling data. In this case, the inverse conversion means adds the digital data that has been subjected to 1if and the old residual data of a predetermined period ago, and includes an arithmetic means that outputs the addition result as current residual data; The apparatus includes a delay means for outputting the old residual data to the performance means after a time delay corresponding to a predetermined period, and a sampling data reproducing means for reproducing the sampling data from the current residual data.

[Effect]

The predicted data has a value close to the sampling data, and therefore the residual data, which is the difference between the sampling data and the predicted data, has a small value compared to the sampling data. In addition, for a periodic waveform, residual data at a certain sampling point and a predetermined period (
For example, the residual data at the previous sampling time point (for example, one cycle) is data for one night that is very close to each other. As a result,
The difference between these residual data is a much smaller value than the sampling data, and therefore, the number of bits can be extremely small.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A and 1B are block diagrams showing the configuration of an embodiment of the present invention.

2(a) and (b) are diagrams showing the circuits that are the basis of the same embodiment, and the embodiment shown in FIG. 1(a) and (b) is as shown in FIG. 2(a), This is an improved version of the circuit shown in (2).

Below, the circuit of FIG. 2 will be explained first. Figure 2 (a) shows the configuration of a data embedding circuit that samples the musical tone signal (analog signal) F(1) of a natural musical instrument, compresses the data, and stores it in the memory M. The configuration of a musical tone signal generating circuit that reads data in memory M and generates a musical tone signal "(shi)" is shown.

In Figure 2 (a), No. 11 1 is At) C (analog/digital converter), which converts the musical sound signal F of a natural musical instrument.
([) is sequentially sampled at the timing of the clock pulse φ, and this sampled data (analog data) is converted to f digital sampling data F (n) and is sequentially used as main data. The predicted data generation circuit 2 generates predicted data FY(n) based on the sampling data F(n).
is generated and output to the subtraction circuit 3. Here, the predicted data FY(n) is -For example, FY(n)=(F(n-1)+F(n+1))/2...
・(1) Created based on the formula: That is, if we take the musical tone signal F(t) from the curve shown in FIG. 3, the times t (n-1), t (n), t (n+
1>, j (n+2), sampling data F (n-1), F (n), from A, D C1, respectively.
F (n-1-1>, F (n +2) are output respectively. At time t(n+i), the predicted data generation circuit 2 generates the sampling data F(11-1) and the sampling supplied at that time. Data F(n+1) and IIO
The prediction data FY(n) is created and output by dividing this addition result by 12''. Similarly, time t
(n +2), the sampling data F (
n) and predicted data FY(n+1) from F(n+2)
Create and output. The subtraction circuit 3 delays the sampling data F (n '') by one bit time of the clock pulse φ, and extracts the predicted data FY from this delayed data.
(n) is subtracted to create residual data D (n). That is, at time t(n+1), this subtraction circuit 3 creates residual data D (n) by the calculation D(n) = F(n) - FY(n) (2) and outputs it. Here, the residual data D (n) is a much smaller value than the sampling data F (n), as is clear from FIG. Perform with fewer hits than the number of hits.

Therefore, the residual data D (n) described above is stored in the memory M
are sequentially written within.

Next, in FIG. 2 ([1), the code 5 retrieves the residual data D(n) from the memory M and reads out the read data D.
This is a sampling data reproducing circuit that reproduces sampling data F (n) based on (n). This circuit 5 will be explained below. The above-mentioned equation (1) is transformed into the equation (
2) Substituting into the equation, D (n) = F (n) - (
F(n-1)+F(n+1))/2...(
3) The following formula is obtained. If we transform this equation (3), we get
F(n+1)=2(F(n)-D(n))-F(n-1
>...(4) The following formula is obtained. The sampling data reproducing circuit 5 is
Based on this equation (4), sampling data F (n
) is played. Assume that the initial first round F(0) and F(1) of the sampling data F(n) are stored in advance in the sampling data reproducing circuit 5. First, the reproducing circuit 5 starts with the first 111J l+ηF
(0) J> and F(1) are sequentially output according to the clock pulse φ, and the residual data D read from the memory M.
The calculation of equation (4) is performed based on (1). That is, data D(1) is subtracted n from data F(1), the result of this subtraction n is multiplied by 2, and data F(0) is subtracted from this multiplication result.

By the above operation n, the sampling data F(2) is 1q
It will be done. The reproduction circuit j] sets the sampling data F(2) obtained in this way to initial values F(0) and F(1
) followed by DAC (digital/analog converter) 6
Output to. Next, the reproducing circuit 5 receives the output pulse φ
When 1-pil-time has elapsed, the calculation of equation (4) is performed based on the residual data D(2>) read from the memo υM, and the sampling data F(3) obtained thereby is calculated.
) is output to DAC6. Thereafter, the same process is repeated, whereby one non-pulling data F (n) is sequentially supplied to the DAC 6. The DAC 6 converts the sequentially supplied sampling data [(n) into an analog signal and outputs it. In this way, the same signal as the musical tone signal F([) ((11L, hanging error exists) is output from the DAC 6.

The above are the details of the circuit shown in FIGS. 2(A) and 2(1). Next, an embodiment of the present invention shown in FIGS. 1(a) and 1(b) will be described. This embodiment is an improvement of the circuit shown in FIGS. 2(a) and 2(b) as described above, and the improvements include the following two points.

First point: Nature! The musical sound waveform of the instrument has periodicity. The first improvement was made by focusing on this periodicity. In the circuit of FIG. 2, the residual f-ta D (n) was stored as is in the memory M, but in this embodiment, , the difference between the residual data D(0) and the residual data D(n) one cycle before (hereinafter, residual data E(n)) is stored in the memory M.
) is memorized. This will be explained in detail below. Now, let the waveform shown in FIG. 4 be the waveform of the musical tone signal F(t) of a natural musical instrument, and time t (OO) be taken as the musical tone generation start time. In this case, residual data D(K)+ at a sample point time t (K)+ in the first period T1 and a sample point (with the same phase) corresponding to time j(K)+ in the second period T2 Residual data D at time t (K)2
(K) The difference from 2 is extremely small 1, similarly at time t
(K)2 residual data D(K)2 and time t
(Residual data D<K when K>3) The difference from 3 is also extremely small. θNow, in the embodiment (not shown in FIG. 1), the residual data/1.0 (n) at the corresponding one point of one cycle before is subtracted from the calculated residual data D(n). , this decrease.

In other words, the residual data E (n) is stored in the memory M.
(See Figure 4). In addition, the first
In period T1, residual data D (n
) does not exist, the residual data E(n)+ is the same data as the residual data D ('n) I .

Therefore, the value of the residual difference data E (n) is the residual data D
(n) is much smaller than the value of the data stored in the memory M. It can be made more coarse. Note that reproducing the sampling data F (n) from the residual difference data E (n >) can be realized by a simple circuit as described later.

Second point: The second improvement is the method of not outputting the prediction data FY(n). That is, in the circuit of FIG. 2, the predicted data F
Although Y(n) was calculated from the two sampling data F(n-1) and F(n+1) (see equation (1)), in this example, the predicted data FYa (0) was calculated from the four sampling data F(n-1) and F(n+1). Sampling data F (n-2), F (n-1
), F (n + 1).

It is calculated from (n+2). The method for outputting 0 will be explained below using FIG.

First, limp ring data F(n-2), F(n-1)
, the prediction data P(n-1) from sampling day F
(n-1), predicted data P from F (n +1)
(n), and the sampling data F (n +1
), F (ri +2) to predicted data P(n+1)
Calculate each. This Ω output is determined by the following formula.

P (n -1) = 'F' (n -1 -) - (
F(n-1>-F(n-2>)・(5)P(n)=[
F(n-1) +F(n-to 1))/2... (6)
P (n + 1) = F (n 4-1) - (F
(n + 2) -1 (n + 1)
) ... (7) Next, these predicted data P(n
−1), P(n), and P(n+1), rlJ and r2J, respectively.
, Ml are multiplied by coefficients and then added, and this weighting result is divided by "4" to obtain predicted data FYa(n).

FYa (n) = (P (n-1>+2P (n
)+P (n+1>)/4...(8) The above is the basic idea of the method of not outputting the prediction data FYa(n). Substituting the above equations (5) to (7) into the above equation (8) and rearranging, FYa (n) = (-F (n-2) +3F
(n −1) t3F(n+1)−F(n+2))/4
...(9) The formula is 1q. That is, in this example,
Based on this equation (9), J and 4, the predicted data I”Ya(n
) is calculated.

According to the above calculation method, compared to the calculation method of the predicted data FY(n) in the circuit shown in FIG.
It is possible to exclude the predicted data FYa (n>) that is closer to the actual sampling data [(n), so that the value of the residual f-ta D (n) becomes smaller and the number of bits can be reduced. In addition, the weight I mentioned above
The coefficient may be determined using, for example, least squares prediction so that the difference between the sampling data F (n) and the predicted data FY (n) is minimized.

The above are the improvements in this embodiment. Next, a specific combination of this embodiment will be explained with reference to FIGS. 1(a) and 1(b). First, in FIG. 1(a), the musical tone signal F([) of a natural instrument is converted to sampling data F([) by ADCl.
(n) and is supplied to the residual data optical 1 unit circuit 11. The residual data generation circuit 11 corresponds to the prediction data generation circuit 2 and circuit 3 in FIG. Residual data D after reducing
〈n, buzzing, D(n) = F(n) - FYa (n) The river (10) is brought out and output. Substituting the above equation (9) into this equation (10) and rearranging, D (n) = (F (++ -2>
-3F (n -1)+4F (n) -3F
(n −)1 ) +F (n +2) )/4...
(11) The following formula is obtained. The residual data generation circuit 11 calculates the residual data D(n) by calculating the equation (11),
Output.

That is, in the residual data generation circuit 11, the code 12
~16 are each D triggered by a clock pulse φ
FF (70 delay flips), and sampling data F (n>) is sequentially read into these 0FF12 to 16 according to the clock pulse φ.
~16 outputs are supplied to multipliers 17-21, respectively, to r
1/4J.

r-3/4J, rlJ, r-3/4J, [1/4J
' is multiplied, each multiplication result is added in an adder 22, and output as residual data D (n).

Incidentally, the multipliers 17 to 21 can be easily constructed using data shift circuits, adders, etc. Therefore, at sampling time t(n+2), J3 is present, and DFFs 12 to 16
respectively have sampling data F(n +2) and F(
n-+-1), F (n), F (n-1>,
F(n-2) is read, and therefore, the residual data D(n) of equation (11) is output from the adder 1a22. The configuration of this residual data generation circuit 11 is the same as that of a linear phase IR filter, which is a type of digital filter.

Next, the residual rata 1](
11) is supplied to the Φλ input end of the mouth reducer 23. mouth reducer 2
3 reduces the data supplied to the O input terminal from the data supplied to the ■ input terminal, leaving this reduction and stop result; (-
difference data] (11).

In other words, this mouth reducer 23 calculates one cycle (Raku14 signal F(t
) is a circuit that reduces the previous residual γ-ta D(n), and the output data of the shift register 24 is input to its 0 input terminal via )'n1-g1-25. Supplied. The shift me register 24 is a register for holding the residual data D (n) for one cycle, and has a sdage equal to the number of sample points within one cycle, and has the residual data D (n) supplied to the input terminal IN. are sequentially read based on the clock pulse φ. The read data D(n) is transferred to the shift register 24
The signals are sequentially shifted within the range, and are outputted from the output GQ after one cycle has elapsed.

Therefore, in the first period T1 (see FIG. 4) of the musical tone signal F([), the signal IC becomes a "1" signal. As a result, the inverter 27 outputs a "0°" signal. Data [0] is output from the AND gate 25.

As a result, the residual data D(n
)+ is the residual difference data E(n)+ directly sent from the subtractor 23.
is output as Then, this residual difference data E(n
)+ are sequentially written into the memory M and supplied to the adder 28. The obstacle device 28 uses residual adhesion difference data E (n)
+ (=D (II)+) and the output data "0" of the AND gate 25, and the result of this addition, that is, the residual data D (n>+) is sequentially transferred to the input terminal IN of the shift register 24. To U (give. This money; (j' - 0 (n) 1
are sequentially read into the jit register 24.

Next, at 13 on the second round +111 T 2, the signal IC
falls to the ``O'' signal. Note that the 81c continuously maintains the "O" signal state from then on. (When the IC becomes the "O" signal, the controller h 25 becomes open, and the residual j-f in the shift register 24 )(n), is the 0 input terminal Jj J of the Q subtractor 23 via the same 7nd gate 25, and the addition G
−5 input terminal l of the device 28 (supplied. As a result, in the second cycle T2, E (n ), ,
=D (11),! -D (n l+...(12
＞ is output, and this data IT:(11>2 is passed to the input circuit M, and from the adder 28, F(I+-), 7 1 −1) (n >+ =D (n
), ) −D (11)+−1−D(n)+ =
D(n)2-(13) data, Suku [straw residual f-
This residual data D(11
)2 are read into shift 1-register 24 sequentially.

From now on, the same overcoat is repeated, and as a result,
Residual difference data I-: (n)+, F,,'
(n)2, . . . are answered in sequence.

Note that the circuit in the lower half of FIG. 1(A) can also be configured as shown in FIG. 6. According to the configuration of FIG. 6, the adder 28 in FIG. 1(a) can be omitted.

Next, at the first end d5, the residual difference data LE (n) read from the memory M is supplied to the ~ input terminal of the adder 31. Note that reading from the memory M is of course performed at the timing of the clock pulse φ. The adder 31 and shift 1 to register 32 store the residual difference data E (, n
) to return the residual data 9 (n).

That is, first, at the timing when each residual difference data E(n)+(=D(n)+) of the first period king 1 is read from the memory N4, the signal IC becomes a "1" signal, and therefore the inverter 33 The "°0°" signal is outputted from the AND GOUT 1 34, and the f-TU "0" is outputted. This data “0” is then supplied to the other input terminal of the adder 31. As a result, the adder 31 outputs the residual data D(n)1, and the ring 1 ring γ-wave regeneration circuit 3
5 and the shift register 32. The shift register 32 has the same configuration as the above-mentioned Iζ shift register 24 (FIG. 1(a)), and is supplied with each residual data D(
n) + sequentially, shift, and output D after 1 cycle.
Output from AQ. Next, the second period from Meshiri M - [
At the timing when the residual cold data E(n) and + of 2 are output, the signal IC becomes the ``0'' signal.Thereafter, the 1 old IC continues to be in the ``OII signal'' state. When the signal IC becomes a '0' signal at the above timing, the AND gate 34 becomes open, and the residual f-D(n)+ in the shift register 32 is transferred to the other side of the adder 31 via the AND gate 34. 1 (sequentially) 1 (supplied to the input terminal).

As a result, from the adder 31, E (n),! +D (n L+ =D (n >
2-D (n+)+D (n)+ =D (+1>
2-414), that is, the residual data D(n
), is output, and this residual data 1. ) Cn ) 2
The data are supplied to the sampling data reproducing circuit 35 and sequentially read into the shift register 32. Thereafter, similar operations are repeated, and the residual data D(n>+, D(n)2, . . .
... are supplied sequentially.

The sampling data reproducing circuit 35 outputs the residual data D.
This is a circuit that reproduces sampling data F (n) from (n). The residual data D (n) is calculated by adding 1 to the above-mentioned equation (11). ! It was created based on This (1st
1) Transforming the formula, F (n +2), = -F (+1-2) +3F (
n-1)-4F (n) +3F (n +1)
+4D (n) (15) The following formula is obtained. Based on this equation (15), the sampling data reproducing circuit 35 reproduces the sampling data F (
n).

To explain in detail below, in the sampling data reproducing circuit 35, 36 to 3 are DFFs, 40 to 44 are q multipliers,
45 is an adder. Now, take the point in time when the residual data +1 (2>) is output from the adder 31. Also, this 11
．． 4 jj, i to Dll''30-36 respectively It combining 7゛-E1 (n) (7) First 1! II l direct F (0), I = (1), F (2), l (
, '3) are memorized in each case. in this case,
Above) The early ships (0) to F(3) each have Tomeki 4.
7'1 to 41 have 43 coefficients r-IJ, r3J, r-4
J, r3J are multiplied by 0, and this heavy result is supplied to the adder 15. , and the residual -j-ta D(2) is multiplied by the C coefficient r4J in the claw bullet device 40, and this multiplication result is supplied to the adder 45. As a result, residual data D(2)
At the time when the output from the adder 45 is output from the sigma generator 31, the output of the adder 45 is -F (0) +3F (1) -4F <2) +3
F(3)+4D (2>...(16) This data is the sampling data F(4) as is clear from the formula ('+5>).In other words, the residual data D (2) is output from the adder Ej7j131, the sampling data F(4) is output from the adder 45 and supplied to the input terminals of the DAC 46 and the DFF 36.Next, 1 hit 1-time of the clock pulse φ Later, when the residual data 0 (3) is output from the addition (1 unit 31),
At this point, DFFs 36 to 39 each have data “(4) to F.
Since (1) is read, -F(1)+3l-(2)-4F(3)+3F(4)+
4D (3>...(17)), Zunawara limp ring j'-data (5) is output.Hereafter, residual data D(4) from the adder 31 is output.
, D(5)... are sequentially output, the sampled data F(6)
, F(7)... are sequentially output and supplied to the DAC 46. As a result, a signal identical to the musical tone signal F(t) of a natural musical instrument is obtained as the output of the DAC 46. Note that the above-described sampling data reproducing circuit 35 has the same configuration as an IIR filter, which is a type of digital filter.

The details of the embodiment shown in FIG. 1 have been described above. Note that in the above embodiment, the prediction data FYa(n)
' as past data F (n-2), F (n-1> and future data F (n +1), F (n +2)
), or this predicted data may be obtained, for example, only from past data, or, as in the circuit of Fig. 2, past data F(n-1) and future data F (
+1-) 1). : L. In the above embodiment, the residual difference data [(n) is obtained by calculating the difference between the residual data D(n) of each period and the residual data D(0) of one period before. However, the present invention is not limited to this, and it may be determined from the difference from the zero child f-ta D(11) of the cycle of Ninhiro (for example, two cycles before or 1/2 cycle before IJ).

For this purpose, the number of stages of the shift registers 24 and 32 in FIGS. 1(a) and 1(b) may be set in accordance with the number of number points within a predetermined period. In this case, a memory such as a RAM may be used instead of the shift registers 24 and 24 to store the residual data D (n).

Furthermore, in the above embodiment, the compressed pig E (n
) is stored in memory M, but this data [(n)
Of course, the present invention can also be applied to the case where the data is transmitted to a device via a transmission line and reproduced as sampling data F(n) in the device.

By the way, by adding a special circuit to the circuit shown in FIG. 2 or the above embodiment, it is possible to further reduce the amount of data to be stored in the computer. That is, the residual difference data D(n) or the residual difference data E(n) to be stored in memory ~1 is further stored in Shannon-
Fano] -+1 or )-1 uffman code and stored in the memory M.

The )luHman code will be briefly explained below. For example, in the circuit shown in FIG. 2, the probability of occurrence of the eight values (0, ±1, ±2, . . . ) of the residual data DCn is different. The l-ll-1urf code is a code that focuses on the probability of occurrence, and a code with a small number of bits is assigned to data with a high probability of occurrence. Note that the 3 hannon-Fano code is based on the same idea. Table 1 is a table showing an example of the relationship between the value of the residual data D(0) and the H, urrman code HC.

Table 1 In Table 1, "probability of occurrence" is a value measured using a musical tone signal of a certain natural musical instrument as a model.

In addition, “other” refers to the case where the residual data D (n) is greater than or equal to +4 or less than or equal to −4; in this case, 1-I
Add actual residual data D(n) (e.g., 8 bits) to Llffmarll-dot1-IC''OOO1°''.

Therefore, when applying this @uffman code to the circuit shown in Figure 2, an encoder is inserted at the position of the broken line H1 shown in Figure 2 (A), and the residual data D (n') is The code shown in Table 1 is converted into the 1uffman code HC and then written into the memory M. In addition, the broken line 12 shown in FIG. 2 (b)
A decoder is inserted at the position of H read from memory M.
The data based on the uffman code HC is returned to the original residual data D (n). Figure 1 (a).

The same applies to (b). In addition, this Huffma
By using the n code, the amount of data to be written into the memory M can be reduced to about 3/8.

Next, the experimental results of the circuit will be explained with reference to FIG. 1(a). Fig. 7 (A) to (C) are each a musical tone signal F ([)
Vibe A° Lugan's trumpet sound (8'-G4
; 3921-17), and the clock pulse φ
The frequency, that is, the sampling frequency, is 35 KHz, and the sampling data F(n) (12 bits), the residual data D (n), and the residual data E(n'
) is a diagram sequentially displaying changes in multi-values in response to clock pulses φ. As is clear from this figure, one shift of the residual data D (n) is the sampling data F (n)
In addition, the value of the residual difference data after the 1st to 11th shifts of the second round; E (n) is even smaller than the value of the residual data [) (n). FIG. 8 is a diagram showing the generation state of the residual error data E (n>) shown in FIG. The multi-value 5 of the generated residual difference data E (n) indicates the raw number of times. For example, E (n) = 0 is 33 times, E (n>-1 is 40 times,
E(n)=2 occurs 34 times, E(n)=-1 58 times, and E(+1)=-2 28 times. Also, in this figure, values of +10 or more or -10 or less are fields that occur on the first cycle day of the musical tone signal F ([), and values that occur on the second
If f-ta E (
n) rarely occurs. In addition, the residual difference 1
-Ta E (n) takes a relatively large value on the first cycle day because, as mentioned above, there is no previous cycle on the first cycle day, so the residual data D (n)
This is because the residual difference data E(11) is used as it is.

In addition, in Fig. 1 (A), DFF1 2 to 16 in "I have been reset to the initial state. Also, Umeyama, who used the pipe organ's 1 to Ranpetsu [~ sound as the subject of the experiment,
This is because there are many harmonic components and the waveform changes frequently.

[Application example]

Next, an application example of the above-described embodiment will be explained. FIG. 9 is a block diagram showing an example of the configuration of an electronic musical instrument to which the circuit shown in FIG. 1(b) is applied. In this figure, the memory M stores, for example, each tone (pinotsuno tone).

flute sound, etc.) and each sound? :For each S, musical tone signal F
Residual data (n) for all waveforms from the rise of (t) to the end are stored.

Then, when any tone is selected by the tone color selection section 50, the output data TO of the tone color selection section 50 allows
A storage area of the memory M in which residual data E(11) corresponding to the timbre is stored is designated. next,
When any key on the keyboard 51 is pressed, the key press detection unit 5
2 detects this and outputs the key code KC of the pressed key, as well as a key-on signal KON. This key-on signal KON is "1'' while the key is pressed.
(Continue with No. 3. The address generator 53
The key code KC outputted from 2 is converted into the corresponding address data AD1 and outputted to the address data AD1, and after the key-on signal KON rises to the II 1 +1 signal, 0, 1.2, Address data AD that changes sequentially as...
Export D to memory M. When the address data AD1 is supplied to the memory M, 'A Vi corresponding to D1 is specified to the address data in the storage area specified by the data TC mentioned above. This area has the tone selected by the tone selection section 50, and has the tone selected by the key press detection section 52.
This is the area where residual difference data E (n) of the musical tone signal F([) having the pitch of the key code KC outputted from the key code KC is stored. Then, when the address data A[)D is supplied to the memory M, the residual difference data E(+1) in the relative address 0 of the area is sequentially read out, and the musical tone reproduction section 5
4 is sequentially supplied. The musical sound reproduction section 54 is shown in FIG.
is the same circuit (except for memory M), and when the residual data E(n) is sequentially supplied, it outputs a musical tone signal F(t) (analog signal) from its output terminal, and the sound system 55. The sound system 55 amplifies the supplied musical tone signal F(t) and produces a musical tone from a speaker.

Incidentally, if a pitch change such as vibrato is to be added to the generated music t'f, the output timing of the address data ADD may be changed. In this case, the data processing within the musical tone reproduction section 54 also follows the output timing of the address data ADD. Also, instead of storing nine residual data E (n) in each pitch turtle, one set of residual difference data E (+1) can be stored in common for all pitches, or each pitch turtle can store a set of residual difference data E (+1). When storing one set of residual difference data E (n), the output timing of the address data A D +) may be set to a speed corresponding to the key code KC.

〔Effect of the invention〕

As explained above, according to the present invention, sampling data is converted to residual data, and then roughly converted to residual difference data and output, so that the sampling data is compressed to an extremely small number of bits. There is an effect that can be output.

[Brief explanation of drawings]

Figures 1(a) and 1(b) show a combination of an embodiment of the present invention. 2(A) and 2(B) are block diagrams showing the configuration of the circuit that is the basis of the same embodiment, and FIG.
A diagram for explaining the predicted data FY (n') and the residual data D (n) in the circuit shown in the figure, FIG. 4 is not shown in FIG. 1 and explains the residual data F(0) in the example. Figure 5 shows the predicted data F in the same example.
A diagram for explaining Ya(n), Figure 6 is the same as Figure 1 (A)
FIGS. 7 and 8 are block diagrams showing other configuration examples of the circuit shown in FIG. FIG. 2 is a block diagram showing an example of the configuration of an electronic musical instrument. 11... Residual data generation circuit, 23...
・Subtractor, 24...Shift register, 31...
...Kashoki, 32...Sif 1 register,
355...17 sampling data reproducing means. Figure 1 C) Figure 4 Figure 5'ν 〒 Do T Tsuni ζ
-5c m4+4+5

Claims (2)

[Claims] (1) In a waveform processing device that inputs digital sampling data consisting of a plurality of bits obtained by sampling a waveform having periodicity and converts the sampling data into digital data having fewer bits than the sampling data, the input sampling data and the plurality of the a residual data forming means for forming residual data that is a difference from predicted data calculated based on the sampling data; a delay means for outputting the residual data with a time delay corresponding to a predetermined period of the waveform; Calculating the difference between the residual data output from the residual data forming means and the residual data output from the delay means,
A waveform processing device comprising: arithmetic means for outputting the calculation result as the converted digital data. (2) A waveform that inputs digital sampling data consisting of multiple bits obtained by sampling a periodic waveform, converts it into digital data with fewer bits than the sampling data, and converts this converted digital data back into the sampling data. In the processing device, (a) residual data forming means for forming residual data that is a difference between the input sampling data and predicted data calculated based on a plurality of the sampling data; a delay means for outputting the data with a time delay corresponding to a predetermined cycle of the residual data, and calculating a difference between the residual data output from the residual data forming means and the residual data output from the delay means;
(b) adding the current data of the digital data and old residual data from a predetermined period before, and calculating the result of the addition; a calculation means for outputting the current residual data as the current residual data; a delay means for delaying the current residual data by a time corresponding to the predetermined period and outputting the current residual data as the old residual data to the calculation means; a waveform processing device comprising: a sampling data reproducing means for reproducing the sampling data from the inverse transform means;