JP3223560B2 - Waveform data reading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform data reading apparatus for an electronic musical instrument for generating a musical tone by reading waveform data stored in a differential PCM system.

[0002]

2. Description of the Related Art In recent years, as a method of storing waveform data in a sound source of an electronic musical instrument, a differential PCM (Differential Pulse CM) which stores a difference value between sample values of waveform data in a memory such as a ROM (Read Only Memory). Code
Modulation) method (hereinafter, a ROM in which waveform data is stored by the DPCM method is called a DPCM-ROM). At the stage of demodulation of the DPCM, that is, during the performance of the electronic musical instrument, the difference values read from the DPCM-ROM are accumulated (integrated) to obtain the original waveform data.

FIG. 11 is an overall configuration diagram of a general waveform data reading device used for such a purpose. In FIG. 11, an address generator 1101 sends an integer address of a current value address (hereinafter, referred to as a current integer address) to an address controller 1102, a carry to an integrator 1103, a decimal address of a current value address (hereinafter, a current decimal address). Interpolator 1104)
To each of them.

As described below, a difference value corresponding to an integer address of a DPCM-ROM (not shown) is read out from these data, and an integrator 1103 is read out.
And the interpolator 1104 generates waveform data.

Hereinafter, an address generator 1101, an address controller 1102, an integrator 1103, and an interpolator 1 constituting the waveform data reading device of FIG.
FIG.
And a specific example shown in FIG.

FIG. 17 shows amplitude values which are accumulated values (integral values) of waveform data stored at integer addresses (3, 4, 5,...) Of the DPCM-ROM, and amplitude values. FIG. 7 is a diagram illustrating an example of a difference value between the two and an address step amount proportional to a pitch.

In FIG. 17, the original pitch of the difference value data stored in the DPCM-ROM is C4, and the integer address of the DPCM-ROM corresponding to the original pitch is (3)
(4), (5), (6), ... The address increment
(1) corresponds to the original pitch.

In this case, the amplitude value at the address (3) is an integral value S, which is an accumulation of the respective difference values up to the address (3).
Is _1, the amplitude value at address (4), by adding the difference value D ₁ of the between addresses (3) ~ (4) of the said integrated values S ₁ stored in the address (3) of the DPCM-ROM integration is the value S _2. The address (5) the amplitude value at the address stored in the integral value S ₂ in the address (4) (4)
Is a value obtained by adding the difference value D ₂ to (5). Similarly, the amplitude value at address (6), the integral value S ₃ address (5)
Is a value obtained by adding the difference value D ₃ between stored and are addresses (5) to (6).

FIG. 17 shows an example in which waveform data corresponding to the pitch name A3 is obtained. Where A3 sound and C
The pitch ratio of the four sounds is 0.794. That is, the address increment is 0.794 ≦ 1. And the current value address is
3.75, i.e., integer address (3), decimal address
It is assumed that the amplitude value A ₁ of the waveform data at the current value address has been obtained as (0.75).

FIG. 12 is a block diagram of a conventional example of the address generator 1101 of FIG. In FIG. 12, the current value address (3.75) read from the current value address storage memory 1201 is, as shown in FIG. 13, a ROM addressing integer part (3), which is an upper part of the address data, and an address data. It is separated into a decimal part (0.75) for interpolation, which is a lower part, and is set in an address integer part register 1202 and an address decimal part register 1203, respectively.

An address increment storage memory 1204
, The address increment (0.794) proportional to the pitch (pitch) of the musical tone to be played is read out and set in the address increment register 1205.

The address increment and the current value address have a relationship as shown in FIG. 13, and the address increment consists of only a decimal part. Next, the decimal address (0.7
5) and the address increment (0.794) read from the address increment register 1205 are added by the binary adder 1206, and the decimal part of the current decimal address (0.75 + 0.794 = 1.544) is added.
(0.544) and carry are output.

On the other hand, if there is no carry output from the binary adder 1206 for the input integer address, the incrementer 1207 outputs the carry address as it is as the current integer address, but as shown in FIG. If there is an output, it is incremented and output as the current integer address (4).

Next, the current integer address (4) and the current decimal address (0.544) are set in the current value address storage memory 1201 as the updated current value address (4.544), and the current integer address (4) is set. Is sent to the address controller 1102 in FIG. 11 and the current decimal address (0.544)
Is output to the interpolator 1104 and the carry is output to the integrator 1103, respectively.

FIG. 14 is a block diagram of the address controller 1102 of FIG. In FIG. 14, the current integer address (4) input from the address generator 1101 of FIG. 11 having the configuration of FIG. 12 is transmitted from the selector 1401 via the address output register 1402 to the DPCM- RO
It is output to M and input to a decrementer 1403. Thereafter, the integer address (3) obtained by subtracting the value 1 by the decrementer 1403 is output to the DPCM-ROM via the selector 1401 and the address output register 1402.

FIG. 15 is a block diagram of a conventional example of the integrator 1103 of FIG. As described above, the DPC-value is determined by the integer address (3) decremented by one.
Data input register 150 for integration read from ROM
The difference value D ₁ of the input data set to ₁ (see FIG. 17) and the integrated value S ₁ read from the integrated value storage memory 1502 and stored in the integrated value output register 1503 are calculated by an integral operation ALU (arithmetic logic). (unit) 1504 is calculated as follows.

That is, the address generator 1101
If there is no carry output from, the integrated value output register 1
Integral values from 503 is output as the ALU1504, also if there is a carry is added the difference value D ₁ is from integrating data input register 1501 to the integration values S ₁ from the integrated value output register 1503 integrated value S ₂ (see FIG. 17), and the integrated value is output from the integrator 1103 to the interpolator 1104.

FIG. 16 is a block diagram of the interpolator 1104 shown in FIG. In FIG. 16, the current integer address (4)
The difference value D _2, which is the input data read by the data input register 1601 and stored in the data input register 1601,
Is multiplied by the current decimal address (0.544), and the multiplied output D
h is added by the adder 1604 to the integral value S ₂ output from the integrator 1103 of FIG. 11 having the configuration of FIG. 15 and stored in the integral value register 1603, and the amplitude value at the current value address (4.544) is obtained. are a ₂ (see FIG. 17).

[0019] As described above, first, in order to obtain the amplitude value at the current integer address (4) in FIG. 17, the integrated values S ₁ of address (3), the address (3) in the stored address (3 ) - (4) the difference value D ₁ of the between is added together, yet as the interpolation calculation, the integral value S ₂ is an amplitude value at address (4), the address stored in the current integer address (4)
(4) - (5) by the value Dh obtained by multiplying the fractional portion of (0.544) the difference value D ₂ between are added, the current value address (4.5
The amplitude value A ₂ of the waveform data obtained in 44).

The above description is for the case where the step amount ≦ 1. Next, the case where the step amount> 1 will be described with reference to a specific example of FIG. The example of FIG. 18 is an example of a case where waveform data corresponding to the pitch name A4 is obtained. Here, the pitch ratio between the A4 sound and the C4 sound is about 1.68> 1. And the current value address is
3.75, i.e., integer address (3), decimal address
It is assumed that the amplitude value A ₁ of the waveform data at the current value address has been obtained as (0.75).

In this case, as in the case where the step amount ≦ 1, the address integer part register 1202 shown in FIG.
Outputs the integer address (3), and the address decimal part register 1203 outputs the decimal address (0.75). On the other hand, the address increment (1.68) is output from the address increment storage memory 1204, and the address increment (1.68) is added to the decimal address (0.75) by the binary adder 1206 which performs the addition operation of the decimal part. You.

As a result, a decimal part (0.43) is obtained, and two carry signals are output from the binary adder 1206 to the incrementer 1207.
The current integer address (5) is output from 207. At the same time, the current decimal address (0.4
3) is output, and the new current value address (5.43) is stored in the current value address storage memory 1201.

[0023]

As will be understood from the above description of the operation, when the increment is larger than 1, the address generator shown in FIG. 12 uses the address generator shown in FIG. The new current integer address (5) to which the binary value (1.68) is added jumps over the integer address (4).

For this reason, if a jump occurs in the integer part of the current value address, the DPCM-
The difference value data of the skipped integer address stored in the ROM is ignored.

As a result, in the DPCM method in which the difference value at each address must be sequentially accumulated, a correct waveform cannot be obtained, and the waveform becomes different from the original waveform at that time.

As described above, in the conventional DPCM type waveform data reading apparatus, the integer part address cannot be skipped by the step amount corresponding to the pitch, and therefore, as shown in FIG. There has been a problem that the waveform data having a frequency higher than the original sound frequency cannot be generated because the frequency cannot be increased to a decimal part or more.

An object of the present invention is to enable a tone data having a frequency equal to or higher than the original sound frequency to be generated in a waveform data reading device of the DPCM system.

[0028]

According to the present invention, first, there is provided difference value data storage means for storing difference value data between sample values of waveform information.

Next, address data generation for updating and generating the address data for reading the difference value data from the difference value data storage means based on the address data increment amount specified based on the pitch information from the musical instrument or the like. Having means.

The address data is generated by the address data generating means.
Address based on the integer part of the
Number of consecutive integer addresses corresponding to the update amount of the integer part of the
Address data control means for generating dress data;
Each integer address sequentially output from the address data control means
Data from the difference value data storage means
Of the difference value data
And integration calculating means for sequentially integrating the difference value data excluding the minute value data .

Then, the integral value data obtained by the integral operation means is obtained.
Data and the last value read from the difference value data storage
The difference value data and the address data
Performs an interpolation operation based on the decimal part of the address data
To generate and output waveform data.
Data output means.

[0032]

The original waveform information is reproduced by successively reading out successive difference value data from the difference value data storage means and sequentially integrating them.

On the other hand, the address data generation means updates the address data for reading the difference value data from the difference value data storage means based on the address data step amount, so that the original waveform information is updated. Thus, it is possible to generate waveform data whose pitch has changed. Therefore,
Such waveform data can be used as a sound source of an electronic musical instrument or the like.

Here, for example, the address data increment is 1
Larger, if the process proceeds address more on difference data storage means by updating the address data in the address data generating means, further from the integer portion of the pre-update address
Each integer address up to the integer part of the new address
The difference value data read by the data is sequentially read from the difference value data storage means and integrated.

As a result, even when the address data increment is larger than 1, appropriate integrated value data can be calculated. Then, with respect to the integral value data obtained in this way, the integer part of the updated address data
The read difference value data and the small
By performing an interpolation operation based on several parts, waveform data can be generated and output.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, the overall configuration of the embodiment of the present invention is the same as the above-described general configuration of FIG. However, the address controller 1101 sends the integrator 1103
Is input with a carry and a step change amount described later. Configuration of Address Generator FIG. 1 is a block diagram of an address generator 1101 in FIG. 11 according to an embodiment of the present invention.

In FIG. 1, the current value address read from the current value address storage memory 101 corresponds to the aforementioned DP.
It is separated into an address upper part (an integer part excluding the first lower digit of the integer part) and a lower address part (the first digit and the decimal part of the integer part) for CM-ROM addressing. Set to 103.

From the address increment storage memory 104, the address increment proportional to the pitch (pitch) of the musical tone to be played is read out, and the address increment register 10 is read.
Set to 5.

The address increment and the current value address have the correspondence shown in FIG. 2, and the address increment corresponds to the lower one digit of the integer part of the current value address and the subsequent decimal part. I have.

Returning to FIG. 1, the binary address adder 106 adds the address lower part read from the address lower register 103 and the address increment read from the address increment register 105. You. Binary adder 106 performs an addition operation in the range of one digit of the integer part and the decimal part, and outputs the lower part of the current address. In this case, when the first digit of the decimal part carries, the binary adder 106
Outputs a carry when the value of the integer part is incremented by one and the first digit of the integer part carries.

On the other hand, the incrementer 107 adds the binary adder 1 to the upper part of the input current value address.
If there is no carry output from 06, it is output as it is as the upper address of the current address. If there is a carry output, it is incremented and output as the upper address of the current address.

Next, the upper part of the current address and the lower part of the current address are set in the current value address storage memory 101 as the updated current value address, and the integer parts of the upper part of the current address and the lower part of the current address are The current integer address to the address controller 1102 of FIG. 11 in the embodiment of the present invention, and the decimal part of the lower part of the current address as the current decimal address in FIG.
Are transferred to one interpolator 1104.

The lower two bits of the integer part of the current value address read from the current value address storage memory 101 are stored in the previous address step register 108, and the lower two bits of the integer part of the updated current value address are stored. At the same time, the calculation is performed by the step calculator 109 in accordance with the calculation truth table shown in FIG. 3, and the calculation result is output to the integrator 1103 of FIG. 11 in the embodiment of the present invention as the step change amount. Configuration of Address Controller Next, a block diagram of the address controller 1102 of FIG. 11 in the embodiment of the present invention is the same as the configuration of FIG. 14 described above.

However, in the embodiment of the present invention, in addition to the current integer address and the integer address obtained by subtracting the value 1 by the decrementer 1403, the subtracted integer address is further reduced by the value 1 by the decrementer 1403. An integer address can be output to the DPCM-ROM. Diagram 4 of the integrator, the integrator 110 of FIG. 11 in the embodiment of the present invention
FIG. 3 is a block diagram of a third embodiment.

In FIG. 4, first, the integral value memory 404
The integrated value read from the
Is stored in On the other hand, in the address controller 1102 of FIG. 11 according to the embodiment of the present invention, the DPCM-R
The difference value data read from the OM is stored in the difference value register 402 of # 2. The difference value data read from the DPCM-ROM by the address obtained by subtracting the value 2 from the current integer address in the address controller 1102 is stored in the # 1 difference value register 401.

When the step change amount input from the address generator 1101 of FIG. 11 having the configuration of FIG. 1 is 0 as described later, the integrated value storage register 4
05 is selected by the integral value selector 406 and input to the integral value calculation ALU 407. The integral value operation ALU 407 stores the integral value in the integral value output register 408 as it is.

When the step change amount is 1 as described later, the difference value data stored in the difference value register 402 of # 2 is selected by the difference value selector 403 and input to the integral value calculation ALU 407. On the other hand, the integral value stored in the integral value storage register 405 is selected by the integral value selector 406, and the integral value calculation ALU 407
Is input to The integral value operation ALU 407 accumulates the integral value from the integral value storage register 405 with the difference value data from the # 2 difference value register 402. The accumulation result is stored in the integrated value output register 408.

Further, when the step change amount is 2 as described later, first, at the first timing, # 1
The difference value data stored in the difference value register 401 is selected by the difference value selector 403, and the integrated value calculation A
LU 407, while the integrated value storage register 40
5 is selected by the integral value selector 406 and input to the integral value calculation ALU 407. The integral value operation ALU 407 accumulates the integral value from the integral value storage register 405 with the difference value data from the difference value register 401 of # 1. The accumulation result is stored in the integrated value output register 408. Next, at the second timing, the difference value data stored in the difference value register 402 of # 2 is selected by the difference value selector 403 and input to the integral value calculation ALU 407, while at the first timing The integral value stored in the integral value storage register 405 is selected by the integral value selector 406, and the integral value operation ALU
407 is input. The integral value calculation ALU 407 accumulates the difference value data from the # 2 difference value register 402 with the integral value obtained at the first timing. The accumulation result is stored again in the integrated value output register 408. Configuration of Interpolator Next, the interpolator 110 of FIG.
The block diagram of FIG. 4 is the same as the configuration of FIG. 16 described above. Operation of Generating Waveform Data According to Specific Examples Next, the operation of the above-described embodiment of the present invention will be described using three specific examples corresponding to step changes 0, 1, and 2. It is assumed that both the address and the address increment have a 4-bit integer part and a 4-bit decimal part, and are data based on floating-point representation. (A) Current value address: 3.25 Address increment: 0.5 FIG. 5 is a diagram (part 1) showing the relationship between the address increment and the amplitude value of waveform data. In this case, even if the address increment is added to the current value address, the current integer address is not updated. FIG. 6 is a diagram (part 1) illustrating a process in which the address increment is added to the current value address, the current value address is updated, and the step change amount is obtained.

First, the current value address (3.25) read from the current value address storage memory 101 in the address generator 1101 of FIG. 11 having the configuration of FIG.
Is represented by 0011: 0100, as shown in FIG. Here, “:” indicates a boundary between the integer part and the decimal part.

Next, when the current value address is DPCM-
It is separated into an upper address part (001) and a lower address part (1: 0100) for ROM addressing, and are set in an address upper register 102 and an address lower register 103, respectively.

The address increment (0.5) (0: 1000) is read from the address increment storage memory 104 and set in the address increment register 105.
Next, the address lower part (1.25) (1: 0100) read from the address lower part register 103 and the address increment read from the address increment register 105
(0.5) (0: 1000) is added by the binary adder 106, and as a result of addition, the lower part (1.75) (1:
1100) is obtained. In this case, the binary adder 1
Since there is no carry of the integer part of 06, no carry is output.

As a result, in the incrementer 107, the output (001) of the address upper register 103
Is output as it is as the current address upper part (001). At this stage, the current integer address becomes (0011 = 3 ₍₁₀₎ ) by the current address upper part (001) and the integer part (1) of the current address lower part, and the current decimal address is
It is equal to the decimal part (0.75) (: 1100) of the lower part of the current address. Here, X ₍₁₀₎ indicates that X is a decimal value.

Next, the current value address (3.75) (0011: 1100) updated by the current address upper part (001) and the current address lower part (1: 1100) is set in the current value address storage memory 101. At the same time, the current integer address (0011 = 3 ₍₁₀₎ ) is output to the address controller 1102 in FIG. 11 and the current decimal address (: 1100) is output to the interpolator 1104 in the embodiment of the present invention.

On the other hand, the lower two digits (11) of the integer part of the current value address (3.25) are stored in the previous address step register 108 as a previous step. Then, for the output of the register 108 and the lower two digits (11) of the integer part of the updated current value address (3.75), which is a new step,
Step calculator 109 performs a calculation shown in a calculation truth table shown in FIG. As a result, in the examples of FIGS.
The step calculator 109 outputs the step change amount 0 to the integrator 1104 in FIG. 11 in the embodiment of the present invention.

Next, in the integrator 1103 of FIG. 11 having the configuration of FIG. 4, the integration value (S _{1 in} FIG. 5) read from the integration value memory 404 is stored in the integration value storage register 40.
5 is stored.

However, in this case, since the step change amount is 0, the addition operation in the integral value operation ALU 407 is not performed, and the contents of the difference value register 401 of # 1 and the difference value register 402 of # 2 are ignored. The integrated value S ₁ is stored in the integrated value output register 408 as it is.

Next, in the interpolator 1104 of FIG. 11 in the embodiment of the present invention having the configuration of FIG. 16, the data input register 1 is read out by the current integer address (3).
₁₁ is multiplied by the current decimal address (0.75) in the multiplier 1602, and the multiplied output Dh is output from the integrator 1 shown in FIG.
An adder 1604 adds the integral value S ₁ output from the inverter 103 to the integral value S ₁ stored in the integral value register 1603 to obtain an amplitude value A _{2 at the} current value address (3.75) (FIG. 5).
reference). (B) Current value address: 3.75 Address increment: 0.5 FIG. 7 is a diagram (part 2) showing the relationship between the address increment and the amplitude value of the waveform data. In this case, the address increment is added to the current value address, and the current integer address is incremented by +
1 is updated. FIG. 8 is a diagram (part 2) illustrating a process in which the address increment is added to the current value address, the current value address is updated, and the step change amount is obtained.

First, the current value address (3.25) read from the current value address storage memory 101 in the address generator 1101 of FIG.
Is represented by 0011: 1100 as shown in FIG.

Next, when the present value address is DPCM-
The address is separated into an upper address part (001) and a lower address part (1: 1100) for ROM addressing, and are set in an address upper register 102 and an address lower register 103, respectively.

The address increment (0.5) (0: 1000) is read from the address increment storage memory 104 and set in the address increment register 105. Next, the address lower part (1.75) (1: 1100) read from the address lower register 103 and the address increment read from the address increment register 105
(0.5) (0: 1000) is added by the binary adder 106, and as a result of addition, the lower part of the current address (0.25) (0: 1000)
0100) and one carry is output to the incrementer 107.

As a result, in the incrementer 107, the output (001) of the upper address register 103 is incremented and output as the current address upper bit (010). At this stage, the current integer address includes the current address upper part (010) and the current address lower part (0).
(0100 = 4 ₍₁₀₎ ), and the current decimal address is the decimal part (0.25) (: 010) of the lower part of the current address.
0).

Next, the current value address (4.25) (0100: 0100) updated by the current address upper part (010) and the current address lower part (0: 0100) is set in the current value address storage memory 101. At the same time, the current integer address (0100 = 4 ₍₁₀₎ ) is output to the address controller 1102 of FIG. 11 and the current decimal address (: 0100) is output to the interpolator 1104 in the embodiment of the present invention.

On the other hand, the lower two digits (11) of the integer part of the current value address (3.75) are stored in the previous address step register 108 as a previous step. Then, for the output of the register 108 and the new step that is the lower two digits (00) of the integer part of the updated current value address (4.25),
Step calculator 109 performs a calculation shown in a calculation truth table shown in FIG. As a result, in the examples of FIGS. 7 and 8,
The step calculator 109 outputs the step change amount 1 to the integrator 1104 in FIG. 11 in the embodiment of the present invention.

Thereafter, the current integer address (4) output from the address generator 1101 is transmitted from the selector 1401 in FIG. 14 in the address controller 1102 in FIG.
Output to the ROM and input to the decrementer 1403. Next, the integer address (3) obtained by decrementing the value 1 by the decrementer 1403 is similarly input to the selector 140
1. DPCM via the address output register 1402
-Output to ROM and input to decrementer 1403 again. Then, decrementer 140
The integer address (2) obtained by further subtracting the value 1 by 3 is similarly output to the selector 1401 and the address output register 1402.
Is output to the DPCM-ROM.

Next, in the integrator 1103 of FIG. 11 having the configuration of FIG. 4, the integrated value (S _{1 of} FIG. 7) read from the integrated value memory 404 is stored in the integrated value storage register 40.
5 is stored.

On the other hand, in the address controller 1102 of FIG. 11 according to the embodiment of the present invention, the DPCM-address is obtained by subtracting the value 1 from the current integer address by address (3).
Difference value data read from the ROM (D _{1 in} FIG. 7)
Are stored in the difference value register 402 of # 2. Also,
The address controller 1102 uses the address (2) obtained by subtracting the value 2 from the current integer address to obtain the DPCM-
The difference value data read from the ROM is stored in the difference value register 401 of # 1. When the step change amount is 1, the difference value data stored in the difference value register 401 of # 1 is integrated. Not used for operation and ignored.

Next, as described above, the step change amount is 1
In the case of, the difference value data (D ₁ ) stored in the difference value register 401 of # 2 is selected by the difference value selector 403 and input to the integral value calculation ALU 407, while
Integral value (S ₁ ) stored in integral value storage register 405
Is selected by the integral value selector 406 and input to the integral value calculation ALU 407. Integral value calculation ALU407
Is the integral value (S ₁ ) from the integral value storage register 405
Then, the difference value data (D ₁ ) from the difference value register 401 of # 2 is accumulated. The accumulation result (S _{2 in} FIG. 7) is
It is stored in the integrated value output register 408.

Next, in the interpolator 1104 of FIG. 11 in the embodiment of the present invention having the configuration of FIG. 16, the data input register 1 is read out by the current integer address (4).
Difference value D ₂ is the input data stored in the 601 is multiplied by the multiplier 1602 and the current fractional addresses (0.25), the multiplication output Dh is, the integrator 1 of Figure 11 having the configuration of FIG. 4
The adder 1604 adds the integral value S ₂ output from the register 103 to the integral value S ₂ stored in the integral value register 1603 to obtain the amplitude value A _{2 at the} current value address (4.25) (FIG. 7).
reference). (C) Current value address: 3.75 Address increment: 1.5 FIG. 9 is a diagram (part 3) showing the relationship between the address increment and the amplitude value of waveform data. In this case, the address increment is added to the current value address, and the current integer address is incremented by +
2 is updated. FIG. 10 is a diagram (part 3) illustrating a process in which the address increment is added to the current value address, the current value address is updated, and the step change amount is obtained.

First, the current value address (3.75) read from the current value address storage memory 101 in the address generator 1101 of FIG. 11 having the configuration of FIG.
Is represented by 0011: 1100 as shown in FIG.

Next, the present value address is set in the DPCM
-Address upper part for ROM addressing (001)
And address lower part (1.75) (1: 1100)
These are set in the address upper register 102 and the address lower register 103, respectively. Also, the address increment amount (1.5) is read from the address increment storage memory 104.
(1: 1000) is read out and set in the address increment register 105.

Next, the lower address part (1.75) (1: 1100) read from the lower address register 103 is read.
And the address increment (1.5) (1: 1000) read from the address increment register 105 are added by the binary adder 106.
(1.25) (1: 0100) is obtained, and one carry is output to the incrementer 107.

As a result, in the incrementer 107, the output (001) of the address upper register 103 is incremented and output as the current address upper part (010). At this stage, the current integer address includes the current address upper part (010) and the integer part (1) of the current address lower part.
(0101 = 5 ₍₁₀₎ ), and the current decimal address is the decimal part (0.25) (: 010) of the lower part of the current address.
0).

Next, the current value address (5.25) (0101: 0100) updated by the current address upper part (010) and the current address lower part (1: 0100) is set in the current value address storage memory 101. At the same time, the current integer address (0101 = 5 ₍₁₀₎ ) is output to the address controller 1102 in FIG. 11 and the current decimal address (: 0100) is output to the interpolator 1104 in the embodiment of the present invention.

On the other hand, the lower two digits (11) of the integer part of the current value address (3.75) are stored in the previous address step register 108 as a previous step. Then, for the output of the register 108 and the new step which is the lower two digits (01) of the integer part of the updated current value address (5.25),
Step calculator 109 performs a calculation shown in a calculation truth table shown in FIG. As a result, in the examples of FIGS. 9 and 10, the step calculator 109 outputs the step change amount 2 to the integrator 1104 of FIG. 11 in the embodiment of the present invention.

Thereafter, the current integer address (5) output from the address generator 1101 is transmitted from the selector 1401 shown in FIG. 14 in the address controller 1102 shown in FIG.
Output to the ROM and input to the decrementer 1403. Next, the integer address (4) obtained by decrementing the value 1 by the decrementer 1403 is similarly input to the selector 140.
1. DPCM via the address output register 1402
-Output to ROM and input to decrementer 1403 again. Then, decrementer 140
In addition, the integer address (3) further subtracted by the value 1 in the selector 3 and the selector 1401, the address output register 1402
Is output to the DPCM-ROM.

Next, in the integrator 1103 of FIG. 11 having the configuration of FIG. 4, the integrated value (S _{1 in} FIG. 9) read from the integrated value memory 404 is stored in the integrated value storage register 40.
5 is stored.

On the other hand, in the address controller 1102 of FIG. 11 according to the embodiment of the present invention, the address (4) obtained by subtracting the value 1 from the current integer address is used for DPCM-
Difference value data read from the ROM (D _{2 in} FIG. 9)
Are stored in the difference value register 402 of # 2. Also,
The address controller 1102 uses the address (3) obtained by subtracting the value 2 from the current integer address to obtain the DPCM-
Difference value data read from the ROM (D _{1 in} FIG. 9)
Are stored in the difference value register 401 of # 1.

Next, as described above, the step change amount is 2
In the case of ( ₁ ), first, at the first timing, the difference value data (D ₁ ) stored in the difference value register 401 of # 1 is selected by the difference value selector 403 and input to the integral value calculation ALU 407. , The integral value (S ₁ ) stored in the integral value storage register 405 is selected by the integral value selector 406 and input to the integral value calculation ALU 407. The integral value calculation ALU 407 accumulates the difference value data (D ₁ ) from the difference value register 401 of # 1 with the integral value (S ₁ ) from the integral value storage register 405.
The accumulation result (S _{2 in} FIG. 9) is stored in an integrated value output register 4
08 is stored.

Subsequently, at the second timing, # 2
The difference value data (D ₂ ) stored in the difference value register 402 is selected by the difference value selector 403 and input to the integral value operation ALU 407, while being stored in the integral value storage register 405 at the first timing. The integration value (S ₂ ) is selected by the integration value selector 406 and input to the integration value calculation ALU 407. Integral value calculation ALU407
Accumulates the difference value data (D ₂ ) from the # 2 difference value register 402 with the integral value (S ₂ ) obtained at the first timing. The accumulation result (S in FIG. 9)
₃ ) is stored in the integrated value output register 408 again.

Next, in the interpolator 1104 of FIG. 11 according to the embodiment of the present invention having the configuration of FIG. 16, the data input register 1 is read by the current integer address (5).
Difference value D ₃ which is the input data stored in the 601 is multiplied by the multiplier 1602 and the current fractional addresses (0.25), the multiplication output Dh is, the integrator 1 of Figure 11 having the configuration of FIG. 4
An adder 1604 adds the integral value S ₃ output from the terminal 103 to the integral value S ₃ stored in the integral value register 1603 to obtain the amplitude value A _{2 at the} current value address (5.25) (FIG. 9).
reference).

As described above, the integer part of the current address is changed by the address increment (1.5) larger than 1.
Even when jumping from (3) to (5), correct waveform data can be obtained by using the step change amount (2 in this case).

As described above, in the embodiment of the present invention, the last step which is the lower two digits of the integer part of the current value address and the new step which is the lower two digits of the integer part of the updated current value address are described. From the numerical relationship, it is possible to determine how many integer parts have been increased by the update operation of the current value address, that is, the step change amount. Therefore, the relationship can be held as a table as shown in FIG. 3 and the step change amount can be obtained by referring to the table when updating the address. Then, according to the step change amount, the DPCM-R
By controlling the number of repetitions of the operation of reading the difference value data from the OM and integrating the same, correct waveform data can be generated even if the address increment is a value larger than 1. Other Embodiments In the embodiment of the present invention described above, the address increment is 2 or less and the step change amount is 2 steps or less. However, the present invention is not limited to these. For example, if the address increment is allowed to be 3 or less, the following may be performed.

That is, the current value address is separated into an upper address portion consisting of an integer part excluding the lower two digits and a lower address portion consisting of the lower two digits of the integer portion and a decimal part. Next, an address increment of two digits of the integer part and a decimal part is added to the lower part of the address. Then, as a result of this addition,
When a carry occurs, the value in the upper part of the address is incremented. In addition, the lower 3 of the integer part of the original current value address
The digit and the last three digits of the integer part of the updated current value address are compared to calculate a step change amount of 0 to 3, and the difference value data of a number corresponding to the step change amount is sequentially transmitted to the DPCM-
The data is read from the ROM and the integration operation is performed. Then, the DPC corresponding to the integration result and the integer part of the current value address is performed.
An interpolation operation is executed based on the difference value read from the M-ROM and the decimal part of the current value address to obtain desired waveform data.

[0084]

According to the present invention, even when the address data increment is larger than 1, appropriate integral value data is calculated based on the difference value data stored in the difference value data storage means. Thus, it is possible to generate and output waveform data with respect to the appropriate integrated value data obtained as described above.

As a result, in the waveform data reading device of the DPCM system, it is possible to generate a musical tone having a pitch higher than the original pitch of the original waveform information. Therefore, the sound source of the electronic musical instrument can be made with a much smaller storage capacity than the conventional PCM sound source, and the production cost can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an address generator according to an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence relationship between a current value address and an address increment according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation truth table in a step calculator.

FIG. 4 is a block diagram of an integrator according to an embodiment of the present invention.

FIG. 5 is a diagram (part 1) illustrating a relationship between an address step amount and an amplitude value of waveform data according to the embodiment of the present invention.

FIG. 6 is a diagram (part 1) illustrating a process in which a step change amount is obtained from a current value address and an address increment.

FIG. 7 is a diagram (part 2) illustrating a relationship between an address increment and an amplitude value of waveform data according to the embodiment of the present invention.

FIG. 8 is a diagram (part 2) illustrating a process of obtaining a step change amount from a current value address and an address increment.

FIG. 9 is a diagram (part 3) illustrating a relationship between an address increment and an amplitude value of waveform data according to the embodiment of the present invention.

FIG. 10 is a diagram (part 3) illustrating a process of obtaining a step change amount from a current value address and an address increment.

FIG. 11 is an overall configuration diagram of a waveform data reading device.

FIG. 12 is a block diagram showing a part of a conventional address generator.

FIG. 13 is a diagram showing a correspondence relationship between a current value address and an address increment in a conventional example.

FIG. 14 is a block diagram of an address controller.

FIG. 15 is a block diagram of a conventional integrator.

FIG. 16 is a block diagram of an interpolator.

FIG. 17 is a diagram (part 1) illustrating a relationship between an address step amount and an amplitude value of waveform data in a conventional example.

FIG. 18 is a diagram (part 2) illustrating a relationship between an address increment and an amplitude value of waveform data in a conventional example.

[Explanation of symbols]

 Reference Signs List 101 Current value address storage memory 102 Upper address register 103 Lower address register 104 Address increment storage memory 105 Address increment register 106 Binary adder 107 Incrementer 108 Previous address step register 109 Step calculator 401 Difference value register # 1 402 Difference value register # 2 403 Difference value selector 404 Integration value memory 405 Integration value storage register 406 Integration value selector 407 Integration value operation ALU 408 Integration value output register 1101 Address generator 1102 Address controller 1103 Integrator 1104 Interpolator 1201 Current value address Storage memory 1202 Address integer register 1203 Address fraction register 1204 Address increment storage memory 1205 Add Scan increment amount register 1401 selector 1402 address output register 1403 decrementer 1501 integrating data input register 1502 integrated value storage memory 1503 integrated value output register 1504 integral calculation ALU 1601 data input register 1602 multiplier 1603 integral value register 1604 adder

Claims (1)

(57) [Claims] 1. A difference value data storage means for storing difference value data between sample values of waveform information, and reading the difference value data from the difference value data storage means based on a designated address data increment. Data generating means for updating and generating address data for use with the address data generated by the address data generating means
The integer of the address data based on the integer part of the data
Number of consecutive integer address data according to the
Address data control means for generating, and each of the alignments sequentially output from the address data control means.
The difference value data storage means corresponding to several address data;
Of the difference value data sequentially read from
Integrate sequentially the difference value data excluding the issued difference value data
Integral operation means, integral value data obtained by the integral operation means, and the difference value
Difference value data last read from the data storage means
And an address generated by the address data generating means.
Perform interpolation calculations based on the decimal part of the
Waveform data output that generates and outputs waveform data
Means for reading waveform data.