JPH08221075A - Musical sound signal generating device - Google Patents

Abstract

PURPOSE: To suppress the occurrence of the cumulative error of the waveform data in waveform reproduction by an ADPCM system and a DPCM system by respectively providing a waveform storage means, a read-out means, a temporary storage means, a decoding means and a musical sound signal generation means specified. CONSTITUTION: The waveform storage means stores the specified waveform data Wj formed based on the specified sampling data Dj selected from the sampling data Di of a musical sound waveform and the difference waveform data ΔWDn obtained subtracting the sampling data Dn-1 from the sampling data Dn . The read-out means reads out successively the Wj or the ΔWDn from the waveform storage means. The decoding means generates the sampling data YDj when the read-out means reads out the Wj to store them in the temporary storage means, and cumulates the ΔWDn in the temporary storage means when the read-out means reads out the ΔWDn to generate the sampling data YDn . The musical sound signal generation means generates a musical sound signal based on the obtained sampling data YDj or YDn .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone signal generator which generates a musical tone signal based on waveform data stored in a waveform memory in advance.

[0002]

2. Description of the Related Art A conventional electronic musical instrument has a tone signal generator. This tone signal generator generates tone signals based on the waveform data stored in advance in the waveform memory. Waveform data in, for example, PCM format is stored in the waveform memory. The PCM data is created by sampling a tone waveform at a predetermined cycle, quantizing it, and further encoding it. Then, the PCM data is sequentially read from the waveform memory according to the sounding instruction, and a musical tone signal is generated based on the read PCM data.

In such a tone signal generator,
In order to generate a tone signal corresponding to a large number of tones, it is necessary to store a huge amount of PCM data in the waveform memory in advance. Therefore, in order to reduce the amount of waveform data,
A method has been proposed in which M data is compressed and stored in a waveform memory, and the compressed waveform data from the waveform memory is expanded when a musical sound is generated. As such a method, for example, ADPCM (Adaptive Differential Pulse Code Modula)
method or DPCM (Differential PulseCode Modul)
ation) method is known. In these methods, the difference waveform data created by calculating the difference between the sampling data at the adjacent sample points of the tone waveform is stored in the waveform memory, and when the tone is generated, the difference waveform data from the waveform memory is accumulated. A musical tone signal is reproduced by being calculated.

The following method is also generally adopted in order to reduce the amount of waveform data to be stored in the waveform memory. That is, for example, as shown in FIG. 12, only a predetermined section (attack section) at the beginning of the musical tone waveform and a predetermined section (repeat section) of the subsequent musical tone waveform are stored in the waveform memory. Then, when a musical tone signal is generated, the attack portion is read only once from the beginning, and then the repeat portion is repeatedly read. The tone signal generator generates a tone signal based on the read waveform data.

However, the above-mentioned ADPCM has been conventionally used.
The system and the DPCM system were rarely adopted as a musical tone signal generator for electronic musical instruments. This is because the following first problem and second problem existed. The first problem is that a cumulative error occurs when a method of repeatedly accumulating the waveform data of the repeat part is adopted. The second problem is that since the sampled musical tone waveform is discrete, it is necessary to interpolate between two adjacent sampling points in order to generate a musical tone having a desired pitch. The problem is that the circuit of becomes complicated.

Despite the problems described above, AD
Since the PCM method or the DPCM method can reduce the amount of waveform data, research for practical use is active. For example, as a means for solving the first problem described above, Japanese Patent Laid-Open No. Sho 62-62
No. 242995 discloses a "tone signal generator". This device eliminates the accumulated error by always using the last data of the attack part at the head part of the repeat part when decoding the coded waveform data which is repeatedly read.

However, in this tone signal generator, a comparison circuit for determining whether or not it is the head of the repeat section, selectors 107 and 117, and a latch 106 for storing data (Δn, Sn + εn) at the time of attack end. And 118 and the like are required, so that there is a drawback that the circuit becomes complicated. Further, the method disclosed in Japanese Patent Laid-Open No. 62-242995 has a drawback that the control method becomes complicated when the waveform data includes a plurality of repeat parts, and the circuit becomes complicated.

The second problem has not been solved yet. For example, if the frequency number (F number) is fixed at "1", the waveform read address for reading the waveform data from the waveform memory is sequentially incremented by "+1", so that interpolation is not necessary. However, the actual electronic musical instrument is
Since it requires a tune function (a function that shifts the pitch level in cents for the entire instrument), a portamento function, a glide function, etc., it is necessary to perform interpolation for fine pitch control. Interpolation requires a complicated control circuit because complicated control is required to generate a musical sound by accessing one sampling data multiple times depending on the pitch.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and when a tone signal is reproduced by the ADPCM system or the DPCM system, it has a simple circuit structure. , It is possible to suppress the generation of cumulative error due to repeated reading of waveform data, and
It is an object of the present invention to provide a musical tone signal generator capable of suppressing the accumulated error when not being repeatedly read.

[0010]

In order to achieve the above-mentioned object, the tone signal generator of the present invention uses (A) a tone waveform at a sampling point P _i (where i = 0, 1, 2, ... , N
-1) Specific sampling data D _j selected from sampling data D _i obtained by sampling in
(However, 0 ≦ j ≦ N−1) specific waveform data W _j and sampling data D _n (where n =
1, 2, ... N−1, and waveform storage means for storing differential waveform data ΔWD _n obtained by subtracting the sampling data D _n−1 from n ≠ j), and (B) From the waveform storage means, the specific waveform data W _j or the differential waveform data Δ
A reading means for sequentially reading WD _n , (C) temporary storage means, and (D) sampling data YD _j is generated when the reading means reads the specific waveform data W _j , and the sampling data YD _j is temporarily stored. A decoding means for storing in the storage means, accumulating the difference waveform data ΔWD _n in the temporary storage means when the reading means reads the difference waveform data ΔWD _n , and thereby generating sampling data YD _n ; )
Tone signal generating means for generating a tone signal based on the obtained sampling data YD _j or YD _n .

The specific waveform data W _j and the differential waveform data ΔWD _n stored in the waveform storage means are produced, for example, as follows. First, as shown in FIG. 12, for example, a musical tone attack portion and a repeat portion in a predetermined section subsequent thereto are extracted. Next, the extracted attack part and repeat part are sampled at a predetermined cycle to obtain a plurality of sampling data D _i (i = 0, 1, 2, ..., N−).
1) is obtained. Specific sampling data D _j (0 ≦ j ≦ N
-1) is selected from N samplings D _i .
The content of the specific sampling data D _j is a predetermined value.
The number of specific sampling data D _j can be 1 or more. The specific waveform data W _j is created (converted) based on the specific sampling data D _j . The specific waveform data W _j has the same format as the specific sampling data D _j ,
For example, it can be in PCM format. The content of the specific waveform data W _j can be the same as or different from the content of the specific sampling data D _j . Differential waveform data DerutaWD _n is obtained by subtracting the sampling data D _n-1 from the sampled data D _n (where, n = 1, 2, a · · · N-1, and n ≠
j). The differential waveform data ΔWD _n is in DPCM format or A
It is in DPCM format.

In the tone signal generating apparatus of the present invention, when the differential waveform data ΔWD _n is read out from the waveform storage means by the reading means, the differential waveform data ΔWD.
_n is accumulated in the temporary storage means. That is, the read difference waveform data ΔWD _n and the sampling data YD _n-1 stored in the temporary storage means are calculated, for example, added, and the sampling data YD _n is reproduced. The obtained sampling data YD _n is used to generate a tone signal. By repeating this accumulation, sampling data YD _n (n = 1, 2, ...
..) is continuously updated, and a musical tone signal that changes over time is generated.

On the other hand, the specific waveform data W is read by the reading means.
_{When j} is read from the waveform storage means, the decoding means generates sampling data YD _j . The contents of the sampling data YD _j are the same as the contents of the specific sampling data D _j . Furthermore, the obtained sampling data YD
_j is the difference waveform data ΔWD _n (n = j + 1, j + 2, ...
..) is stored in the temporary storage means as initial sampling data for accumulating.

According to the above configuration, it is possible to eliminate the accumulated error peculiar to the ADPCM system or the DPCM system. Further, according to the musical tone signal generator, not only the case where the specific waveform data W _j or the differential waveform data ΔWD _n is repeatedly read but also the case where the specific waveform data W _j or the differential waveform data ΔWD _n is read only once is accumulated. The error can be removed.

Further, in a preferred embodiment of the tone signal generating apparatus of the present invention, the reading means is an F number generating means for generating an F number for designating a pitch, and an F number from the F number generating means. And an F number accumulating means for generating a waveform read address composed of an integer part and a decimal part, the read means comprising: The specific waveform data W _j is the difference waveform data ΔW when the integer part of the waveform read address is n.
Each D _n is read from the waveform storage means, and the decoding means includes an interpolating means, which interpolates between the sampling data YD _{n + 1} and YD _n or the sampling data YD.
Interpolation is performed between _{j + 1} and YD _j according to the value of the decimal part of the waveform read address to obtain interpolation data, and the tone signal generating means further generates a tone signal based on the interpolation data YD. To do.

In this preferred embodiment, for example, when a key-on is instructed, the pitch F is designated.
The number is generated by the F number generating means.

According to this preferred embodiment, there is an effect that it is possible to achieve a musical tone signal generator capable of fine pitch adjustment.

In the tone signal generator of the present invention, the content of the specific sampling data D _j can be zero. The content of the specific waveform data W _j is, for example, the minimum value “8000H” (“H” at the end indicates that it is a hexadecimal number. The same applies below) or the maximum value “7FF.
FH "or a value near any one of these. This content can be expressed in two's complement format. Normally, the content of the difference waveform data ΔWD _n does not have the above value. Therefore, the specific waveform data W _j is
It can be distinguished from the difference waveform data ΔWD _n .

When the specific waveform data W _j is read out from the waveform storage means when a tone signal is generated, the sampling data YD _n-1 reproduced by being accumulated in the temporary storage means until then is discarded, Sampling data YD _j
Is set in the temporary storage means as new sampling data. As a result, the sampling data YD
_The accumulation is restarted from _j .

When actually sampling the tone waveform, at important points such as the beginning position (start address SA), loop start position (loop top address LT), and loop end position (loop end address LE) of the tone waveform. Often selected to be the specific sampling data D _j .

In the tone signal generator of the present invention, the content of the specific sampling data D _j can be within a predetermined spread range. Such a predetermined spread is
For example, it can be set to 1/256 times the maximum allowable content of the sampling data D _i . In this case, since the content of the specific sampling data D _j is within the predetermined spread range, the specific waveform data W _j can be easily produced, unlike the case where the content of the specific sampling data D _j has no spread. .

In a preferred embodiment of the tone signal generator of the present invention, the differential waveform data ΔWD _n-1 is the sampling data D _M-1 (where 1≤M≤N-3) to D _N-2.
Is obtained by subtracting, where j is M <j <N
−1 is satisfied, the reading means sets the difference waveform data ΔWD.
After reading _N-1 , the differential waveform data ΔWD _M is read again. According to this preferred embodiment, the value "M"
Is the content of the loop top address LT, and the value "N"
Is the content of the loop end address LE.

Furthermore, in another preferred embodiment of the tone signal generator of the present invention, the specific waveform data W _j is j =
The waveform is stored at a position designated by M in the waveform storage means, and the reading means reads the differential waveform data ΔWD _N−1 , and then, again, the specific waveform data W _j (where j =
Read M). In this preferred embodiment, the value "M" is the content of the loop top address LT and the value "N" is the content of the loop end address LE.

As described above, the tone signal generating apparatus of the present invention has a simple circuit structure, but has an ADP
Not only is it possible to suppress the occurrence of cumulative errors due to repeated reading when a tone signal is generated by the CM or DPCM method, but it is also possible to suppress cumulative errors when not being repeatedly read.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a tone signal generating apparatus of the present invention will be described in detail below with reference to the drawings. The musical tone signal generator is composed of a tone generator circuit and a CPU for controlling the tone generator circuit. However, since the configuration and operation of the CPU are well known, the configuration and operation of the tone generator circuit will be mainly described below.

(First Embodiment) The tone signal generator of the first embodiment generates a tone signal without interpolating sampling data. In the tone signal generator of the first embodiment, the differential waveform data ΔW in ADPCM format is used.
D _n and specific waveform data W _{j in} PCM format are used.

As shown in FIG. 3A, the ADPCM data has a sign (bit 15) and an exponent (bits 14 and 13).
And the mantissa (bits 12 to 0) in the floating point format. This ADPCM data is created as follows. As shown in FIG. 4, a musical tone waveform is sampled at a sampling point P _i (i = 0, 1, 2, ...
1) sampling, quantizing, and coding to obtain sampling data D _i (i = 0, 1, 2, ... N−
1) is produced. This sampling data D _i is PC
It is in M format and is represented in 2's complement format. Differential waveform data DerutaWD _n is obtained by subtracting the sampling data D _n-1 from the sampled data D _n. However, n = 0,
1, 2, ... N-1, and n ≠ j. The difference waveform data ΔWD _n is in DPCM format and is represented in 2's complement format. Therefore, a positive number or negative number can be expressed. For example, in the example shown in FIG. 4, each sampling data D _{n at the} sampling points P _n and P _n-1
Differential waveform data ΔWD _n (= D representing the difference between the D _n-1 and
_n −D _n−1 ) is obtained as a positive number. Sampling point P
Difference waveform data ΔWD _{n + 1} (= D _{n + 1} −D) representing the difference between each sampling data D _{n + 1} and D _{n at n + 1} and P _n.
n ) is obtained as a negative number.

Difference waveform data Δ thus obtained
WD _n (where n = 1, 2, ... N−1 and n ≠ j) is converted into floating point format data having an exponent according to the magnitude of the absolute value. The difference waveform data ΔWD _n obtained by this conversion is in ADPCM format. The differential waveform data ΔWD _n in the ADPCM format created in this way is stored in the waveform memory 208 described later. The waveform memory 208 corresponds to the waveform storage means of the present invention.

As described above, the difference waveform data ΔWD _n
In the process of creating, the special processing is performed when the content of the sampling data D _{j in} the PCM format is a specific value in the PCM format, for example, zero. That is, in this case, the specific waveform data W _{j in the} PCM format is created based on the specific sampling data D _j . Specific waveform data W _j
Are stored in the waveform memory 208. Here, it is assumed that the content of the specific waveform data W _j is Z11.

In the following, the specific waveform data W _j and a plurality of differential waveform data ΔWD _n (n = 1, 2, ... N-1)
And a group of n ≠ j) is referred to as a “waveform data group”. Further, one of the specific waveform data W _j or the plurality of difference waveform data ΔWD _{n in} the waveform data group is referred to as “waveform data of the waveform data group”.

As the above Z11, for example, the minimum value "8"
000H "or the maximum value" 7FFFH "or a value in the vicinity thereof can be used. In most cases, the content Z11 of the specific waveform data W _j is completely different from the content of the differential waveform data ΔWD _n . Therefore, the specific waveform data W _j can be distinguished from each difference waveform data ΔWD _n . Book first
In the embodiment, the minimum value “8000H” is used as an example of the content (value) Z11.

In the first embodiment, the waveform read address for reading the differential waveform data ΔWD _n or the specific waveform data W _j from the waveform memory 208 is composed of 32-bit data. The lower 16 bits of the waveform read address are used as a decimal address (decimal part). The upper 16 bits of the waveform read address are used as an integer address (integer part).

The loop top address LT is composed of 16-bit data. This loop top address LT corresponds to the integer part of the waveform read address. The loop end address LE is composed of 16-bit data. This loop end address LE corresponds to the integer part of the waveform read address. Loop top address LT
Is used to specify the beginning of the repeat part of the waveform data group. The loop end address LE is used to specify the end portion of the repeat part of the waveform data group.

FIG. 5 shows how the specific waveform data W _j and the differential waveform data ΔWD _n created as described above are stored in the waveform memory 208. That is, at the sampling points P ₀ and P ₁₂₈ , since the contents of the sampling data D ₀ and D ₁₂₈ are zero, the specific waveform data W _j (j = 0 and j = 128) in the PCM format is generated and the address is generated. It is stored in the position of the waveform memory 208 designated by “0” and “128”. The content of the specific waveform data W _j (j = 0 and j = 128), that is, Z11 is “8000H” in this embodiment. Other sampling points P _i (i = 1, 2, ..., 127, 129 ...
.), The sampling data D _i (i = 1, 1
2, ..., 127, 129 ...) are not zero, the sampling data D _n to the sampling data D
By subtracting _n−1 , the difference waveform data ΔWD _n (i = 1, 2, ..., 127, 12) in ADPCM format is obtained.
9 ...) is obtained, and addresses “1”, “2”, ...
It is stored in the position of the waveform memory 208 designated by "127", "129" ... At the position of the waveform memory 208 designated by the address “0”, the specific waveform data W
_{When j} is not stored, the waveform memory 208 in which the content of the sampling data D ₀ is designated by the address “0”
Is stored in the position. In the first embodiment, the loop top address LT (M) is “128”. That is, the content of the waveform memory 208 designated by the loop top address LT (M = “128”) is the specific waveform data W.
_j (j = 128).

(1) Description of Decoding Circuit FIG. 1 is a block diagram showing a decoding circuit 209 (see FIG. 2) applied to the tone generator circuit of the musical tone signal generator. The decoding circuit 209 corresponds to the decoding means and the temporary storage means.

In FIG. 1, the comparator 100 compares the specific waveform data W _j or the difference waveform data ΔWD _n (waveform data of the waveform data group) from the waveform memory 208 with the value Z21. The value Z21 is the same as the content of the specific waveform data W _j . The value Z21 can be stored in a ROM, a register or the like (not shown). As the value Z21,
For example, the minimum value "8000H" or the maximum value "7FF
FH "or a value in the vicinity thereof can be used. The minimum value "8000H" is used as an example of the value Z21. As a result of this comparison, the comparator 100 generates "1" as the control signal when the both match, and "0" otherwise. This control signal is supplied to the input terminal S of the selector 104.

The expansion circuit 101 inputs the differential waveform data ΔWD _n from the waveform memory 208 and converts the differential waveform data ΔWD _n from ADPCM format to DPCM format. This transform restores the compressed quantization width. Conceptually, as shown in FIG.
The value of the mantissa part is left-shifted according to the value of the exponent part of the data. As a result, the ADPCM data is converted into the DPCM data having the two's complement format in the fixed point format.
If the differential waveform data ΔWD _n stored in the waveform memory 208 is in the DPCM format, the expansion circuit 101
Can be removed. When the expansion circuit 101 inputs the specific waveform data W _j from the waveform memory 208, the expansion circuit 101 outputs the converted specific waveform data. The differential waveform data ΔWD _n or the converted specific waveform data is supplied to the gate 102.

The current sample memory 106 corresponds to temporary storage means. Difference waveform data is accumulated in the current sample memory 106. Here, it is assumed that the difference waveform data ΔWD _n-1 is accumulated in the current sample memory 106 and the sampling data YD _n-1 is reproduced and stored in the current sample memory 106. The tone signal generator of the present invention can simultaneously generate a plurality of tone signals. The current sample memory 106 is composed of a plurality of blocks corresponding to a plurality of tone generation channels. Current sample memory 10
Each block of 6 corresponds to each waveform data group. The number of blocks is equal to the number of time divisions. Which block is activated depends on the timing generator 201 which will be described later.
Is determined by the timing signal TC from Hereinafter, such a configuration is referred to as a “time division configuration”. Sampling data YD _n-1 from the current sample memory 106
Is supplied to the B input terminal of the adder 103.

If the coincidence signal CF is "0", the gate 102 outputs the difference waveform data ΔWD _n from the expansion circuit 101.
Alternatively, the converted specific waveform data is passed as it is.
On the other hand, if the coincidence signal CF is "1", zero is output.
The coincidence signal CF is generated by the comparator 210 (see FIG. 2) described later. The coincidence signal CF is “1” when the value of the integer part of the waveform read address is the same as the previous time, and is “0” otherwise. Whether or not the differential waveform data ΔWD _n is accumulated in the sampling data YD _n-1 is determined by this coincidence signal. The output of the gate 102 is supplied to the A input terminal of the adder 103.

The adder 103 adds the output of the gate 102 to the sampling data YD _n-1 from the current sample memory 106. As a result, the next sampling data YD _n is obtained. The sampling data YD _n from the adder 103 is supplied to the B input terminal of the selector 104.

The selector 104 receives either the value Z12 supplied to the A input terminal or the next sampling data YD _n supplied from the current sample memory 106 to the B input terminal according to the control signal from the comparator 100. select. The value Z12 is equal to the content of the specific sampling data D _j , that is, zero. The value Z12 can be stored in a ROM, a register or the like (not shown). When the selector 104 receives the control signal “1” from the comparator 100, the A input terminal of the selector 104 is selected. Accordingly, the selector 104 outputs the sampling data YD _j having the same contents as the specific sampling data D _j to the clear circuit 105. On the other hand, the selector 104 is the comparator 10
When the control signal “0” is received from 0, the B input terminal of the selector 104 is selected. As a result, the selector 104
Outputs the sampling data YD _n to the clear circuit 105.

The clear circuit 105 outputs a clear signal CLRB.
According to the above, the input data is passed as it is or the zero is forcibly output. This clear circuit 105
It is used to clear the contents of the current sample memory 106 when the reading of the waveform data of the waveform data group is started. Therefore, if the waveform data group has data having a value of zero at its head, the clear circuit 105 can be removed in some cases.

Whether the clear circuit 105 is activated and zero is output is determined by the control flag latch 202.
It is controlled by a control signal CLRB from (see FIG. 2). The contents of the control flag latch 202 are set or reset by the data from the CPU (not shown). The output of the clear circuit 105 is supplied to the current sample memory 106. As a result, the sampling data YD _j , YD _n or zero is the current sample memory 10
6 is stored. The output of the clear circuit 105 is also supplied to the multiplier 217.

(2) Description of tone generator circuit FIG. 2 is a block diagram of a first embodiment of a tone generator circuit applied to the musical tone signal generating apparatus. In this sound source circuit,
The decoding circuit 209 described above is included. Hereinafter, the configuration and operation of the tone generator circuit will be described in detail with reference to the block diagram shown in FIG.

The reading means of the present invention comprises a current step memory 203, a selector 204, a current address memory 205, an adder 206 and a loop top address memory 2.
12, loop end address memory 213 and comparator 2
It is composed of 11. This reading means generates a waveform read address.

In FIG. 2, the CPU and the tone generator circuit are 1
They are connected to each other via a 6-bit data bus DB, a 24-bit address bus AB and a control data bus CNT. Latch 200 is a bidirectional tristate latch. The latch 200 is used to control transmission / reception of data between the CPU and the tone generator circuit. The tone generator circuit handles 32-bit wide data. Therefore, data transfer from the CPU to the tone generator circuit is performed twice with 16 bits each. The latch 200 sequentially takes in 16-bit data from the data bus DB and sends it to the internal bus 250 when 32 bits have been gathered. Conversely, 32-bit data is set in the latch 200 when transferring data from the tone generator circuit to the CPU. The data set in the latch 200 is output to the data bus DB 16 bits at a time. The latch timing and transfer direction of the latch 200 are controlled by the control signal CT from the timing generator 201.

The timing generator 201 has a clock signal CLK from a clock generator (not shown), address data sent from the CPU via the address bus AB, and control data sent from the CPU via the control data bus CNT. To generate various control signals for controlling each part of the tone generator circuit. Specifically, the timing generator 201 includes a control signal CT for controlling the latch 200 and a control signal SEL for controlling the selector 204.
And a timing signal T designating one time slot
Generate C. The timing signal TC is, for example, 3 when the sound source circuit operates in a time division of 32 sound generation channels.
Used to specify any one of the two time division time slots. The timing signal TC is supplied to various memories and the like described later.

The control flag latch 202 has a time division structure and stores data from the CPU. Clear signal CL output from a predetermined bit of the control flag latch 202
RA is supplied to the clear circuit 207. Further, the clear signal CLRB output from other bits is the clear circuit 10
5 (see FIG. 1). As will be described later, the clear circuit 207 is removed, and the clear circuit 1 described above is used.
The control signal latch 202 is not necessary in the tone signal generator having the configuration in which 05 is removed.

The current step memory 203 has a time division structure, and stores the F number from the CPU. F here
The number is data defining the pitch (frequency) of the musical sound to be generated. Specifically, when the waveform data of the waveform data group is sequentially read from the waveform memory 208,
It is used as the increment value of the waveform read address. The F number from the current step memory 203 is added to the adder 20.
6 is supplied to the A input terminal.

The selector 204 has three input ports (port 0, port 1 and port 2). Then, each input port is selected according to the control signal supplied to the control input terminals S0 and S1. 16 for port 1
Bit data is supplied. Therefore, when the port 1 is selected, the selector 204 outputs 32-bit data with the lower 16 bits set to zero. The table below shows the relationship between the control signals (S0, S1) and the selected input port.

[0051]

<Table 1> <S1> <S0> <Selected input port> 0 0 Port 2 (next waveform read address) 0 1 Port 1 (loop top address LT) 1-Port 0 (data sent from CPU)

The port 0 is used to select one waveform data group from a plurality of waveform data groups.
Each waveform data group corresponds to each timbre. The CPU sends control data for generating the control signal SEL to the timing generator 201. At the same time, the CPU sends the start address (start address SA) of the waveform data group corresponding to the desired tone color to the latch 200 via the data bus DB. As a result, port 0 is selected based on the control signal SEL, and the selector 204 outputs the start address SA of the waveform data group. As a result, the initial value of the waveform read address of the waveform data group is determined. Port 1 is used to return from the loop end address LE of the repeat part of the waveform data group to the loop top address LT. Port 2 is used for purposes other than the above, that is, for sequentially updating the waveform read address. The data selected by the selector 204 is the current address memory 2
It is supplied to 05.

The current address memory 205 has a time division structure, and stores the current waveform read address. The current waveform read address stored in the current address memory 205 indicates the storage position of the waveform data of the read waveform data group. This current address memory 20
The current waveform read address from 5 is supplied to the B input terminal of the adder 206 and the B input terminal of the comparator 210.

The adder 206 adds the F number from the current step memory 203 to the current waveform read address. The output of the adder 206 is the next waveform read address. The integer part of the next waveform read address indicates the storage position of the waveform data of the waveform data group read in the next cycle. The output of the adder 206 is the clear circuit 207.
Is supplied to.

The clear circuit 207 is used to set the lower predetermined bits of the next waveform read address from the adder 206 to zero. The clear circuit 207 is necessary when the lower predetermined bits of the waveform read address from the CPU include invalid data. Therefore, when 32-bit valid data is sent from the CPU, the clear circuit 207 can be removed. This clear circuit 20
The output of 7 is the waveform memory 208 (upper 16 bits), the A input terminal of the comparator 210 (upper 16 bits), the comparator 2
11 A input terminals (upper 16 bits) and port 2 (32 bits) of the selector 204 described above.

As described above, the waveform memory 208 stores a plurality of differential waveform data ΔWD _n in ADPCM format and specific waveform data W _j in PCM format. The contents of the waveform memory 208 are read according to the integer part of the next waveform read address from the clear circuit 207. That is, the specific waveform data W related to the integer part of the current waveform read address stored in the current address memory 205.
_In parallel with the generation of the tone signal based on _j or the difference waveform data ΔWD _n , the specific waveform data W _{j + 1} or the difference waveform data ΔWD _{n + 1} is read from the waveform memory 208. Specific waveform data W _{j + 1} from this waveform memory 208
Alternatively, the difference waveform data ΔWD _{n + 1} is supplied to the decoding circuit 209 in the next cycle. The sampling data YD _j or YD _n obtained by the generation or accumulation in the decoding circuit 209 is supplied to the input terminal A of the multiplier 217.

The comparator 210 compares the integer part of the current waveform read address from the current address memory 205 with the integer part of the next waveform read address from the clear circuit 207. If they match, the comparator 210 outputs "1". If they do not match, the comparator 210 outputs "0". The output of the comparator 210 is the gate 1 in the decoding circuit 209 as the coincidence signal CF.
02. The gate 102 has differential waveform data Δ
It is provided to prevent WD _n from being added to the sampling data YD _n in an overlapping manner. The possibility of overlapping addition occurs when the interval at which the waveform data of the waveform data group is read out to reproduce a low tone becomes short. In other words, it occurs when the value of the integer part does not change even if the waveform read address is incremented.

The loop top address memory 212 has a time division structure and stores a plurality of loop top addresses LT corresponding to a plurality of waveform data groups. Loop top address LT from this loop top address memory 212
Are supplied to the port 1 of the selector 204.

The loop end address memory 213 has a time division structure and stores a plurality of loop end addresses LE corresponding to a plurality of waveform data groups. The loop end address LE from this loop end address memory 213
Is supplied to the B input terminal of the comparator 211.

The comparator 211 detects the end of the repeat part by detecting the integer part (upper 16 parts) of the next waveform read address.
(Bit) and the loop end address LE from the loop end address memory 213 are constantly compared. Then, a signal indicating the comparison result is sent to the control input terminal S0 of the selector 204. As a result, when the integer part of the next waveform read address matches the loop end address LE, port 1 of the selector is selected. As a result, the loop top address LT and the value of zero (lower 16 bits) from the loop top address memory 212 are stored in the current address memory 205. On the other hand, when the integer part of the next waveform read address does not match the loop end address LE, port 2 of the selector 204 is selected. As a result, the next waveform read address is stored in the current address memory 205. By the above operation, the function of repeatedly reading the repeat part of the waveform data group is achieved.

The envelope parameter memory 214 has a time division structure and stores the current envelope target value, envelope addition value and loudness value. The contents of the envelope parameter memory 214 are read by the envelope generator 215. The current envelope memory 216 has a time division structure and stores a current envelope value which is an intermediate result of envelope calculation.

The tone signal generating means of the present invention comprises an envelope generator 215 and a multiplier 217.

The envelope generator 215 time-divisionally adds the envelope addition value from the envelope parameter memory 214 to the current envelope value from the current envelope memory 216. Then, the envelope generator 215 determines whether the calculation result has reached the envelope target value. If the calculation result has not arrived, the calculation result is stored as the current envelope value in the current envelope memory 216 and prepared for the next calculation. The calculation result is further multiplied by the loudness value. The multiplication result is the envelope level EL
Is output from the envelope generator 215. In this way, the envelope generator 215 generates an envelope that gradually approaches the envelope target value. The envelope level EL from the envelope generator 215 is supplied to the B input terminal of the multiplier 217.

The multiplier 217 multiplies the sampling data YD _j or YD _n from the decoding circuit 209 by the envelope level EL from the envelope generator 215. By this multiplication, a musical tone signal with an envelope added is generated. The tone signal from the multiplier 217 is supplied to the series adder 218.

The sequence adder 218 assigns all tone generation channels to at least one of the four tone color sequences and adds tone signals within each tone color sequence. This series adder 21
The output of 8 is supplied to the digital control filter 219.

As the digital control filter 219, for example, a digital filter which operates by 8 times oversampling can be used. The output of the digital control filter 219 is the D / A converter 2
20. The D / A converter 220 converts the oversampled digital signal into an analog signal for each tone color sequence described above. This analog signal is supplied to a speaker or an earphone through an amplifier (not shown).

As described above, according to the first embodiment, the specific waveform data W _j (PCM format “8000” is used).
(Stored in the waveform memory 208 as “H”) is read from the waveform memory 208, the sampling data YD _n−1 obtained by the accumulation up to that point is discarded, and the accumulation is restarted from the sampling data YD _j. It As a result, the accumulated error peculiar to the ADPCM or DPCM method can be removed. Further, it is possible to remove the accumulated error when the repeated reading is not performed.

When the musical tone waveform is sampled in a predetermined cycle, it is considered that the specific sampling data D _j (j = 0) does not exist at the sampling point P ₀ . In this case, the sampling start position may be slightly moved so that the sampling data D _j (j = 0) whose content is zero is obtained.

The waveform memory 208 can store a plurality of waveform data groups corresponding to a plurality of timbres. Each waveform data group is composed of specific waveform data W _j and a plurality of differential waveform data ΔWD _n, and the specific sampling data D _j related to the specific waveform data W _j of each waveform data group is the respective waveform data group. It is preferable that they are the same.

In the first embodiment, the specific waveform data W _j is the waveform memory 2 specified by j = M = 128.
It is stored at position 08. That is, the content of the waveform memory 208 designated by the loop top address LT is the specific waveform data W _j . Alternatively, the difference waveform data ΔWD _n-1 is obtained by subtracting D _N-2 from the sampling data D _M-1 (where 1 ≦ M ≦ N-3), and j is M <j <N−. 1 is satisfied, the reading means reads the differential waveform data ΔWD _N−1 and then reads the differential waveform data ΔWD _M again. In this case, the value of "M" is the loop top address and the value of "N" is the loop end address.

(Second Embodiment) In the second embodiment,
1 shows a preferred embodiment of the musical tone signal generator of the present invention.
The tone signal generator of the second embodiment generates tone signals while interpolating sampling data. Book second
In the embodiment, the differential waveform data Δ in the DPCM format
WD _n and specific waveform data W _{j in} DPCM format are used. The content of the specific sampling data D _j has a predetermined range of spread.

Specific waveform data W _j and differential waveform data Δ
As shown in FIG. 8A, WD _n is 16-bit data in 2's complement format having a sign in the most significant bit (bit 15). The specific waveform data W _j and the differential waveform data ΔWD _n are produced by the same method as already described with reference to FIG. In this case, if the content of the sampling data is within a predetermined spread range, for example, within a range of ± 256, the following processing is performed. That is, if such sampling data (specific sampling data D _j ) is a positive number, the lower byte remains as it is, and the portion (bits 8 to 14) of the upper byte excluding the sign bit is set to “1”. On the other hand, when such sampling data (specific sampling data D _j ) is a negative number, the lower byte remains as it is, and the portion (bits 8 to 14) of the upper byte excluding the sign bit is cleared to “0”. The data subjected to such processing is the specific waveform data W _j in the PCM format.

The difference waveform data ΔWD _n (DPCM format) and the specific waveform data W _j (PCM format) obtained in the same manner as in the first embodiment are located in the waveform memory 316 specified by an integer address described later. Stored in.

The waveform data group stored in the waveform memory 316 is handled as shown in FIG. 8B when generating or reproducing the sampling data YD _j or YD _n . That is, among positive numbers, “0000H to 7EFFH (+0000
H ~ + 7EFFH)) "is treated as difference waveform data ΔWD _n , but" 7F00H-7FFFH (+ 7F)
00H to + 7FFFH) "is treated as the specific waveform data W _j . The content of the specific waveform data W _j is “7F
00H to 7FFFH "is" 0 "as shown in FIGS. 8C and 8X in order to generate the sampling data YD _j .
000H to 00FFH (+ 0000H to + 00FF
H) ”is converted into PCM data. Similarly, among negative numbers, "FFFFH to 8100H (-0001 to -7F00)
H) ”is treated as difference waveform data ΔWD _n , but“ 80FFH to 8000H (−7F01H to −80).
00H) ”is treated as the specific waveform data W _j .
The content of this specific waveform data W _j is “80FFH-8
000H ”is used to generate sampling data YD _j , as shown in FIGS. 8 (C) and 8 (Y).
FF00H (-0001H to -0100H) "PCM
Converted to data. In the parentheses, the signed absolute value is represented in hexadecimal.

(1) Description of Decoding Circuit FIG. 6 is a block diagram showing a decoding circuit 317 (see FIG. 7) applied to the tone generator circuit of the tone signal generating apparatus of the present invention. The decoding circuit 317 corresponds to the decoding means including the interpolation means and the temporary storage means. In FIG. 6, the same or corresponding parts as those of the decoding circuit shown in FIG. 1 are designated by the same reference numerals.

In FIG. 6, delay latches 120, 1
22, 123 and 124 are provided for pipeline control. These delay latches latch input data in synchronization with the channel clock CCK. The channel clock CCK is, for example, as shown in FIG. 11, a clock that defines a time slot corresponding to each sounding channel. The tone generation channel is switched at the falling edge of the channel clock CCK. The sample clock SCK is the channel clock C
CK is a clock that generates a falling edge every time a time slot corresponding to all sound generation channels is counted. Processing of each sampling data is performed in synchronization with the sample clock SCK.

The delay latch 120 includes the waveform memory 31.
The waveform data of the waveform data group from 6 is stored in synchronization with the channel clock CCK. The waveform memory 316 corresponds to the waveform storage means. The waveform data of the waveform data group from the delay latch 120 is supplied to the B input terminal of the comparator 100, the data converter 121, and the A input terminal of the adder 103.

The range value Z13 stored in the ROM or register (not shown) is supplied to the comparator 100. The comparator 100 compares the content of the waveform data of the waveform data group with the range value Z13. The range value Z13 has the same range spread as the content of the specific waveform data W _j . That is,
Range value Z13 is 7F00H to 7FFFH and 80FFH
~ 8000H.

When the waveform data whose contents are within the range of the range value Z13 is input to the comparator 100, the comparator 100
Detects the specific waveform data W _j and outputs the control signal C of "1".
Output MP. When the waveform data whose content is outside the range of the range value Z13 is input to the comparator 100, the comparator 1
00 detects the difference waveform data ΔWD _n and outputs the control signal CMP of “0”. The control signal CMP is supplied to the input terminal S of the selector 104.

The data converter 121 includes the delay latch 1
The waveform data of the waveform data group from 20 is converted by the method shown in FIG. That is, when the waveform data of the waveform data group is a positive number, the lower byte remains unchanged and the upper byte is set to "00H". In the case of a negative number, the lower byte remains and the upper byte is set to "FFH".
As a result, the specific waveform data W _j is restored to PCM data (content of the specific waveform data W _j having a value within the range of ± 256) that is the same as or close to the specific sampling data D _j . The output of the data converter 121 is the selector 10
4 is supplied to the A input terminal. Difference waveform data ΔWD _n
Is transformed into data with strange content. However, such converted data is discarded at selector 104.

The expansion circuit 101 is an option. That is, in the second embodiment, since the differential waveform data ΔWD _n stored in the waveform memory 316 is in the DPCM format, the decompression circuit 101 is unnecessary. Waveform memory 31
When the differential waveform data ΔWD _n in ADPCM format is stored in 6, the decompression circuit 101 may be inserted at the position shown in FIG. The expansion circuit 101 according to the second embodiment
Can use the same thing as what was used in 1st Embodiment.

The first current sample memory 106 and the second current sample memory 128 have a time division structure, and correspond to the temporary storage means of the present invention. The first current sample memory 106 stores the sampling data YD _n-1 accumulated so far.

The sampling data YD _n-1 is supplied to the clear circuit 126. The clear circuit 126 outputs zero when a clear signal CLRB from a tone generator circuit described later is activated. Otherwise, clear circuit 1
26 passes the sampling data YD _n-1 as it is. The output (zero or sampling data YD _n-1 ) of the clear circuit 126 is supplied to the second current sample memory 128 and the B input terminal of the adder 103. The clear signal CLRB is activated when the reading of the waveform data of the waveform data group is started, that is, when the key-on event occurs, whereby the contents of the second current sample memory 128 are cleared to zero.

The second current sample memory 128 is
The sampling data YD _n-1 from the first current sample memory 106 is stored. Writing to the second current sample memory 128 is performed by the channel clock CCK except when a specific condition (described later) is satisfied.
It is done in synchronization with. Therefore, the content (YD _n-1 ) of the first current sample memory 106 is delayed by one channel clock and stored in the second current sample memory 128. The sampling data YD _n-1 from the second current sample memory 128 is supplied to the B input terminal of the subtractor 129 and the A input terminal of the adder 131.

The adder 103 receives the specific waveform data W _j or the differential waveform data ΔWD _n from the delay latch 120 as
Clear circuit 1 from the first current sample memory 106
Sampling data YD _n-1 sent via 26
Add to. The output of the adder 103 is the sampling data YD _n . The adder 103 realizes the function of accumulating the difference waveform data ΔWD _n . The sampling data obtained from the adder 103 is supplied to the B input terminal of the selector 104.

The selector 104 selects either the converted data from the data converter 121 or the sampling data YD _n from the adder 103 according to the control signal CMP from the comparator 100. More specifically, if the control signal CMP is "1", the A input terminal side of the selector 104 is selected. As a result, the data converter 12
The converted data from 1 is the sampling data YD _j
Is output as the first current sample memory 106
Is supplied to. On the other hand, if the control signal CMP is "0", the B input terminal side of the selector 104 is selected. As a result, the data from the adder 103, that is, the obtained sampling data YD _n is output and supplied to the first current sample memory 106.

This first current sample memory 106
The writing to is performed in synchronization with the channel clock CCK except when a specific condition (described later) is satisfied. The sampling data YD _n from the first current sample memory 106 is supplied to the clear circuit 126 and the subtractor 129.

Writing to the first and second current sample memories 106 and 128 is performed by the delay latch 1
This is done by the write signal created by 24 and the AND gate 125. The delay latch 124 is composed of a D-type flip-flop having an inverted output. The delay latch 124 latches the coincidence signal CF in synchronization with the channel clock CCK, and supplies the signal from its inverting output terminal to the AND gate 125. Therefore, if the coincidence signal CF is “0”, the channel clock CCK is supplied to the first and second current sample memories 106 and 128 via the AND gate 125. As a result, the first current sample memory 106
The sampling data YD _n-1 stored in the second current sample memory 128 is written in the second current sample memory 128, and
The output (YD _n or YD _j ) of the selector 104 is written in the first current sample memory 106. On the other hand, if the coincidence signal CF is "1", the channel clock CCK is masked by the AND gate 125, and writing to the first and second current sample memories 106 and 128 is not performed.

The coincidence signal CF is generated in the tone generator circuit described later. The coincidence signal CF is set to "1" when the waveform read address having the same value in the integer part is successively output twice or more, and is cleared to "0" otherwise. Therefore, when the coincidence signal CF is set to "1", writing to the first and second current sample memories 106 and 128 is prohibited in the time slot after one channel clock.

The interpolation means of the present invention comprises a subtractor 129, a multiplier 130 and an adder 131. These are used to calculate an interpolated value between the sampling data YD _{j + 1} and YD _j or between the sampling data YD _{n + 1} and YD _n . The subtractor 129 stores the contents (YD _{j + 1} or YD _{n + 1} ) of the first current sample memory 106.
To the contents of the second current sample memory 128 (YD
_j or YD _n ) is subtracted. Thereby, the difference value between the two sampling data is calculated. This subtractor 12
The output of 9 is supplied to the B input terminal of the multiplier 130.

The A input terminal of the multiplier 130 is supplied with a decimal address (details will be described later) delayed by two channel clocks by the delay latches 122 and 123. The multiplier 130 multiplies this decimal address by the difference value from the subtractor 129. The output of the multiplier 130 constitutes an interpolated value and is supplied to the B input terminal of the adder 131. Second
The sampling data YD _n or YD _j from the current sample memory 128 is supplied to the A input terminal of the adder 131. Therefore, the addition data is added by the adder 131 to generate the interpolated sampling data YD. The output (YD) of the adder 131 is supplied to the clear circuit 132.

The clear circuit 132 outputs zero when the clear signal CLRB from the control flag latch 302 of the tone generator circuit described later is activated, and otherwise outputs the adder 131 (interpolated sampling data Y
Pass D) as is. The output of the clear circuit 132 is used as the interpolated sampling data YD to generate a tone signal, so that the multiplier 3 of the tone generator circuit described later is used.
26. As described above, the clear signal CLRB is activated when the reading of the differential waveform data ΔWD _n or the specific waveform data W _j is started, that is, when the key-on event occurs, and the output of the indeterminate interpolated sampling data is output. Is prevented.

As described above, since the present decoding circuit internally stores the sampling data YD _n , it is not necessary to always read the sampling data at two sampling points, unlike the conventional case. That is, interpolation can be performed only by reading the waveform data of one waveform data group from the waveform memory 316. Therefore, the circuit configuration becomes simple. Further, for example, the time of the time slot corresponding to one sounding channel can be shortened, so that a tone signal generating apparatus capable of higher speed processing can be achieved.

(2) Description of Sound Source Circuit FIG. 7 is a block diagram of a second embodiment of the sound source circuit applied to the musical tone signal generator. In this sound source circuit,
The decoding circuit 317 described above is applied. Below, FIG.
The configuration and operation of the tone generator circuit will be described in detail with reference to the block diagram shown in FIG.

The reading means of the present invention is an F number generating means,
F number accumulating means, bank memory 311, OR gate 3
12, adder 313, comparator 314 and selector 315
It consists of. The F number generating means is composed of a current step memory 303 and a clear circuit 306. The F number accumulation means is composed of a selector 304, a current address memory 305, an adder 307, a loop top address memory 308, a loop end address memory 309, and a comparator 310.

First, the format of the waveform read address for reading the waveform data of the waveform data group from the waveform memory 316 will be described with reference to FIG. The waveform read address is composed of 32-bit data as shown in FIG. The waveform read address has an integer part and a decimal part. Lower 16 bits (A
15-A0) is used as a decimal address (decimal part) and is also used as an interpolation address. In the second embodiment, 4 bits (A15-A12) are used as the interpolation address, but any value in the range of 1 to 16 bits can be used as required.

High-order 16 of the waveform read address related to the integer part
Bits (A31 to A16) and bank address (B7-
B0) forms an address that actually specifies the position of the waveform memory 316. The waveform memory 316 is composed of 256 banks each of which is 64 Kbytes. Bank address is 1 out of 256 banks
Used to select one bank. The integer address is used to specify the position of one differential waveform data ΔWD _n or specific waveform data W _j in the bank.

The loop top address LT is composed of 16-bit data. This loop top address L
T corresponds to the integer part of the waveform read address. The loop end address LE is composed of 16-bit data. This loop end address LE corresponds to the integer part of the waveform read address. Loop top address LT
Is used to specify the start position of the repeat part of the waveform data group. The loop end address LE is used to specify the end position of the repeat part of the waveform data group.

In FIG. 7, the CPU and the tone generator circuit are 16
Bit data bus DB, 24-bit address bus A
B and the control data bus CNT are connected to each other. Latch 300 is a bidirectional tristate latch. The latch 300 is used to control transmission / reception of data between the CPU and the sound source circuit. The latch 300 takes in 16-bit data from the data bus DB and outputs it to the internal bus 350. Further, the latch 300 takes in 16-bit data from the internal bus 350 and outputs it to the CPU. Latch 300
The latch timing and transfer direction of the
The control is performed based on the control signal CT sent from 01.

The timing generator 301, like the timing generator 201 in the first embodiment, generates various control signals for controlling each part of the tone generator circuit. More specifically, the timing generator 301 includes a latch 300
Control signal CT for controlling the
A control signal SEL for controlling 4 and a timing signal TC for designating one sounding channel are generated. Each of these signals has the same property as in the case of the first embodiment.

The control flag latch 302 has a time-division structure and stores data sent from the CPU. The clear signal CLRA output from a predetermined bit of the control flag latch 202 is supplied to the clear circuit 306. Further, the clear signal CLRB output from the other bits is supplied to the clear circuits 126 and 132 (see FIG. 6).

The current step memory 303 has a time division structure and stores an F number. The current step memory 303 corresponds to the F number generating means of the present invention. The CPU generates an F number according to the key depression information. The F number to be stored in the current step memory 303 is obtained from the CPU. The F number from the current step memory 303 is supplied to the clear circuit 306.

The clear circuit 306 controls the control flag latch 3
When the clear signal CLRA from 02 is activated, zero is output, otherwise, the F number from the current step memory 303 is passed through as it is. The output of the clear circuit 306 is supplied to the A input terminal of the adder 307. By the way, the clear signal CLRA is usually controlled to be active only during the first one time slot when the reading of the waveform data of the waveform data group from the waveform memory 316 is started (see FIG. 9). Therefore, in the initial state, zero is supplied to the A input terminal of the adder 307. Therefore, the adder 307 outputs the content of the current address memory 305 as it is. As a result, in the initial state, the reading of the waveform data of the waveform data group is started from the specific waveform read address.

The selector 204 has four input ports (port 0, port 1, port 2 and port 3). These input ports are connected to control input terminals S0 and S1.
Is selected according to the control signal supplied to. Port 1
3 is supplied with only 16-bit data. Therefore, when any one of these is selected, the lower 16
32 created by replacing bits with "0"
Bit data is output. 32 on port 0
Since the bit data is supplied, when the port 0 is selected, the input 32-bit data is output as it is. The relationship between the control signals (S0, S1) and the selected input port is shown in the table below.

[0105]

[Table 2] <S1> <S0> <Selected input port> 0 0 Port 0 (Next waveform read address) 0 1 Port 1 (Loop top address LT) 1 0 Port 2 (Data sent from CPU) 1 1 Port 3 (data sent from CPU)

The ports 2 and 3 are used to select one waveform data group from a plurality of waveform data groups. That is, the CPU sends the control data for generating the control signal SEL to the timing generator 301, and at the same time, sets the start address (integer part of the start address SA) of the waveform data group corresponding to the desired tone color in the data bus DB
To the latch 300 via. As a result, the control signal S
Port 0 is selected based on EL, and the selector 304 outputs the waveform read address. Port 1 is used to return from the loop end address LE of the repeat part of the waveform data group to the loop top address LT. When this port 1 is selected, the selector 304 outputs a 32-bit loop top address LT (integer address + decimal address (0)). The port 0 is used for purposes other than the above, that is, for reading the waveform data of the waveform data group while sequentially updating the waveform read address. When this port 0 is selected, the selector 304 outputs a 32-bit next waveform read address (integer address + fractional address). The data selected by the selector 304 is supplied to the current address memory 305.

The current address memory 305 has a time division structure and stores the current waveform read address. The current waveform read address from the current address memory 305 is
It is supplied to the B input terminal of the adder 307.

The adder 307 adds the F number from the clear circuit 306 to the current waveform read address. The result of this addition is used as the next waveform read address. The output of the adder 307 is the port 0 (A31
To A0), the OR gate 312 (A15-A12), the B input terminal (A31-A16) of the adder 313, and the delay latch 122 (A15-A12) of the decoding circuit 317.

The interpolation address (A15-12) of the waveform read address from the adder 307 is supplied to the OR gate 312. The OR gate 312 performs a logical sum operation. Therefore, if the interpolation address is not zero, OR gate 3
“1” is output from 12 and supplied to the A input terminal of the adder 313.

The adder 313 adds the output of the OR gate 312 to the integer address (A31-A16). By the OR gate 312 and the adder 313, when the interpolation address is not zero, an integer address (A31-
The function of incrementing (A + 1) (“+1”) has been achieved. As a result, the next waveform read address for interpolation can be obtained. The output of the adder 313 is the comparator 3
It is supplied to the A input terminal of 14 and the B input terminal of the selector 315.

As will be described later, the loop end address memory 3
The loop end address LE from 09 is output to the comparator 314.
Is supplied to the B input terminal of. Therefore, this comparator 314
Then, the integer part of the next waveform read address is compared with the loop end address LE. As a result of this comparison, if the two match, "1" is output, and if not, "0"
Is output. The output of the comparator 314 is supplied to the input terminal S of the selector 315 as a control signal.

The selector 315 responds to the control signal from the comparator 314 and outputs a loop top address LT (T31-T1) from a loop top address memory 308, which will be described later.
6) or the integer part of the next waveform read address from the adder 313 is selected. “1” is the selector 315
When it is supplied to the input terminal S of, the A input terminal of the selector 315 is selected in order to output the loop top address LT. On the other hand, when "0" is supplied to the input terminal S of the selector 315, the B input terminal of the selector 315 is selected to output the integer part of the next waveform read address. The output of the selector 315 is supplied to the waveform memory 316 as the waveform read address (A31-A16), and at the same time, the delay latch 318 and the A of the comparator 319 are used.
It is supplied to the input terminal. With this configuration, the function of returning to the loop top address LT when the integer part of the next waveform read address matches the loop end address LE is achieved.

The delay latch 318 has a time division structure and latches the bank address and the integer part of the next waveform read address from the selector 315 in synchronization with the channel clock CCK. The delay latch 318 is used to store the bank address and the integer part of the next waveform read address until one channel clock later. The output of the delay latch 318 is supplied to the B input terminal of the comparator 319.

The comparator 319 compares the output of the selector 315 with the output of the delay latch 318. If the two match, it is "1", and if not, "0"
Is output. The output of the comparator 319 is the clear circuit 3
20.

The clear circuit 320 uses the control flag latch 3
It outputs zero when the clear signal CLRB from 02 is activated. If not, the output of the comparator 319 is passed as it is. The output of the clear circuit 320 is supplied to the delay latch 124 of the decoding circuit 317 as the coincidence signal CF. This clear signal CLRB is
When the reading of the waveform data of the waveform data group is started, it is controlled to be active only during the first two time slots (see FIG. 9). Therefore, the coincidence signal CF is forced to "0" during the first two time slots.
This avoids malfunction of the tone generator circuit.

The waveform memory 316 corresponds to the waveform storage means of the present invention. As described above, the waveform memory 316 stores the difference waveform data ΔWD _n or PCM in the DPCM format.
The format specific waveform data W _j is stored. The contents of the waveform memory 316 are read according to the integer part of the waveform read address from the selector 315 and the bank address from the bank memory 311 described later. This waveform memory 20
The waveform data of the waveform data group read from No. 8 is supplied to the decoding circuit 317.

The sampling data YD from the decoding circuit 317 is supplied to the A input terminal of the multiplier 326.

The loop top address memory 308 has a time division structure and stores each loop top address LT of a plurality of waveform data groups. Here, each of the plurality of waveform data groups corresponds to each timbre.
The loop top address LT from the loop top address memory 308 is stored in the current address memory 305 via the port 1 of the selector 304.

The loop end address memory 309 has a time division structure and stores each loop end address LE of a plurality of waveform data groups. The loop end address LE from this loop end address memory 309 is
It is supplied to the B input terminal of the comparator 314. Then, the loop end address LE is constantly compared with the data output from the adder 313.

Further, the loop end address memory 309
The loop end address LE from is supplied to the B input terminal of the comparator 310. The comparator 310 compares the integer part of the next waveform read address from the adder 307 and the loop end address LE from the loop end address memory 309. If the two match, "1" is output, and if not, "0" is output. The output of the comparator 310 is supplied to the control input terminal S0 of the selector 304. As a result, when the integer part of the next waveform read address matches the loop end address LE, port 1 of the selector is selected and a total of 32 bits of the loop top address LT (upper 16 bits) and zero (lower 16 bits). It is stored in the current address memory 305. Otherwise, port 0 is selected and the next waveform read address is stored in the current address memory 305. As a result, the function of repeatedly reading the repeat portion of the waveform data group in the waveform memory 316 is achieved.

The bank memory 311 has a time division structure,
The bank address for selecting one bank of the waveform memory 316 is stored. The bank address from the bank memory 311 is supplied to the waveform memory 316.

The configurations, operations, and functions of the envelope parameter memory 321 and the envelope generator 323 are the same as those of the envelope parameter memory 214 and the envelope generator 215 described in the first embodiment, and therefore the description thereof will be omitted. The envelope level EL from the envelope generator 323 is supplied to the delay latch 324.
Is supplied to.

The tone signal generating means of the present invention comprises an envelope generator 323, delay latches 324 and 325, and a multiplier 326.

The delay latch 324 stores the envelope level EL from the envelope generator 323 in synchronization with the channel clock CCK. The envelope level EL delayed by one channel clock from the delay latch 324 is supplied to the delay latch 325. The delay latch 325 is the delay latch 3
Channel level C from the envelope level from 24
Store in synchronization with CK. The envelope level delayed by two channel clocks from the delay latch 325 is supplied to the B input terminal of the multiplier 326. By the pipeline control achieved by these delay latches 324 and 325, sampling data YD obtained by delaying by two channel clocks,
The phase of the envelope data to be added to the sampling data YD is adjusted.

The multiplier 326 multiplies the sampling data YD from the decoding circuit 317 and the data obtained by delaying the envelope level from the envelope generator 323 by 2 channel clocks. By this multiplication, a musical tone signal with an envelope added is generated. The output of the multiplier 326 is supplied to the series adder 327. The series adder 327, the digital control filter 328, and the D / A converter 329 have the same configurations as the series adder 218, the digital control filter 219, and the D / A converter 220 of the above-described first embodiment, respectively.
Their operations are also the same.

Next, in order to deepen the understanding of the second embodiment, the operation of the second embodiment will be described with reference to FIG. FIG. 9 shows how the waveform data of the waveform data group stored in the waveform memory 316 is interpolated and the sampling data YD is output. The lower part of the figure shows the state of data change at the main points of the decoding circuit 317. In addition, for simplification of description, the state of change is indicated by a decimal number.

In FIG. 9, points indicated by white circles are the difference waveform data ΔWD stored in the waveform memory 316.
_{The number} that indicates _n and is surrounded by the "<>" symbols is the range value Z13.
Indicates. FIG. 9 shows that the waveform data of the waveform data group is stored at addresses 0 to 10. That is, D (j
= 0), ΔWD ₁ , ΔWD ₂ , ... Corresponding to the waveform data of the waveform data group, “0” is assigned to address 0, “+200” is assigned to address 1, “+100” is assigned to address 2, and so on. Sequentially stored.

Furthermore, the dotted line in FIG. 9 shows the transition of the sampling data YD. The black circle on the dotted line is the sampling data interpolated by the decimal address, that is,
The sampling data YD obtained by the interpolation in the decoding circuit 317 is shown. FIG. 9 shows the F number =
The case of 0.75 is shown. Therefore, the integer addresses C31-C16 of the waveform read address are "0 → 1 → 2 → 3.
→ 3 → 4 → 5 → 6 → ... ”, and the decimal address FA
Since F is delayed by the two-stage delay latches 122 and 123, “indefinite → indefinite → 0 → 0.75 → 0.50
(Accumulated F number 0.75 + 0.75 = 1.50 fractional part) → 0.25 (accumulated F number 1.50+
0.75 = 2.25 fractional part) → ... ". The waveform data of the waveform data group read from the waveform memory 316 is delayed by one cycle by the delay latch 120 of one stage (indicated by ZD in FIG. 9).

The coincidence signal CF is created in the tone generator circuit,
It is controlled to be "1" when the same waveform read address is output twice or more. This coincidence signal CF is
The delay latch 124 delays by one channel clock. The control signal CMP indicating the comparison result is a signal output from the comparator 100 of the decoding circuit 317. When the control signal CMP is “1”, the output of the data converter 121 is selected by the selector 104 and supplied to the current sample memory 106.

In the waveform data of the waveform data group and the waveform data (ZD) of the delayed waveform data group, the data indicated by the symbol "<>" is the PCM format specific waveform stored in the waveform memory 316. This is the data W _j . The other data is the DPC stored in the waveform memory 316.
It is the difference waveform data ΔWD _n in the M format. By adopting the pipeline control method, there is a delay of two channel clocks from the output of the integer part of the waveform read address to the waveform memory 316 until the result (interpolated sampling data YD) is obtained.

As described above, according to the second embodiment, when the specific waveform data W _j is read from the waveform memory 316, the first current sample memory 106 and the second current sample memory 128 are stored until then. The sampling data accumulated in 1 is discarded, and the accumulation is restarted with the specific waveform data as the initial value. Therefore, ADPC
It is possible to eliminate the accumulated error peculiar to the M or DPCM method. In addition, it is possible to suppress an accumulated error when not repeatedly reading.

Further, according to the second embodiment, even when the musical tone waveform is simply sampled at a predetermined cycle, the sampling data D within the predetermined spread range is obtained.
_It suffices if _j is provided. Therefore, there is an advantage that the waveform data group can be easily created.

Further, the interpolated sampling data YD
Is output, the tone signal generator can finely adjust the pitch. Furthermore, unlike the prior art, it is not always necessary to read the sampling data at two sampling points. That is, since the next waveform read address of the waveform data group is read out only when the value of the integral part of the accumulated F number (waveform read address) changes, the time of the time slot corresponding to one sound generation channel is shortened. it can. As a result, according to the tone signal generator of the second embodiment, higher speed processing can be achieved.

[0134]

As described above, according to the musical tone signal generator of the present invention, the waveform data of the waveform data can be reproduced when the musical tone signal is reproduced by the ADPCM system or the DPCM system, though the circuit configuration is simple. It is possible to provide a musical tone signal generation device capable of suppressing the occurrence of cumulative error due to repeated reading, and also suppressing the cumulative error when not being repeatedly read.

[Brief description of drawings]

FIG. 1 is a block diagram of a decoding circuit applied to a tone generator circuit according to a first embodiment of a tone signal generating apparatus of the present invention.

FIG. 2 is a block diagram of a tone generator circuit of the first embodiment of the musical tone signal generator of the invention.

FIG. 3 is a diagram illustrating data used in the first embodiment of the musical tone signal generating apparatus of the present invention.

FIG. 4 is a diagram for explaining a method of creating waveform data used in the first embodiment of the musical tone signal generator of the invention.

FIG. 5 is a diagram showing an example of storage of waveform data in a waveform memory in the first embodiment of the tone signal generating apparatus of the invention.

FIG. 6 is a block diagram of a decoding circuit applied to a tone generator circuit according to a second embodiment of a musical tone signal generator of the invention.

FIG. 7 is a block diagram of a tone generator circuit of a second embodiment of the musical tone signal generator of the invention.

FIG. 8 is a diagram for explaining data used in the second embodiment of the musical tone signal generator of the invention.

FIG. 9 is a diagram for explaining an example of storing waveform data in a waveform memory and a decoding operation in a second embodiment of the musical tone signal generating apparatus of the present invention.

FIG. 10 is a diagram for explaining waveform read addresses used in the second embodiment of the musical tone signal generator of the invention.

FIG. 11 is a timing chart showing the operation timing of the decoding circuit in the second embodiment of the musical tone signal generating apparatus of the present invention.

FIG. 12 is a diagram showing an example of storing waveform data in a waveform memory in the embodiment of the musical tone signal generating apparatus of the present invention.

[Explanation of symbols]

100, 210, 211, 310, 314, 319
Comparator 101 Expanding circuit 102 Gate circuit 103, 131, 206, 307, 313 Adder 104, 204, 304, 315 Selector 105, 126, 132, 207, 320 Clear circuit 106, 128 Current sample memory 120, 122, 123, 124, 318, 324, 3
25 Delay Latch 121 Data Converter 125 AND Gate 129 Subtractor 130, 217, 326 Multiplier 200, 300 Latch 201, 301 Timing Generator 202, 302 Control Flag Latch 203, 303 Current Step Memory 205, 305 Current Address Memory 208, 316 Waveform memory 209, 317 Decoding circuit 212, 308 Loop top address memory 213, 309 Loop end address memory 214, 321 Envelope parameter memory 215, 323 Envelope generator 216, 322 Current envelope memory 218, 327 Series adder 219, 328 Digital control Filter 220, 329 D / A converter 311 Bank memory 312 OR gate

Claims (6)

[Claims] (A) Selected from sampling data D _i obtained by sampling a tone waveform at a sampling point P _i (where i = 0, 1, 2, ..., N-1). Specific sampling data D _j (where 0 ≦ j ≦ N
Specific waveform data W _j created based on −1) and sampling data D _n (where n = 1, 2, ... N−
1 and the sampling data D _n-1 from n ≠ j)
Waveform storage means for storing the differential waveform data ΔWD _n obtained by subtracting (b) reading means for sequentially reading the specific waveform data W _j or the differential waveform data ΔWD _n from the waveform storage means; and C) a temporary storage means, (D) said read is detecting means to generate the sampling data YD _j when reading the specified waveform data W _j, stored in the temporary storage means the sampling data YD _j, it is said read out means difference Decoding means for accumulating the difference waveform data ΔWD _n in the temporary storage means when the waveform data ΔWD _n is read, and thereby generating sampling data YD _n , and (E) the obtained sampling data YD _j or YD _n
And a musical tone signal generating means for generating a musical tone signal based on the above. 2. The reading means accumulates an F number generating means for generating an F number for designating a pitch and an F number from the F number generating means in a predetermined cycle, and thus an integer part is obtained. And an F number accumulating means for generating a waveform read address consisting of a decimal part and the read means, when the integer part of the waveform read address is j, the specific waveform data W _j , and the integer of the waveform read address. When the part is n, the difference waveform data ΔWD _n is read from the waveform storage means, the decoding means includes an interpolation means, and the interpolation means is between the sampling data YD _{n + 1} and YD _n or the sampling data YD _n. Interpolation is performed between _{j + 1} and YD _j according to the value of the decimal part of the waveform read address to obtain interpolation data, and the tone signal generating means further generates a tone signal based on the interpolation data YD. Characterized by The musical tone signal generator according to claim 1. 3. The differential waveform data ΔWD _N-1 is obtained by subtracting D _N-2 from sampling data D _M-1 (where 1 ≦ M ≦ N-3), where j is M. <J <N-
The musical tone signal generating apparatus according to claim 1, wherein the reading means reads the differential waveform data ΔWD _N-1 and then reads the differential waveform data ΔWD _M again. 4. The specific waveform data W _j is stored at a position in the waveform storage means designated by j = M, and the reading means reads the differential waveform data ΔWD _N-1 and then specifies again. The musical tone signal generating apparatus according to claim 1, wherein the waveform data W _j (where j = M) is read out. 5. The musical tone signal generator according to claim 1, wherein the content of the specific sampling data D _j is zero. 6. The musical tone signal generating apparatus according to claim 1, wherein the content of the specific sampling data D _j is within a predetermined spread range.