JP2008046175A - Waveform generator and waveform generation processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a waveform generator for generating a musical sound waveform exceeding the upper limit of a reproduction pitch decided by a control of a waveform address stepping value. <P>SOLUTION: A pitch control flag F is provided in each of channel areas CH 0-CH 63 of a RAM 10 corresponding to sounding channels CH 0-CH 63. When there is the sounding channel having the pitch control flag F representing the excess of the upper limit of the reproduction pitch, a leading channel slot and a following channel slot assigned to the sounding channel are regarded as one channel slot. In the leading channel slot, the first output waveform is generated by a difference waveform reproduction based on a maximum address stepping value, and the first output waveform is added to the second output waveform obtained by the difference waveform reproduction based on the remaining address stepping value after subtracting the maximum address stepping value so as to generate the musical sound waveform, in the following channel slot. As a result, the musical sound waveform exceeding the upper limit of the reproduction pitch can be generated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a waveform generation device and a waveform generation processing program suitable for use as a sound source of an electronic musical instrument.

  2. Description of the Related Art Conventionally, a waveform generator that reads differential waveform data that has been subjected to differential PCM encoding from a memory and generates a musical sound waveform is known. As this type of device, for example, in Patent Document 1, the step amount of the waveform address for reading the differential waveform data stored in the memory is larger than “1”, and the waveform address integer part updated thereby is the pre-update waveform portion. When the waveform address integer part becomes discontinuous, based on the waveform address decimal part while sequentially integrating the corresponding differential waveform data from the waveform address integer part before update to the updated waveform address integer part A technique is disclosed in which a musical sound waveform is generated at a reproduction pitch equal to or higher than the original sound pitch by performing an interpolation calculation.

Japanese Patent No. 3223560

  By the way, in the recent multi-timbral sound source, the period of the processing slot assigned to one tone generation channel is short due to the increase in the number of polyphonics. If such a sound source is equipped with a waveform generator that generates a musical sound waveform based on a differential waveform, the number of times of reading differential waveform data from the waveform memory is necessarily limited. The limitation on the number of waveform readouts causes a limitation on the waveform address step value, which causes a problem that the reproduction pitch is limited to a predetermined upper limit value (maximum address step value).

  The present invention has been made in view of such circumstances, and provides a waveform generation device and a waveform generation processing program capable of generating a musical sound waveform exceeding the upper limit of the reproduction pitch determined by the limitation of the waveform address step value. The purpose is to do.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a waveform generator for reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform. Determining means for determining whether or not the sound generation pitch is assigned to a sound generation channel that exceeds the upper limit of the playback pitch by the determination means. Slot designating means for designating the preceding channel slot corresponding to the following channel slot, and the preceding channel slot designated by the slot designating means, the sounding pitch is set to the maximum address step value which is the upper limit of the reproduction pitch. Limit and regenerate differential waveform based on the limited maximum address step value In the first waveform generating means for generating the first waveform output at the time point and the subsequent channel slot designated by the slot designating means, based on the remaining address step value obtained by subtracting the maximum address step value from the tone generation pitch. And a second waveform generating means for adding a first waveform output generated by the first waveform generating means to a second waveform output obtained by differential waveform reproduction to form a musical sound waveform. And

  According to a second aspect of the present invention, in a waveform generator for reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform, a sound generation pitch exceeding the upper limit of the reproduction pitch is assigned. A discriminating means for discriminating whether or not the sound channel is a sound channel, and until the sound producing pitch falls within the upper limit of the playback pitch when the discriminating means determines that the sound channel is assigned a sound generation pitch exceeding the upper limit of the playback pitch. Slot assigning means for assigning a plurality of channel slots required for decreasing the maximum address increment value to the tone generation channel, and the maximum address increment value among the plurality of channel slots assigned by the slot assigning means. Channel slots are based on their limited maximum address step value. In a channel slot that generates waveform output during differential waveform playback and is assigned a residual address step value less than or equal to the maximum address step value, the waveform output obtained by differential waveform playback based on the residual address step value is displayed. And waveform generating means for accumulating the waveform outputs generated in the channel slots to form a musical sound waveform.

  According to a third aspect of the present invention, in a waveform generator for reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform, a sound generation pitch exceeding the upper limit of the reproduction pitch is assigned. And a first channel corresponding to the sounding channel when the sounding channel is determined to be assigned a sounding pitch exceeding the upper limit of the reproduction pitch. A slot designating unit for designating a slot and a second channel slot for continuing the differential waveform reproduction performed in the first channel slot, and a sounding pitch is reproduced in the first channel slot designated by the slot designating unit. Limit to the maximum address step value that is the upper limit of the pitch, and limit the maximum address In the first waveform generation means for generating the first waveform output by the differential waveform reproduction based on the scan step value, and the second channel slot designated by the slot designation means, the maximum address step value is calculated from the tone pitch. A second waveform output obtained by differential waveform reproduction based on the subtracted remaining address step value is added to the first waveform output generated by the first waveform generating means to form a musical tone waveform. And a waveform generating means.

  According to a fourth aspect of the present invention, there is provided a program that is executed by a waveform generating apparatus that reproduces a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform, and is an upper limit of a reproduction pitch. A determination process for determining whether or not the sound generation channel is assigned a sound generation pitch exceeding the sound generation pitch, and when the sound generation channel is determined to be assigned a sound generation pitch exceeding the upper limit of the playback pitch by the determination processing, the sound generation channel In the slot designation process for designating the preceding channel slot corresponding to the following channel slot and the subsequent channel slot, and the preceding channel slot designated by the slot designation process, the tone generation pitch is set to the maximum address step value which is the upper limit of the reproduction pitch. Limit waveform playback based on the limited maximum address step value And a difference based on the remaining address step value obtained by subtracting the maximum address step value from the tone generation pitch in the first channel generation process for generating the first waveform output and the subsequent channel slot specified by the slot specifying process. And a second waveform generation process for adding a first waveform output generated by the first waveform generation process to a second waveform output obtained by waveform reproduction to form a musical sound waveform. To do.

  According to a fifth aspect of the present invention, there is provided a program that is executed by a waveform generator that forms a musical tone waveform by reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation, and an upper limit of a reproduction pitch A determination process for determining whether or not the sound generation channel is assigned a sound generation pitch that exceeds the sound generation pitch, and if the sound generation channel is determined to be a sound generation channel that is assigned a sound generation pitch that exceeds the upper limit of the playback pitch by the determination processing, A slot allocation process for allocating a plurality of channel slots required for decreasing the maximum address step value until the upper limit of the reproduction pitch is reached, and a maximum address among the plurality of channel slots allocated by the slot allocation process For channel slots restricted to step values, the restricted maximum Waveform output is generated by differential waveform playback based on the address step value, and in the channel slot to which the remaining address step value below the maximum address step value is assigned, the differential waveform playback based on the remaining address step value is performed. And a waveform generation process for generating a waveform waveform by accumulating the waveform outputs generated in each channel slot.

  According to a sixth aspect of the present invention, there is provided a program that is executed by a waveform generator that forms a musical tone waveform by reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation, and an upper limit of a reproduction pitch A determination process for determining whether or not the sound generation channel is assigned a sound generation pitch exceeding the sound generation pitch, and when the sound generation channel is determined to be assigned a sound generation pitch exceeding the upper limit of the playback pitch by the determination processing, the sound generation channel A slot designating process for designating a first channel slot corresponding to the second channel slot for continuing the differential waveform reproduction performed in the first channel slot, and a first channel designated by the slot designating process. In the slot, limit the pronunciation pitch to the maximum address step value that is the upper limit of the playback pitch, In the first waveform generation processing for generating the first waveform output in the differential waveform reproduction based on the limited maximum address step value, and in the second channel slot specified by the slot specification processing, the maximum from the tone generation pitch The tone waveform is obtained by adding the first waveform output generated by the first waveform generating means to the second waveform output obtained by differential waveform reproduction based on the remaining address step value obtained by subtracting the address step value. And a second waveform generation process to be formed.

  In the present invention, when it is determined that the sound generation channel is assigned a sound generation pitch exceeding the upper limit of the reproduction pitch, the preceding channel slot corresponding to the sound generation channel and the subsequent channel slot are designated. In the designated preceding channel slot, the tone generation pitch is limited to the maximum address step value that is the upper limit of the playback pitch, and the first waveform output is generated by the differential waveform playback based on the limited maximum address step value, In the subsequent channel slot, the first waveform output obtained in the preceding channel slot is added to the second waveform output obtained by the differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the sound generation pitch. Since the musical tone waveform is formed, the musical tone waveform exceeding the upper limit of the reproduction pitch determined by the limitation of the waveform address step value can be generated.

Embodiments of the present invention will be described below with reference to the drawings.
A. First embodiment
(1) Configuration
FIG. 1 is a block diagram showing a main configuration of the waveform generator according to the first embodiment of the present invention, and shows a configuration example of a waveform generator mounted on a sound source of an electronic musical instrument. In this figure, the clock generator 100 is composed of a 10-bit counter that counts the basic clock ck, and a clock mc [3: 0] that is the lower 4 bits output (3SB to 0SB (LSB)) of the counter; A clock mc [9: 4] that is an upper 6-bit output (9SB (MSB) to 4SB) is generated.

  Here, a correspondence relationship between the basic clock ck, the clock mc [3: 0], and the clock mc [9: 4] will be described with reference to FIG. As shown in this figure, the clock mc [9: 4] forms channel slots CH0 to CH63 respectively corresponding to 64 (0h to 3Fh) sound generation channels that perform time-division operation in the sound source. The period of the channel slots CH0 to CH63 corresponds to one sampling period 1 / Fs (Fs: sampling frequency) of the differential waveform data.

  The clock mc [3: 0] is composed of 16 (0h to Fh) processing slots “0h (0)” to “Fh (15)” of one channel slot CH formed by the clock mc [9: 4]. Divide into Based on the clock mc [9: 4] and the clock mc [3: 0], the operation timing of each component of the waveform generator illustrated in FIG. 1 is controlled.

  In FIG. 1, a RAM 10 is used as a work memory of a waveform generator. As shown in FIG. 3, the RAM 10 includes channel areas CH <b> 0 to CH <b> 63 respectively associated with the 64 sound generation channels included in the sound source. Data reading / writing in these channel areas CH0 to CH63 is performed in synchronization with the processing slot formed by the clock mc [3: 0] described above.

  Each channel area CH0 to CH63 of the RAM 10 has a pitch control flag F, an integer part pitch data P, a decimal part pitch data p, an integer part address A, a decimal part address a, a shift value E, a peak value X, and an output volume V. Stored. The pitch control flag F is “1” when the pitch of the musical sound waveform to be generated exceeds the upper limit of the reproduction pitch determined by the limit of the address step value, and is “0” otherwise.

  The integer part pitch data P and the fractional part pitch data p represent address step values corresponding to the pronunciation pitch. The integer part pitch data P and the fractional part pitch data p are collectively referred to as pitch data Pitch. The integer part address A and the fractional part address a represent the current waveform address (the phase of the differential waveform currently specified). The integer part address A and the fractional part waveform address a are collectively referred to as the current waveform address AD.

  The shift value E represents the amount of bit shift when the differential waveform data read from the waveform memory 30, that is, the differential waveform data of 8-bit width expressed in mantissa with 2's complement is expressed as a real number. The peak value X is a peak value obtained by integrating the differential waveform data corresponding to the current waveform address AD before update. The output volume V represents the amplitude level of the musical sound waveform to be output.

  In FIG. 1, the pitch control flag F read from the RAM 10 is stored in the pitch control flag register 11. The discrimination table 12 generates an output value “7” when the pitch control flag F output from the pitch control flag register 11 is “1”, that is, exceeds the upper limit of the reproduction pitch, while the pitch control flag F is In the case of “0”, an output value “0” is generated. The subtracter 13 generates a subtracted value obtained by subtracting the output value of the discrimination table 12 from the output of the pitch register 17 and supplies it to the controller 14 and the selector 15.

  The controller 14 gives the selector 15 a switching instruction according to the pitch control flag F output from the pitch control flag register 11 and the output (subtraction value) of the subtractor 13. The selector 15 selects one of pitch data Pitch (integer part pitch data P and fractional part pitch data p) read from the RAM 10, input data “0”, and the output of the subtractor 13 in response to a switching instruction from the controller 14. Select and store in the pitch register 17 of the next stage.

  When the value of the pitch control flag F output from the pitch control flag register 11 is “1”, the RAM controller 16 sets two consecutive channel slots (preceding channel slot CH, succeeding channel slot CH + 1) as one channel slot. The address of the RAM 10 is changed so that it can be seen. That is, if the value of the pitch control flag F read from the channel area CH corresponding to the preceding channel slot CH is “1”, the address of the preceding channel area CH is assigned to the succeeding channel slot CH + 1.

  When the pitch data Pitch output from the pitch register 17 is “7” or more, the pitch limiter 18 outputs the pitch data Pitch limited to “7”. If the pitch data Pitch output from the pitch register 17 is less than “7”, the through data is output as it is. That is, in the present embodiment, the maximum address step value in the differential waveform reproduction is set to “7”. If the pitch data Pitch is “7” or more, the maximum address step value is exceeded, so the pitch limiter 18 forcibly limits the pitch data Pitch to “7”.

  In this embodiment, as described above, when the pitch data Pitch exceeds “7”, that is, when the upper limit of the reproduction pitch determined by the limitation of the waveform address step value is exceeded, two consecutive channel slots CH , CH + 1 are regarded as one channel slot, the pitch data Pitch is limited to “7” by the pitch limiter 18 in the preceding channel slot CH to generate the maximum address step value “7”, and then the subsequent channel slot CH + 1 The address step value exceeding “7” is generated.

  Specifically, for example, if the pitch data Pitch read from the RAM 10 is “10”, the pitch data Pitch stored in the pitch register 17 via the selector 15 is “7” by the pitch limiter 18 in the preceding channel slot CH. ". In the subsequent channel slot CH + 1, “3” is obtained by subtracting (10−7) the output “7” of the discrimination table 12 from the pitch data Pitch stored in the pitch register 17 by the subtractor 13.

  If the pitch data Pitch read from the RAM 10 is less than “7”, for example “6”, the pitch data Pitch stored in the pitch register 17 via the selector 15 is stored in the pitch limiter 17 in the preceding channel slot CH. Since it passes through 18 as it is, it becomes “6”. In the subsequent channel slot CH + 1, the subtracter 13 subtracts (6-7) the output “7” of the discrimination table 12 from the pitch data Pitch stored in the pitch register 17 to become “−1”. In this case, since the secretor 15 selects the input data “0” according to the switching instruction from the controller 14, the output of the pitch limiter 18 eventually becomes “0”.

  The selector 20 selects either the current waveform address AD (integer part address A and fractional part address a) read from the RAM 10 or the output of the adder 19 and stores it in the ADC register 21 at the next stage in a predetermined processing slot. To do. When the selector 20 selects the current waveform address AD read from the RAM 10, the output of the pitch limiter 18 and the current waveform address AD output from the ADC register 21 are added by the adder 19, thereby the current waveform address. AD is updated. The adder 19 generates a decimal part carry when a carry occurs in the decimal part when adding the output of the pitch limiter 18 and the output of the ADC register 21 (current waveform address AD).

  The updated current waveform address AD is stored in the ADC register 21 via the selector 20. The updated current waveform address AD (integer part address A and decimal part address a) stored in the ADC register 21 is written to the corresponding channel area CH of the RAM 10 via the selector 42. The ADC LSB register 22 stores the least significant bit LSB of the integer part address A in the current waveform address AD stored in the ADC register 21.

  The adder 23 adds the decimal part carry generated by the adder 19 to the output of the pitch limiter 18 to generate a waveform address step value. The waveform address step value generated by the adder 23 is stored in the STEP register 24. The save register 25 functions as a delay buffer of the STEP register 24 and saves and stores the waveform address step value of the STEP register 24.

  The adder 26 adds “−6” to the integer part address A of the current waveform address AD output from the ADC register 21. The output of the adder 26 (integer part address A-6) is stored in the WADR register 28 via the selector 27 with the upper 15 bits excluding the least significant bit LSB. The output of the WADR register 28 becomes the read address WADR of the waveform memory 30. The incrementer 29 advances the read address WADR stored in the WADR register 28 in synchronization with a predetermined processing slot, and generates four read addresses WADR, WADR + 1, WADR + 2, and WADR + 3.

  As shown in FIG. 4, the waveform memory 30 has a storage area having a 16-bit width. In one storage area, 8-bit wide differential waveform data expressed as a mantissa in 2's complement is stored in the upper byte and the lower byte. The 8-bit width differential waveform data is bit-shifted according to a shift value stored in an E register 39, which will be described later, and becomes 16-bit differential waveform data.

  The waveform memory 30 reads the differential waveform data D0 to D3 according to the four read addresses WADR, WADR + 1, WADR + 2 and WADR + 3 which are sequentially generated by the WADR register 28. The differential waveform data D0 is composed of high-order byte differential waveform data D0H and low-order byte differential waveform data D0L. Similarly, the differential waveform data D1 includes differential waveform data D1H and D1L, the differential waveform data D2 includes differential waveform data D2H and D2L, and the differential waveform data D3 includes differential waveform data D3H and D3L.

  The differential waveform data D0 to D3 read from the waveform memory 30 is stored in the DW0 register 32 to DW3 register 35 via the selector 31. That is, the differential waveform data D0H and D0L are stored in the DW0 register 32, the differential waveform data D1H and D1L are stored in the DW1 register 33, the differential waveform data D2H and D2L are stored in the DW2 register 34, and the differential waveform data D3H is stored in the DW3 register 35. , D3L are stored respectively.

  The selector 31 stores the differential waveform data D0 to D3 read from the waveform memory 30 in the DW0 register 32 to DW3 register 35 in accordance with an instruction from the controller 37. The selector / shifter 36 selects the differential waveform data instructed by the controller 37 from the DW0 register 32 to DW3 register 35, and bit-shifts the selected differential waveform data according to the shift value E stored in the E register 39. Thus, the differential waveform data is expressed as a 16-bit real number.

  The adder 38 adds (integrates) the peak value X output from the X register 41 to the differential waveform data output from the selector 36. The controller 37 performs an integration calculation pattern (described later) according to the waveform address step value stored in the save register 25 and the value of the ADC LSB register 22 (the least significant bit LSB of the integer part address A in the current waveform address AD). ), The adder 38 selects differential waveform data for integrating the peak value X.

  Here, referring to FIG. 5 to FIG. 6, the waveform address step value stored in the save register 25 and the value of the ADC LSB register 22 (the least significant bit LSB of the integer part address A in the current waveform address AD) The contents of the determined integral calculation pattern will be described. FIG. 5 shows an integration calculation pattern when the value of the ADC LSB register 22 is “1”, and FIG. 6 shows an integration calculation pattern when the value of the ADC LSB register 22 is “0”. The integration calculation patterns shown in these figures are integral calculations determined according to the waveform address step values “0” to “7” stored in the save register 25 and the processing slot designated by the clock mc [3: 0]. The contents of

  First, an example of an integration operation when the value of the ADC LSB register 22 is “1” will be described with reference to FIG. It is assumed that the waveform address step value stored in the save register 25 is “7” when the value of the ADC LSB register 22 is “1”. At this time, if the processing slot “C” specified by the clock mc [3: 0] is specified, the integration operation is not performed, and “X = RAM” is expressed. “X = RAM” means that the peak value X read from the RAM 10 is stored in the X register 41 via the selector 40.

  Next, an integral operation “X = X + S (D0H)” is executed in the processing slot “D”. “X = X + S (D0H)” means that the peak value output from the X register 41 after the differential waveform data D0H stored in the DW0 register 32 is bit-shifted according to the shift value E stored in the E register 39. This means that X is integrated by the adder 38 and the integrated peak value is stored in the X register 41.

  Subsequently, an integration operation “X = X + S (D0L)” is executed in the processing slot “0”. “X = X + S (D0L)” is a peak value output from the X register 41 after the differential waveform data D0L stored in the DW0 register 32 is bit-shifted according to the shift value E stored in the E register 39. This means that X is integrated by the adder 38 and the integrated peak value is stored in the X register 41.

  Thereafter, similarly, “X = X + S (D1H)” in the processing slot “1”, “X = X + S (D1L)” in the processing slot “4”, and “X = X + S (D2H)” in the processing slot “5”. In the processing slot “8”, integration operations “X = X + S (D2L)” and “X = X + S (D3H)” in the processing slot “9” are executed.

  Next, an example of the integration operation when the value of the ADC LSB register 22 is “0” will be described with reference to FIG. It is assumed that the waveform address step value stored in the save register 25 is “6” when the value of the ADC LSB register 22 is “0”. At this time, if the processing slot “C” specified by the clock mc [3: 0] is specified, the integration operation is not performed, and “X = RAM” is expressed. “X = RAM” means that the peak value X read from the RAM 10 is stored in the X register 41 via the selector 40.

  Next, in the processing slot “D”, the adder 38 performs an operation “X = X + 0” that integrates “0” into the peak value X output from the X register 41. Subsequently, an integration operation “X = X + S (D0L)” is executed in the processing slot “0”. “X = X + S (D0L)” is a peak value output from the X register 41 after the differential waveform data D0L stored in the DW0 register 32 is bit-shifted according to the shift value E stored in the E register 39. This means that X is integrated by the adder 38 and the integrated peak value is stored in the X register 41.

  Next, in the processing slot “1”, an integral operation “X = X + S (D1H)” is executed. “X = X + S (D1H)” means that the peak value output from the X register 41 after the differential waveform data D1H stored in the DW1 register 32 is bit-shifted according to the shift value E stored in the E register 39. This means that X is integrated by the adder 38 and the integrated peak value is stored in the X register 41. Thereafter, “X = X + S (D1L)” in the processing slot “4”, “X = X + S (D2H)” in the processing slot “5”, “X = X + S (D2L)” in the processing slot “8”, Integration processing of “X = X + S (D3H)” is executed in the processing slot “9”.

  Now, the peak value X stored in the X register 41 by such an integration operation is supplied to the adder 38 as a peak value to be integrated next, and is also supplied to the multiplier 45. The VOL register 43 stores the output volume V read from the RAM 10. The ADC dec register 44 stores the decimal part address a of the current waveform address AD output from the ADC register 21.

The multiplier 45, the selector 46, and the adder / subtractor 47 are based on the fractional part address a of the current waveform address AD stored in the ADC dec register 44 and the following equation (1) for the peak value X stored in the X register 41: The peak value Y (n, a) calculated by this is stored in the Y register 48.
Y (n, a) = X (n) + a × {X (n + 1) −X (n)} (1)
In the above equation (1), n represents the number of times differential waveform data is read, and a represents the decimal part address.

  The peak value Y stored in the Y register 48 is written into the corresponding channel area CH of the RAM 10 via the selector 42 as the updated peak value X. The multiplier 49 multiplies the peak value Y output from the Y register 48 by the output (output volume V) of the VOL register 43. The adder 50, the selector 51, and the M register 52 accumulate all output waveforms of the sound generation channels output from the multiplier 49 to form a waveform output wave. This waveform output wave is D / A converted and output every sampling period in a sound source not shown.

(2) Operation
Next, the operation of the first embodiment having the above configuration will be described with reference to the timing charts shown in FIGS. In the following description of the operation, a processing slot in the channel slot CH0 is referred to as a CH0 processing slot, and a processing slot in the channel slot CH1 is referred to as a CH1 processing slot.

  First, in the data period d1 of the CH0 processing slot “0”, the pitch control flag f1 is read from the channel area CH0 of the RAM 10. In this example of operation, it is assumed that the pitch control flag f1 is “1”, that is, the tone pitch (pitch data Pitch) of the tone generation channel CH0 exceeds the upper limit of the reproduction pitch. The read pitch control flag f1 is stored in the pitch control flag register 11 in synchronization with the CH0 processing slot “1”. Next, in the data period d2 of the CH0 processing slot “2”, the pitch data Pitch (the integer part pitch data P and the fractional part pitch data p) is read from the channel area CH0 of the RAM 10.

  The read pitch data Pitch (integer part pitch data P and fractional part pitch data p) is stored in the pitch register 17 in the data period p1 of the CH0 processing slot “3”. In the data period d3 of the CH0 processing slot “3”, the current waveform address AD (the integer part address A and the fractional part waveform address a) is read from the channel area CH0 of the RAM 10. Further, in the data period sa1 of the CH0 processing slot “3”, the subtractor 13 generates a subtraction value (Pitch-7) obtained by subtracting the output value “7” of the discrimination table 12 from the pitch data Pitch.

  Next, in the data period p2 after the CH0 processing slot “3”, the output (Pitch-7) of the subtractor 13 is stored in the pitch register 17. In the data period a1 synchronized with the CH0 processing slot “4”, the current waveform address AD (integer part address A and fractional part waveform address a) read from the RAM 10 in the data period d3 is stored in the ADC register 21. The Further, in the data period sb1 of the CH0 processing slot “4”, the limit value “7” output from the pitch limiter 18 and the current waveform address AD of the ADC register 21 are added by the adder 19.

  In the data period STEP0 after the CH0 processing slot “4”, the decimal part carry generated by the adder 19 in response to the decimal part carry in the data period sb1 is the limit value “7” output from the pitch limiter 18. A waveform address step value obtained by adding to is generated and stored in the STEP register 24. Subsequently, in the data period a2 after the CH0 processing slot “5”, the current waveform address AD updated in the data period a1 is stored in the ADC register 21, while the ADC in the data period d4 of the CH0 processing slot “5”. The value of the register 21 (updated current waveform address AD) is stored in the channel area CH 0 of the RAM 10 via the selector 42.

  The current waveform address AD output from the ADC register 21 is obtained by adding “−6” to the integer part address A by the adder 26, and then the upper 15 bits excluding the least significant bit LSB are read out as WADR as WADR. Stored in register 28. Then, in the data periods WADR0 to WADR3 after the CH0 processing slot “8”, the read address WADR of the WADR register 28 is sequentially incremented by the incrementer 29 to generate four read addresses WADR, WADR + 1, WADR + 2 and WADR + 3.

  On the other hand, in the data period STEP 0 after the CH 0 processing slot “A”, the waveform address step value read from the STEP register 24 is saved in the save register 25. In the data period ADClsb0 after the CH0 processing slot “A”, the least significant bit LSB of the current waveform address AD stored in the ADC register 21 in the data period a2 of the CH0 processing slot “5” is stored in the ADC LSB register 22. . Next, in the data period ADCdec0 after the CH0 processing slot “B”, the decimal part address a of the current waveform address AD stored in the ADC register 21 in the data period a2 of the CH0 processing slot “5” is stored in the ADC dec register 44. To do.

  The differential waveform data D0 (D0H, D0L) to D3 (D3H, D3L) read by the waveform memory 30 according to the four read addresses WADR, WADR + 1, WADR + 2, and WADR + 3 sequentially output from the WADR register 28 are illustrated in FIG. Are stored in the DW0 register 32 to DW3 register 35 via the selector 31 at the timing of That is, the differential waveform data D0H and D0L are stored in the DW0 register 32, the differential waveform data D1H and D1L are stored in the DW1 register 33, and the differential waveform data D3H and D3L are stored in the DW2 register 34. Each is stored.

  Then, in the data period d9 of the CH0 processing slot “C”, the shift value E and the peak value X are read from the channel area CH0 of the RAM 10. The read shift value E is stored in the E register 39 in the data period E0 after the CH0 processing slot “D”. On the other hand, the peak value X is stored in the X register 41 in the data period X00 synchronized with the CH0 processing slot “D”.

  In the data period I00 of the CH0 processing slot “D”, the waveform address step value stored in the save register 25 and the value of the ADC LSB register 22 (the least significant bit LSB of the integer part address A in the current waveform address AD) are stored. Integral calculation is performed according to the integral calculation pattern determined according to.

  For example, as described above, when the value of the ADC LSB register 22 is “1” and the waveform address step value stored in the save register 25 is “7”, as illustrated in FIG. , The integration operation “X = X + S (D0H)” is executed in the data period I00 of the CH0 processing slot “D”. “X = X + S (D0H)” means that the peak value output from the X register 41 after the differential waveform data D0H stored in the DW0 register 32 is bit-shifted according to the shift value E stored in the E register 39. This means that X is integrated by the adder 38 and the integrated peak value is stored in the X register 41.

  Thereafter, “X = X + S (D0L)” is set in the data period I01 of the CH1 processing slot “0”, “X = X + S (D1H)” is set in the data period I02 of the CH1 processing slot “1”, and the CH1 processing slot “4” is set. “X = X + S (D1L)” in the data period I03, “X = X + S (D2H)” in the data period I04 in the CH1 processing slot “5”, and “X = X in the data period I05 in the CH1 processing slot“ 8 ”. X + S (D2L) ”and“ X = X + S (D3H) ”are executed in the data period I06 of the CH1 processing slot“ 9 ”.

  Then, as shown in FIG. 7, the peak value X obtained by the integration calculation of these processing slots is stored in the X register 41 in the corresponding data period X00 to X06, and is added as the peak value to be integrated next. Is supplied to the multiplier 45.

  If the transition from the CH0 process to the CH1 process is performed while such an integration operation is being performed, the pitch control flag f2 is read from the channel area CH1 of the RAM 10 in the data period d5 of the CH1 process slot “0”. Here, it is assumed that the value of the read pitch control flag f2 is “0”. Then, the RAM controller 16 assigns a read address that should originally be assigned to the channel area CH1 to the channel area CH0. By doing so, the processing of the preceding channel slot CH0 is continued in the channel slot CH1.

  That is, in the data period d6 of the CH1 processing slot “2”, the remaining pitch data Pitch after being limited to “7” in the channel slot CH0, that is, the subtractor 13 is discriminated from the pitch data Pitch stored in the pitch register 17. The remaining pitch data Pitch (integer part pitch data P and fractional part pitch data p) after subtracting the output “7” of the table 12 is generated.

  In the data period d7 of the CH1 processing slot “3”, the current waveform address AD (the integer part address A and the fractional part waveform address a) is read from the channel area CH0 of the RAM 10. Further, in the data period d8 of the CH1 processing slot “5”, the value of the ADC register 21 (the updated current waveform address AD) is stored in the channel area CH0 of the RAM 10 via the selector 42.

  The output volume V read from the channel area CH0 of the RAM 10 in the data period d10 (see FIG. 8) of the CH1 processing slot “8” is stored in the VOL register 43 in the data period V0 after the CH1 processing slot “9”. Is done. In the data period J00 synchronized with the CH1 processing slot “9”, X06 × ADCdec0 is calculated by multiplying the peak value X06 of the X register 41 by ADCdec0 (decimal part address a of the current waveform address AD) of the ADC dec register 44. In the subsequent data period J01, X07 × ADCdec0 is calculated by multiplying the peak value X07 of the X register 41 by ADCdec0 (decimal part address a of the current waveform address AD) of the ADC dec register 44.

  Next, in the data period Y00 of the CH1 processing slot “A” shown in FIG. 8, X06-X06 × ADCdec0, which is the elapsed value of the linear interpolation calculation, is generated and stored in the Y register 48, and in the subsequent data period Y01, the data X07 × ADCdec0 is added to X06−X06 × ADCdec0 generated in the period Y00. As a result, the linearly interpolated peak value Y (n, a) = X (n) + a × {X (n + 1) −X (n)} is stored in the Y register 48.

  In the data period K 0 synchronized with the CH 1 processing slot “B”, the peak value Y 01 stored in the Y register 48 is multiplied by the output volume V 0 of the VOL register 43. In the M register 52, after clearing to zero in synchronization with the CH1 processing slot “B”, the output waveform Y01 × V0 generated in the data period K0 is stored in the data period M0. As a result, an output waveform Y01 × V0 corresponding to the preceding channel slot CH0 is generated.

  Thereafter, according to the remaining pitch data Pitch (integer part pitch data P and fractional part pitch data p) obtained in the data periods d6 and d7 and the current waveform address AD (integer part address A and fractional part waveform address a). Thus, the output waveform Y11 × V11 of the subsequent channel slot CH1 is generated in the same process as described above. Then, the generated output waveform Y11 × V11 is accumulated in the M register 52 in the data period M1 after the CH2 processing slot “C”.

  As described above, in the first embodiment, the pitch control flag F indicating whether or not the tone pitch exceeds the upper limit of the reproduction pitch is provided for each of the channel areas CH0 to CH63 of the RAM 10 corresponding to the tone generation channels CH0 to CH63. If there is a tone generation channel having a pitch control flag F indicating that the upper limit of the playback pitch is exceeded, the preceding channel slot CH assigned to the tone generation channel and the succeeding channel slot CH + 1 are substantially one channel slot. I will look down.

  In the preceding channel slot CH, the pitch data Pitch is limited to the maximum address step value, the first output waveform is generated by the differential waveform reproduction based on the limited maximum address step value, and then the subsequent channel slot CH + 1. Then, the final output waveform is generated by adding the first output waveform to the second output waveform obtained by differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the pitch data Pitch. Therefore, it is possible to generate a musical sound waveform exceeding the upper limit of the reproduction pitch determined by the limitation of the waveform address step value.

B. Second Embodiment Next, a second embodiment will be described with reference to FIGS. In the first embodiment described above, if there is a tone generation channel having the pitch control flag F indicating that the upper limit of the reproduction pitch is exceeded, the preceding channel slot CH assigned to the tone generation channel and the subsequent channel slot CH + 1 are combined into one. It was considered as a channel slot. On the other hand, the second embodiment is not limited to two continuous channel slots as in the first embodiment described above, but extends the upper limit of the reproduction pitch by continuing two or more channel slots.

  FIG. 9 is a block diagram showing the configuration of the second embodiment. In this figure, the same number is attached | subjected to the same component as 1st Embodiment illustrated in FIG. 1, and the description is abbreviate | omitted. The configuration of the second embodiment illustrated in FIG. 9 is different from the first embodiment in that a channel register 200 is provided. The channel register 200 holds the number of the channel slot CH (the value of the clock mc [9: 4]) in which the pitch control flag F is first “1” until the pitch control flag F becomes “0”. The RAM controller 16 generates an address of the channel area CH of the RAM 10 corresponding to the channel slot CH number held in the channel register 200.

  Next, the operation of the second embodiment will be described with reference to the timing charts shown in FIGS. First, the pitch control flag f1 is read from the channel area CH0 of the RAM 10 in the data period d1 of the CH0 processing slot “0” shown in FIG. For example, if the pitch data Pitch of the channel slot CH0 is “16” exceeding the maximum address step value, the pitch control flag f1 is “1”. The pitch control flag f1 read in the data period d1 is stored in the pitch control flag register 11 in synchronization with the CH0 processing slot “1”.

  Next, in the data period d2 of the CH0 processing slot “2”, the pitch data Pitch (= “16”) is read from the channel area CH0 of the RAM 10. Further, in synchronization with the CH0 processing slot “2”, the value “0” of the clock mc [9: 4] is stored in the channel register 200 as the number C1 of the first channel slot CH in which the pitch control flag F becomes “1”. Stored. The pitch data Pitch read in the CH0 processing slot “2” is stored in the pitch register 17 in the data period p1 of the CH0 processing slot “3”.

  In the data period d3 of the CH0 processing slot “3”, the current waveform address AD (the integer part address A and the fractional part waveform address a) is read from the channel area CH0 of the RAM 10. Further, in the data period sa1 of the CH0 processing slot “3”, the subtractor 13 subtracts the output value “7” of the discrimination table 12 from the pitch data Pitch to generate a subtraction value (16−7 = 9).

  Next, the subtraction value “9” is stored in the pitch register 17 in the data period p2 after the CH0 processing slot “3”. In the data period a1 synchronized with the CH0 processing slot “4”, the current waveform address AD (integer part address A and fractional part waveform address a) read from the RAM 10 in the data period d3 is stored in the ADC register 21. Is done. Further, in the data period sb1 of the CH0 processing slot “4”, the limit value “7” output from the pitch limiter 18 and the current waveform address AD of the ADC register 21 are added by the adder 19.

  Subsequently, in the data period a2 after the CH0 processing slot “5”, the current waveform address AD updated in the data period a1 is stored in the ADC register 21, while the ADC in the data period d4 of the CH0 processing slot “5”. The value of the register 21 (updated current waveform address AD) is stored in the channel area CH 0 of the RAM 10 via the selector 42. Thereafter, the waveform output of the channel slot CH0 is generated by the same operation as in the first embodiment described above.

  Next, in the data period d5 of the CH1 processing slot “0”, the pitch control flag F of the channel area CH1 of the RAM 10 is read out originally, but since the RAM controller 16 maintains the address of the channel area CH0 of the RAM 10, Similar to the data period d1, the pitch control flag f1 of the channel area CH0 is read. The pitch control flag f1 read in the data period d5 is stored in the pitch control flag register 11 in synchronization with the CH1 processing slot “1”.

  Next, in the data period d6 of the CH1 processing slot “2”, the pitch data Pitch is originally read from the channel area CH1 of the RAM 10, but here, the subtraction value stored in the data period p2 after the CH0 processing slot “3”. Since “9” is held in the pitch register 17, the pitch data Pitch is not read.

  In the data period d7 of the CH1 processing slot “3”, the updated current waveform address AD (the integer part address A and the fractional part waveform address a) stored in the channel area CH0 of the RAM 10 in the data period d4 of the CH0 processing slot “5”. Is read. Further, in the data period sa2 of the CH0 processing slot “3”, the subtractor 13 subtracts the output value “7” of the discrimination table 12 from the previous subtraction value “9” to generate a subtraction value (9−7 = 2). To do.

  Next, in the data period p3 after the CH1 processing slot “3”, the subtraction value “2” is stored in the pitch register 17. In the data period a3 synchronized with the CH1 processing slot “4”, the current waveform address AD (integer part address A and fractional part waveform address a) read from the RAM 10 in the data period d7 is stored in the ADC register 21. Is done. Further, in the data period sb2 of the CH1 processing slot “4”, the limit value “7” output from the pitch limiter 18 and the current waveform address AD of the ADC register 21 are added by the adder 19.

  Subsequently, in the data period a4 after the CH1 processing slot “5”, the current waveform address AD updated in the data period a3 is stored in the ADC register 21, while the ADC in the data period d8 of the CH1 processing slot “5”. The value of the register 21 is stored in the channel area CH0 of the RAM 10 via the selector 42. Thereafter, the waveform output of the channel slot CH1 generated by the same operation as in the first embodiment is accumulated to the waveform output of the channel slot CH0 to form an accumulated waveform.

  Next, in the data period d9 of the CH2 processing slot “0”, the pitch control flag f1 of the channel area CH0 is read out similarly to the data period d5 of the CH1 processing slot “0”, and the read pitch control flag f1 is , Stored in the pitch control flag register 11 in synchronization with the CH2 processing slot “1”. Subsequently, in the data period d10 of the CH2 processing slot “2”, the pitch data Pitch is originally read from the channel area CH2 of the RAM 10, but here, the subtraction stored in the data period p3 after the CH1 processing slot “3” is stored. Since the value “2” is held in the pitch register 17, the pitch data Pitch is not read.

  In the data period d11 of the CH2 processing slot “3”, the updated current waveform address AD (the integer part address A and the fractional part waveform address a) stored in the channel area CH0 of the RAM 10 in the data period d8 of the CH1 processing slot “5”. Is read. Further, in the data period sa3 of the CH2 processing slot “3”, since the previous subtraction value “2” is equal to or less than the maximum address step value “7”, a subtraction value (2-0 = 2) is generated.

  Next, the subtraction value “2” is stored in the pitch register 17 in the data period p4 after the CH2 processing slot “3”. In the data period a5 synchronized with the CH2 processing slot “4”, the current waveform address AD (integer part address A and fractional part waveform address a) read from the RAM 10 in the data period d11 is stored in the ADC register 21. Is done. Further, in the data period sb3 of the CH2 processing slot “4”, the subtracted value “2” output from the pitch limiter 18 and the current waveform address AD of the ADC register 21 are added by the adder 19.

  Subsequently, in the data period a6 after the CH2 processing slot “5”, the current waveform address AD updated in the data period a5 is stored in the ADC register 21, while the ADC in the data period d12 of the CH2 processing slot “5”. The value of the register 21 is stored in the channel area CH0 of the RAM 10 via the selector 42. Thereafter, an output waveform is generated by adding the waveform output of the channel slot CH2 generated by the same operation as in the first embodiment to the accumulated waveform of the channel slots CH0 and CH1.

  As described above, in the second embodiment, if there is a sound generation channel having the pitch control flag F indicating that the upper limit of the reproduction pitch is exceeded, the sound pitch (pitch data Pitch) of this sound generation channel falls within the upper limit of the reproduction pitch. A plurality of channel slots required to decrease the maximum address step value by 1 are assigned to the sound generation channel.

  Of the plurality of channel slots, in the channel slot limited to the maximum address step value, an output waveform generated by differential waveform reproduction based on the limited maximum address step value is generated, and the maximum address step value is generated. In a channel slot to which a remaining address step value less than the decimal value is assigned, an output waveform obtained by differential waveform reproduction based on the remaining address step value is generated, and each output waveform generated in each channel slot is generated. Are sequentially accumulated to generate a final output waveform, so that it is possible to generate a tone waveform that exceeds the upper limit of the reproduction pitch determined by the limitation of the waveform address step value.

C. Third Embodiment Next, a third embodiment will be described with reference to FIGS. In the first embodiment described above, if there is a sound generation channel having the pitch control flag F indicating that the upper limit of the reproduction pitch is exceeded, the preceding channel slot CH assigned to the sound generation channel and the subsequent channel slot CH + 1 are combined into one. It was considered as a channel slot. On the other hand, in the third embodiment, the playback pitch is not limited to two continuous channel slots as in the first embodiment described above, and the two consecutive channel slots are regarded as one channel slot. It extends the upper limit of.

  FIG. 12 is a block diagram showing the configuration of the third embodiment. In this figure, the same number is attached | subjected to the same component as 1st Embodiment illustrated in FIG. 1, and the description is abbreviate | omitted. The configuration of the third embodiment shown in FIG. 12 is different from the first embodiment in that a channel register 300 that holds channel data C read from the RAM 10 is provided. FIG. 13 is a diagram showing a data configuration of the RAM 10 according to the third embodiment, and is the same as that of the first embodiment except for the channel data C.

  The channel data C designates the number of another channel slot that continues the differential waveform reproduction performed in the channel slot assigned to the sound generation channel that exceeds the upper limit of the reproduction pitch and the pitch control flag F is “1”. . The RAM controller 16 changes the address so that two non-consecutive channel slots are regarded as one channel slot according to the channel data C stored in the channel register 300. For example, if the pitch control flag F stored in the channel area CH0 of the RAM 10 is “1” and the channel data C is “15 (Fh)”, the RAM controller 16 is in the RAM 10 during the channel slot CH15. The address is changed to the address of the channel area CH0.

  Next, the operation of the third embodiment will be described with reference to the timing chart shown in FIG. In the following, an operation example is described assuming that the pitch control flag F stored in the channel area CH0 of the RAM 10 is “1” and the channel data C is “15”.

  Assume that the pitch control flag f1 (= “1”) and the channel data C (= “15”) are read from the channel area CH0 of the RAM 10 in the data period d1 of the CH0 processing slot “0” illustrated in FIG. Then, the pitch control flag f1 is stored in the pitch control flag register 11 in synchronization with the CH0 processing slot “1”, while the channel data C is stored in the channel register 300.

  Next, in the data period d2 of the CH0 processing slot “2”, the pitch data Pitch is read from the channel area CH0 of the RAM 10. The read pitch data Pitch is stored in the pitch register 17 in the data period p1 of the CH0 processing slot “3”. In the data period d3 of the CH0 processing slot “3”, the current waveform address AD (the integer part address A and the fractional part waveform address a) is read from the channel area CH0 of the RAM 10. Further, in the data period sa1 of the CH0 processing slot “3”, the subtractor 13 subtracts the output value “7” of the discrimination table 12 from the pitch data Pitch to generate a subtraction value.

  Next, the subtraction value is stored in the pitch register 17 in the data period p2 after the CH0 processing slot “3”. Next, in the data period a1 synchronized with the CH0 processing slot “4”, the current waveform address AD read from the RAM 10 in the data period d3 is stored in the ADC register 21. Further, in the data period sb1 of the CH0 processing slot “4”, the limit value “7” output from the pitch limiter 18 and the current waveform address AD of the ADC register 21 are added by the adder 19.

  Subsequently, in the data period a2 after the CH0 processing slot “4”, the current waveform address AD updated in the data period a1 is stored in the ADC register 21. In the data period d4 of the CH0 processing slot “5”, the value of the ADC register 21 (updated current waveform address AD) is stored in the channel area CH0 of the RAM 10 via the selector. Thereafter, an output waveform is generated by differential waveform reproduction based on the maximum address step value by the same operation as in the first embodiment described above.

  Thereafter, when the data period d9 of the CH15 processing slot “0” is reached, the pitch control flag f3 is read from the channel area CH15 of the RAM 10. In the channel area CH15 of the RAM 10, the remaining pitch data Pitch after being limited to the maximum address step value “7” in the channel slot CH0 is set. Therefore, the value of the pitch control flag f3 stored in the channel area CH15 of the RAM 10 is “0”. The pitch control flag f3 is stored in the pitch control flag register 11 in synchronization with the CH15 processing slot “1”.

  Next, in the data period d10 of the CH15 processing slot “2”, the pitch data Pitch is originally read from the channel area CH15 of the RAM 10, but the RAM controller 16 changes the address of the RAM 10 to the address of the channel area CH0. The remaining pitch data Pitch after being limited to the maximum address step value “7” is read from the channel area CH10 of the RAM 10. The read pitch data Pitch is stored in the pitch register 17 in the data period p4 after the CH15 processing slot “3”.

  In the data period d11 of the CH15 processing slot “3”, the current waveform address AD (integer part address A and fractional part waveform address a) is read from the channel area CH0 of the RAM 10 by changing the address of the RAM controller 16. Further, in the data period sa3 of the CH15 processing slot “3”, the subtractor 13 subtracts the output value “0” of the discrimination table 12 from the pitch data Pitch to generate a subtraction value (Pitch-0).

  Next, in the data period a5 synchronized with the CH15 processing slot “4”, the current waveform address AD read from the RAM 10 in the data period d11 is stored in the ADC register 21. Further, in the data period sb3 of the CH15 processing slot “4”, the adder 19 adds the subtraction value (Pitch-0) output through from the pitch limiter 18 and the current waveform address AD of the ADC register 21. Subsequently, in the data period a6 after the CH15 processing slot “4”, the current waveform address AD updated in the data period a5 is stored in the ADC register 21.

  Thereafter, according to the remaining pitch data Pitch (integer part pitch data P and fractional part pitch data p) obtained in the data periods d10 and d11 described above and the current waveform address AD (integer part address A and fractional part waveform address a). Thus, an output waveform of the channel slot CH15 is generated and accumulated in the output waveform of the channel slot CH0.

  As described above, in the third embodiment, for each channel area CH0 to CH63 of the RAM 10 corresponding to the sound generation channels CH0 to CH63, the pitch control flag F indicating whether the sound generation pitch exceeds the upper limit of the reproduction pitch, Channel data C for designating the number of another channel slot for continuing the differential waveform reproduction performed in the channel slot assigned to the sound generation channel for which the pitch control flag F is “1” is provided, and the reproduction pitch is set. When there is a sound generation channel having a pitch control flag F indicating that the upper limit is exceeded, the first channel slot assigned to the sound generation channel and the second channel slot specified by the channel data C are substantially one. Think of it as a channel slot.

  Then, in the first channel slot, the pitch data Pitch is limited to the maximum address step value, and after the first output waveform is generated by the differential waveform reproduction based on the limited maximum address step value, In the channel slot, the final output waveform is obtained by adding the first output waveform to the second output waveform obtained by differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the pitch data Pitch. Therefore, it is possible to generate a tone waveform that exceeds the upper limit of the reproduction pitch determined by the limit of the waveform address step value.

  In the first to third embodiments described above, the waveform generation apparatus is configured by hardware. However, the gist of the present invention is not limited to hardware, and the function is implemented by software. Needless to say, this is applicable even in cases.

It is a block diagram which shows the structure of 1st Embodiment by this invention. It is a figure which shows the correspondence of basic clock ck, clock mc [3: 0], and clock mc [9: 4]. It is a memory map which shows the data structure of RAM10 in 1st Embodiment. 3 is a memory map showing a data structure of a waveform memory 30. It is a figure for demonstrating the integral calculation pattern in case the value of the ADC LSB register | resistor 22 is "1". It is a figure for demonstrating the integral calculation pattern in case the value of the ADC LSB register | resistor 22 is "0". It is a time chart for demonstrating operation | movement of 1st Embodiment. It is a time chart for demonstrating operation | movement of 1st Embodiment. It is a block diagram which shows the structure of 2nd Embodiment. It is a time chart for demonstrating operation | movement of 2nd Embodiment. It is a time chart for demonstrating operation | movement of 2nd Embodiment. It is a block diagram which shows the structure of 3rd Embodiment. It is a memory map which shows the data structure of RAM10 in 3rd Embodiment. It is a time chart for demonstrating operation | movement of 2nd Embodiment.

Explanation of symbols

10 RAM
11 Pitch control flag register 12 Discrimination table 13 Subtractor 14, 37 Controller 15, 20, 27, 31, 40, 42, 46, 51 Selector 16 RAM controller 17 Pitch register 18 Pitch limiter 19, 23, 26, 38, 50 Addition Device 21 ADC register 22 ADC LSB register 24 STEP register 25 Save register 28 WADR register 29 Incrementer 30 Waveform memory 32 to 35 DW0 to DW3 register 36 Selector / shifter 39 E register 41 X register 43 VOL register 44 ADC dec register 45, 49 Multiplier 47 Adder / Subtractor 48 Y register 52 M register

Claims (6)

In a waveform generator that forms a musical sound waveform by reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation,
A discriminating means for discriminating whether or not the tone generation channel is assigned a tone pitch exceeding the upper limit of the playback pitch;
A slot designating unit for designating a preceding channel slot corresponding to the sounding channel and a subsequent channel slot when the sounding channel is assigned with a sounding pitch exceeding the upper limit of the reproduction pitch by the determining unit;
In the preceding channel slot designated by the slot designating means, the tone generation pitch is limited to the maximum address step value which is the upper limit of the reproduction pitch, and the first difference waveform is reproduced based on the limited maximum address step value. First waveform generating means for generating a waveform output;
In the subsequent channel slot designated by the slot designating means, the second waveform output obtained by differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the tone generation pitch is used as the first waveform. A waveform generator comprising: a second waveform generator configured to add a first waveform output generated by the generator to form a musical sound waveform. In a waveform generator that forms a musical sound waveform by reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation,
A discriminating means for discriminating whether or not the tone generation channel is assigned a tone pitch exceeding the upper limit of the playback pitch;
A plurality of channel slots required to decrease the maximum address step value until the sound generation pitch falls within the upper limit of the reproduction pitch when the determination means determines that the sound generation channel is assigned with the sound generation pitch exceeding the upper limit of the reproduction pitch. Slot assigning means for assigning to the sound channel;
Among the plurality of channel slots assigned by the slot assigning means, in the channel slot restricted to the maximum address step value, a waveform output is generated by differential waveform reproduction based on the restricted maximum address step value, In the channel slot to which the remaining address step value less than or equal to the maximum address step value is assigned, a waveform output obtained by differential waveform reproduction based on the remaining address step value is generated and generated in each of these channel slots. And a waveform generating means for accumulating each waveform output to form a musical sound waveform. In a waveform generator that forms a musical sound waveform by reproducing a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation,
A discriminating means for discriminating whether or not the tone generation channel is assigned a tone pitch exceeding the upper limit of the playback pitch;
When it is determined that the sound generation channel is assigned a sound generation pitch exceeding the upper limit of the playback pitch by the determination means, the first channel slot corresponding to the sound generation channel and the differential waveform reproduction performed in the first channel slot are performed. Slot designation means for designating a second channel slot to be continued;
In the first channel slot designated by the slot designating means, the tone generation pitch is limited to the maximum address step value which is the upper limit of the playback pitch, and the first is performed by differential waveform playback based on the limited maximum address step value. First waveform generating means for generating a waveform output of
In the second channel slot designated by the slot designating means, the second waveform output obtained by the differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the tone generation pitch is used as the first waveform output. A waveform generator comprising: a second waveform generator configured to add a first waveform output generated by the waveform generator to form a musical sound waveform. A program executed by a waveform generator that reproduces a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform,
A determination process for determining whether or not the sound generation channel is assigned a sound generation pitch that exceeds the upper limit of the playback pitch;
A slot designating process for designating a preceding channel slot corresponding to the sounding channel and a subsequent channel slot when the sounding channel is assigned with a sounding pitch exceeding the upper limit of the reproduction pitch by the determining process;
In the preceding channel slot designated by the slot designation process, the tone generation pitch is limited to the maximum address step value that is the upper limit of the reproduction pitch, and the first difference waveform is reproduced based on the limited maximum address step value. A first waveform generation process for generating a waveform output;
In the subsequent channel slot designated by the slot designation process, the first waveform is output to the second waveform output obtained by the differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the tone generation pitch. A waveform generation processing program comprising: a second waveform generation process for forming a musical sound waveform by adding the first waveform outputs generated by the generation process. A program executed by a waveform generator that reproduces a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform,
A determination process for determining whether or not the sound generation channel is assigned a sound generation pitch that exceeds the upper limit of the playback pitch;
A plurality of channel slots required for decreasing the maximum address step value until the sound generation pitch falls within the upper limit of the reproduction pitch when it is determined by the determination process that the sound generation channel is assigned with the sound generation pitch exceeding the upper limit of the reproduction pitch. Slot assignment processing for assigning to the sound channel;
Among the plurality of channel slots allocated by the slot allocation process, in the channel slot limited to the maximum address step value, a waveform output is generated by differential waveform reproduction based on the limited maximum address step value, In the channel slot to which the remaining address step value less than or equal to the maximum address step value is assigned, a waveform output obtained by differential waveform reproduction based on the remaining address step value is generated and generated in each of these channel slots. A waveform generation processing program comprising: waveform generation processing for accumulating each waveform output to form a musical sound waveform. A program executed by a waveform generator that reproduces a differential waveform for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation to form a musical sound waveform,
A determination process for determining whether or not the sound generation channel is assigned a sound generation pitch that exceeds the upper limit of the playback pitch;
When it is determined by the determination process that the sound generation channel is assigned a sound generation pitch exceeding the upper limit of the reproduction pitch, the first channel slot corresponding to the sound generation channel and the difference waveform reproduction performed in the first channel slot are performed. Slot designation processing for designating a second channel slot to be continued;
In the first channel slot designated by the slot designation process, the tone generation pitch is limited to the maximum address step value that is the upper limit of the reproduction pitch, and the first difference waveform is reproduced based on the limited maximum address step value. A first waveform generation process for generating a waveform output of
In the second channel slot designated by the slot designation process, the second waveform output obtained by the differential waveform reproduction based on the remaining address step value obtained by subtracting the maximum address step value from the tone generation pitch is used as the first waveform output. A waveform generation processing program comprising: a second waveform generation process for adding a first waveform output generated by the waveform generation means to form a musical sound waveform.