JPH04102080U - waveform generator - Google Patents

Abstract

(57) [Summary] [Purpose] To realize a waveform generator that can easily change the output position of waveform B without requiring rewriting of trigger data. [Structure] Equipped with two systems of analog waveform generation means that read waveform data from the waveform memory using separate clocks, sequentially convert it to analog, and output it. One system is clocked based on trigger data output from the other system. In a waveform generator having a function of determining the input start and adding the output waveforms of the two systems and outputting the resultant waveform as one waveform, the clock input is delayed by a predetermined time and the amount of delay can be changed as appropriate. A variable delay circuit is provided so that the addition position of one output waveform to the other output waveform can be changed as appropriate.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to a waveform generator, and more specifically, to a waveform generator that adds two generated waveforms to one This paper relates to improving the waveform addition position when creating two waveforms.

0002

[Conventional technology]

Traditionally, waveform data imported into waveform memory is sequentially read out and then converted into analog data. Two systems of waveform generation circuits are available to obtain analog waveforms by converting and outputting analog waveforms. , output the waveforms of two channels separately, or add the waveforms of two channels to create one analog There are waveform generators that are configured so that they can be output as a graphical waveform.

0003 FIG. 3 is a block diagram of a conventional waveform generator of this type. Note that Figure 4 shows the clock generation A configuration diagram showing details of the device, and FIG. 5 is a time chart. However, in Figure 5, Waveform B is conceptually shown in a compressed form in the time axis direction. The waveform memory 10 contains waveform A data and trigger data (1-bit data). Multiple items are stored in pairs. The data in the waveform memory (b in Figure 5) is The trigger data ( c) in FIG. 5 and the waveform data are output separately. Waveform data is digital The signal is input to a log converter (hereinafter referred to as a DA converter) 11, converted into analog data, and then increased. It is appropriately amplified by the amplifier 12 and then passed through the filter 13 and attenuator 14 to provide a smooth signal. Shaped into an analog waveform. On the other hand, the data of waveform B (e in FIG. 5) stored in the waveform memory 20 is also Analog waveform through DA converter 21, amplifier 22, filter 23, and attenuator 24 is output as Read data from waveform memory and convert with DA converter is performed in synchronization with the clock.

0004 40 is an adder, 41, 42, 43 are switches, and the switch 41 is OFF, and when switches 42 and 43 are ON, the first and second waveform memories The two analog waveforms read from are output separately. When switches 41 and 42 are turned on and switch 43 is turned off, two analog The added waveforms are added by an adder 40 and the added waveform is output via a switch 42. In the clock generator 30 shown in FIG. 4, 31 is an edge-triggered flip-flop. A HIGH level signal is always applied to the D input, and the waveform memory When the trigger data (1 bit data) given from 10 changes from 0 to 1 At this point, the output Q1 of the flip-flop becomes HIGH level (g in FIG. 5).

[0005] The Q1 signal is delayed by a predetermined time Δt in the delay circuit 32, and then passed through the AND gate 33. to go into. The clock CLK2 (i in Figure 5) output from the gate 33 is a one-shot clock. A pulse of a predetermined time width T1 is inputted to the clock pulse generator 34, and a pulse of a predetermined time width T1 is generated at the rising edge of the clock. (j in Figure 5). The edge trigger type flip-flop 35 is activated at the rising edge of the output pulse of Q4. Output Q5 becomes HIGH level (m in FIG. 5). On the other hand, the counter 36 indicates that Q4 is H. Start counting the clock CLK2 at IGH level and count the clock a predetermined number of times. (this period is T2), an overflow signal R (l in Figure 5) is output. and resets the flip-flop 35, flip-flop 31 and pulse generator 34. cut.

[0006] The output Q5 of the flip-flop 35 is HIGH when the output Q4 of the pulse generator 34 is HIGH. It remains at HIGH level until the reset signal R is input. ing. Gate 37 gates the clock by this signal Q5 and is shown in FIG. The output Q6 is outputted as a clock. Waveform B is read by this clock Q6. Extrusion is carried out. With this configuration, data for waveform B can be read out more easily than data for waveform A. Starting at a timing delayed by △t time, the output waveform from waveform B enters the adder. is added to the output waveform from waveform A, and output as one analog waveform.

[0007]

[Problem that the idea aims to solve] By the way, in conventional waveform generators, the addition position of waveform B (waveform B with respect to waveform A) (addition point), the trigger data must be rewritten and the operation The problem was that it was extremely complicated. The purpose of this invention is to eliminate such drawbacks and to rewrite trigger data. Waveform generation that allows you to easily change the output position of waveform B without the need for It is an attempt to realize a vessel.

[0008]

[Means to solve the problem]

In order to achieve this purpose, this invention Outputs the output clock of the clock generator with a predetermined time delay, and also Equipped with a variable delay circuit configured to change the amount as appropriate, one output waveform The feature is that the addition position of the other output waveform can be changed as appropriate. Ru.

[0009]

[Effect]

One waveform memory contains timing information for reading waveform data from the other waveform memory. The trigger data that determines the waveform data is stored in pairs with the waveform data. When reading data from one waveform memory, separate the waveform data and trigger data. Release and output. Based on the trigger data (for example, when the trigger data is 1), the clock generator ) Open the gate and let the clock pass. Furthermore, this clock is connected to a variable delay circuit. is delayed by a predetermined time via . the other wave based on this delayed clock. Reading of data from the shaped memory begins. The delay time in the variable delay circuit can be changed arbitrarily, so the trigger data The output waveform from one waveform memory can be compared to the output waveform from the other waveform memory without changing the data. It is possible to easily change the addition position of the output waveform from the source.

0010

【Example】

The present invention will be explained in detail below using the drawings. Figure 1 shows the waveform generator according to the present invention. FIG. 2 is a main part configuration diagram showing one embodiment, and is a time chart for explaining the operation. however In FIG. 2, waveform B is conceptually shown in a compressed form in the time axis direction. In FIG. 1, parts equivalent to those in FIG. 3 are given the same reference numerals. In addition, in Figure 1 The details of the clock generator 30 are the same as those in FIG. 4, and illustration thereof is omitted. Figure 1 Smell The difference from the conventional example shown in FIG. This is where the delay circuit 50 is inserted.

[0011] The variable delay circuit 50 outputs the clock output from the clock generator 30 for a predetermined period of time. The amount of delay (delay time) can be controlled externally. Ru. The delayed clock is supplied to waveform memory 20 and DA converter 21.

0012 The operation in such a configuration will be explained next. Reading from waveform memory 10 The operation and the operation of clock generator 30 are the same as in the prior art. clock generator 30 The clock output from is as shown in n in FIG. The variable delay circuit 50 This clock is delayed by Δt1 time and output as shown at p in FIG. △t1 can be set arbitrarily by an external signal. The clock provided by the variable delay circuit 50 The waveform data is read out from the waveform memory 20 by the DA converter 21. Converted to log signal. The subsequent operation is the same as before, adding waveform A and waveform B. The calculated waveform becomes as shown in q of FIG.

[0013] According to such a configuration, by adjusting the delay amount Δt1, the waveform A can be adjusted. The addition position of waveform B can be easily changed.

[0014]

[Effect of the idea]

As explained above, according to the present invention, the variable device is connected after the clock generator for waveform B. Trigger data can be rewritten simply by adding a delay circuit and increasing or decreasing its delay amount. This makes it possible to easily change the addition position of waveform B to waveform A, which is faster than before. Improved operability.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a waveform generator according to the present invention.

FIG. 2 is a time chart for explaining the operation of the waveform generator of the present invention.

FIG. 3 is a configuration diagram of a conventional waveform generator.

FIG. 4 is a configuration diagram showing details of the clock generator in FIG. 3;

FIG. 5 is a time chart for explaining the operation of a conventional waveform generator.

[Explanation of symbols]

10, 20 waveform memory 11, 21 DA converter 12,22 Amplifier 13,23 Filter 14, 24 Attenuator 30 Clock generator 31,35 flip flop 32 Delay circuit 33,37 gate 34 One shot pulse generator 36 counter 40 Adder 41, 42, 43 switch 50 Variable delay circuit

Claims (1)

[Scope of utility model registration request] Claims: 1. Two systems of analog waveform generation means for sequentially converting and outputting data read from a waveform memory into analog form; one waveform memory stores waveform data and trigger data as a pair; When reading data from memory, waveform data and trigger data are output separately,
It is equipped with a clock generator that outputs a clock for reading the other waveform data based on the trigger data, and the waveform data is read from the other waveform memory using the clock output from this clock generator, and the waveform data is output from the waveform memory. In a waveform generator configured to add two output waveforms and output as one analog waveform, the output clock of the clock generator is delayed by a predetermined time and outputted, and the amount of delay can be changed as appropriate. What is claimed is: 1. A waveform generator comprising a variable delay circuit configured to allow the addition position of one output waveform to another output waveform to be changed as appropriate.