JPH02241220A - Pulse train generator - Google Patents

Abstract

PURPOSE:To arbitrarily set a period of a pulse, and a timing for generating leading and trailing edges of each pulse by a prescribed resolution by providing a leading edge setting means for setting a timing of a leading edge of a pulse, and a fall setting means for setting a timing of a trailing edge. CONSTITUTION:This device is constituted of a leading edge setting means 100 for setting a timing of a leading edge of an output pulse, a trailing edge setting means 110 for setting a timing of a leading edge, and a pulse forming means 120 for forming an output pulse, based on the timings which are set by both the setting means concerned 100, 110, respectively. As for the leading edge setting means 100 and the fall setting means 110, the circuit constitutions are the same substantially. The leading edge setting means 100 is provided with a main memory circuit 101, an RZ circuit 103, a programmable delaying circuit 104 and a programmable delay memory circuit 105.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a pulse generator, and in particular, a pulse generator that digitally sets the period of a pulse and the timing of the rising and falling edges of each pulse arbitrarily with a predetermined resolution. The present invention relates to a pulse train generator capable of generating a pulse train.

[Technical Background of the Invention and Problems Therewith] In conventional digital pulse train generators, the generation of the pulse train cannot be interrupted at the same time in the middle of the pulse period and the timing of the rising and falling edges of each pulse. Timing on the fly (ti
miB on the fly) function, RZ (re
turn to zero), N RZ (non
Some devices are equipped with a format on the fly function that allows the output format of each pulse, such as return to zero, to be changed midway through without interrupting the generation of the pulse train.

Pulse train generators having these functions generally have a circuit configuration as shown in FIG. 5, but these circuit configurations require complicated circuits and architecture.

Furthermore, since the output format is mainly created using hardware, only pre-designed formats can be output, and the types thereof are therefore limited.

[Objective of the Invention] An object of the present invention is to provide a device that can arbitrarily set the pulse period and the timing of the rising and falling edges of each pulse with a predetermined resolution using a relatively simple circuit configuration. shall be.

[Summary of the Invention] According to an embodiment of the present invention, there is provided a rising edge setting means for setting the timing of the rising edge of each pulse, a falling edge setting means for setting the timing of the falling edge of each pulse, and the rising edge setting means for setting the timing of the falling edge of each pulse. A digital pulse generator is provided, comprising: means for generating output pulses, and pulse forming means for forming output pulses based on the timings respectively set by the falling edge setting means. The falling edge setting means is comprised of almost the same circuit as the rising edge setting means.

The rising edge setting means includes a main memory circuit, an R2 circuit, a programmable delay circuit, and a programmable delay memory circuit. The main memory circuit can divide the human clock applied thereto by any natural number greater than or equal to 2, and can apply a rough delay to the human clock. The R2 circuit has one power connected to the input clock through a delay circuit, and the other power connected to the output of the main memory circuit, and performs an AND operation of the two powers. The R2 circuit becomes effective when the periods of the input clock and the output pulse train are the same.

The input of the programmable delay circuit is connected to the output of the R2 circuit to apply a slight delay to the output.

The programmable delay memory circuit stores a setting value regarding the delay of the programmable delay circuit, is connected to the programmable delay circuit, and is used to set the delay of the delay circuit to a desired value. Each input of the pulse forming circuit is connected to the output of the programmable delay circuit of each of the rising edge setting means and the falling edge setting means, and has the timing of the rising edge and falling edge respectively set by these edge setting means. Form the output pulse.

In this way, the present invention can arbitrarily set the pulse period and the timing of the rising and falling edges of each pulse with a predetermined resolution using a relatively simple circuit configuration.

[Embodiments of the invention] FIG. 1 shows an embodiment of the pulse train generator of the present invention.

This device includes a rising edge setting means 100 for setting the timing of the rising edge of the output pulse of this device, and a falling edge setting means 110 for setting the timing of the falling edge of the output pulse of this device.
, and a pulse forming means 120 that forms an output pulse based on the timings respectively set by the setting means 100 and 110. The rising edge setting means 100 and the falling edge setting means 110 have substantially the same circuit configuration. The rising edge setting means 100 includes a main memory circuit 101, an R2 circuit 103, a programmable delay circuit 104, and a programmable delay memory circuit 105.

The main memory circuit 101 stores data regarding the level generation of output pulses (hereinafter referred to as pulse data).
It is driven by a human clock signal CLK and sequentially outputs a pulse train waveform based on the pulse data. Depending on the content of the pulse data, the high-power clock signal CLK can be set to any two
The frequency is divided by the above natural number and a coarse delay is applied. Main memory circuit 101 is 256 kilowords or 1 megaword in size. Human clock signal CL
The frequency of K is 100MH2. Although the present device may operate based on either the rising edge or the falling edge of the manual clock signal CLK, the following description assumes that it operates based on the rising edge.

The pulse data stored in the main memory circuit 101 is
For example, when the data is 0101010101..., the data is sequentially outputted by the input clock signal CLK, and at the output end of the main memory circuit 101, a pulse train based on the data as shown in FIG. 2(b) is generated. A waveform is generated.

The human power clock signal CLK is also delayed by the delay circuit 102 by the signal propagation delay in the main memory circuit 101 and is applied to one human power of the R2 circuit 103. The output of the main memory circuit 101 is connected to the other input terminal of the R2 circuit 103. The R2 circuit 103 is mainly composed of an AND circuit, and ANDs the respective outputs of the delay circuit 102 and the main memory circuit 101, and outputs the result. The R2 circuit 103 is effective when the desired pulse train of this device has the same frequency as the input clock signal CLK. This means that when the pulse data of the main memory circuit 101 is 1111111111...
The output level of the main memory circuit 101 remains unchanged (DC signal)
This is because it becomes . The output of R2 circuit 103 is shown in FIG. 2(c). The frequency of the output pulse is the same as the CLK
If a lower value is acceptable, the R2 circuit 103 is not necessarily required.

The programmable delay circuit 104 is a circuit for setting the timing of the rising edge of each pulse of the output pulse train of this device with high resolution. As is clear from the above description, the timing of setting the rising edge of the output of the R2 circuit 103 with respect to a certain reference point is the cycle of the manual clock signal CLK. It can only be set with a resolution of 1 Onsec. Although the resolution can be improved by increasing the frequency of the input clock signal CLK, the main memory circuit 10
It is not possible to obtain a resolution of several hundred psec in relation to the operating frequency range of 1. The programmable delay circuit 104 is composed of a commercially available programmable delay line with a resolution of 100 ρs, ec, and the R2 circuit 103
By applying a slight delay to the output of the output pulse, it is possible to set the timing of the rising edge of the output pulse with a high resolution of 100 ρsec. The total variable delay range in the programmable delay circuit 104 only needs to be 100 seconds, which is the period of the input clock signal CLK. The output of the programmable delay circuit 104 when a delay of 3 nsec is applied is shown in Figure 2 (d).
) is shown.

The programmable delay memory circuit 105 stores a setting value for setting the delay of the programmable delay circuit 104, and is driven by the input clock signal CLK that has passed through the delay circuit 106 to convert the delay setting value into a programmable delay. The signal is sent to the circuit 104, and the delay amount of the delay circuit 104 is set to a desired value.

Programmable delay memory circuit 105 requires the same memory size as main memory circuit 101.

The pulse forming means 120 is constituted by, for example, a flip-flop circuit with a reset terminal as shown in FIG. 3(a). Since the D terminal is connected to high level,
When the clock terminal C is clocked by the output of the programmable delay circuit 104 in the rising edge setting means 100, the output of the output terminal Q becomes high level at the rising edge. Next, the output of the programmable delay circuit 114 in the falling edge setting means 110 drives the reset terminal R, and the rising edge causes the output of the output terminal 0 to become low level. As a result, the rising edge setting means 1
It is possible to obtain an output pulse in which the timing of the rising edge is controlled by the output of 00 and the timing of the falling edge is controlled with high resolution of 100 psec by the output of the falling edge setting means 110. Furthermore, the output pulse width and output frequency can also be set arbitrarily. This situation is shown in FIG. 3(b).

In order to obtain the output pulse train waveform shown in FIG.
Main memory circuit 101: 01001011010 Main memory circuit 111: 01001011010 Programmable delay memory circuit 105: 0 0 0 0 0'
Olns 7ns O3ns O programmable delay memory circuit 115:0 8ns OO8ns
It is sufficient to store the data of 0 3ns 9ns 0 5ns O.

[Effects of the Invention] As explained above, by using the present invention, the period of the output pulse and the timing of the rising and falling edges of each pulse can be arbitrarily controlled with a predetermined high resolution using a relatively simple circuit configuration. Therefore, timing-on-the-fly and arbitrary format-on-the-fly can be easily achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the pulse train generator of the present invention, FIG. 2 is a diagram for explaining the operation of the device, and FIG. 3 is an embodiment of the pulse forming means used in the device. FIG. 4 is a diagram showing an example of an output pulse train waveform made possible by the present invention, and FIG. 5 is a diagram showing an example of a conventional pulse train generator. 100: Rising edge setting means 110: Falling edge setting means 120; Pulse forming means

Claims (2)

[Claims] (1) A pulse train generator comprising the following (a) and (b). (a) a main memory circuit that stores pulse data regarding the level of the output pulse and sequentially outputs the pulse data by being driven by an input clock signal; a programmable delay circuit that delays the output of the main memory circuit with a short time resolution; and a programmable delay circuit that stores delay data for setting the amount of delay in the programmable delay circuit to a predetermined value, and is driven by the input clock signal to delay the output of the main memory circuit. A programmable delay memory circuit that sequentially sends data to the programmable delay circuit; and rising edge setting means and falling edge setting means, respectively. (b) The pulse is connected to the rising edge setting means and the falling edge setting means, and has a rising edge and a falling edge respectively related to the timing of the rising edge and falling edge set by the both setting means. pulse forming means for forming; (2) A pulse train generator comprising the following (c) and (d). (c) a main memory circuit that stores pulse data regarding the level of the output pulse and sequentially outputs the pulse data by being driven by an input clock signal; and a main memory circuit that receives a signal related to the input clock signal as one input; an RZ circuit that takes the output of the input clock signal as another input, ANDs the two inputs and outputs the result; and an RZ circuit that is connected to the output of the RZ circuit and outputs the output of the RZ circuit with a time resolution shorter than the period of the input clock signal. a programmable delay circuit that causes a delay; and a programmable delay that stores delay data for setting a delay amount in the programmable delay circuit to a predetermined value, and that is driven by the input clock signal and sequentially sends the delay data to the programmable delay circuit. A memory circuit, and rising edge setting means and falling edge setting means, respectively. (d) being connected to the rising edge setting means and the falling edge setting means, and generating pulses having rising edges and falling edges respectively related to the timings of the rising edges and falling edges set by the both setting means; pulse forming means for forming;