JPS5895440A - Difference data compression system - Google Patents

Abstract

PURPOSE:To make high-speed data compression possible, by converting the difference between an input signal and a signal, which is obtained by delaying the input signal by the period of clocks, to a digital signal. CONSTITUTION:An input signal ei is applied to a correcting circuit 12 and a delay circuit 13. The delay time of the delay circuit 13 is set to a delay time t1 by which the signal is delayed through an AD converter 4, an adder 6, and a DA converter 3. The output ei of the delay circuit 13 and an output e0 of the DA converter 3 are applied to a differential amplifier 14 to obtain an error signal eAGC. The error signal eAGC is applied to the correcting circuit 12 to correct the magnitude of the input signal ei. A corrected input signal eA and a signal eA' obtained by delaying the signal eA by a time corresponding to one period of clicks 5, 10, and 11 are applied to a differential amplifier 2 to obtain a difference signal eD. This difference signal is applied to the AD converter 4 to obtain a digital signal ED. This digital signal ED is applied to the adder 6 and is added to an output EADD' of a forecaster 8 to obtain a forecasting signal EADD of the input signal ei. This forecasting signal EADD is applied to the DA converter 3 and is converted to the analog signal e0 and is applied to the differential amplifier 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential data compression method, which enables high-speed data compression by converting the difference signal between an input analog signal and an analog signal delayed by a certain period of time into a digital signal. The purpose is to provide a type data compression method.

Conventionally, ADi convertible devices have been used for converting analog signals such as video signals into digital signals in order to compensate for fluctuations in the time axis of VTR playback signals and for various other purposes. In order to reduce the number of bits of a digital signal converted by such an AD converter, there has conventionally been a differential data compression method that performs hybrid differential pulse code modulation (hereinafter referred to as rDPCMJ) as shown in FIG. In the same figure,
The analog signal e□ input from the input terminal 1 is supplied to the differential amplifier 2, where the analog signal e is supplied from the DA converter 6. (The analog signal e0 is an analog signal that enters the input terminal 1 one clock before the analog signal e1, and contains errors due to the AD converter 4 and transmission error, which will be described later.) and is converted into a difference signal eD. After AD
Power supply supplied to converter 4.

The AD converter 4 converts the difference signal eD into a digital signal ED of a predetermined number of bits using the clock signal supplied from the input terminal 5, and supplies this digital signal ED to the digital adder 6, while supplying the digital signal ED from the output terminal 7. Output. The digital adder 6 receives a digital signal ``ADD'' obtained by multiplying the sum of the digital signal ED and the digital signal ED up to one clock period before the digital signal E2D is supplied by a predetermined coefficient by a predictor 8. Perform the addition with
A digital signal EADD, which is the addition output signal, is supplied to the latch circuit 9 and the DA converter 5. The latch circuit 9 supplies the digital signal EADD to the predictor 8 after being delayed by one clock by the clock signal from the input terminal 10, and the DA converter 6 receives the supplied digital signal EADD.
After launching the DD using the clock signal supplied from the input terminal 11, it performs DA conversion and supplies this to the differential amplifier 2 as an analog signal e0 delayed by one clock from the analog signal e1 from the input terminal 1. , Here, when the number of bits of the digital signal ED outputted from the AD converter 4 is, for example, 6 bits, the AD converter 4 has a configuration as shown in FIG. In the figure, the difference signal e
D is compared with 7 (7-2'-1) types of reference signals by the comparator 4a, and the obtained 8 fIiSi('-> signal is supplied to the encoding circuit 4b ((), where it is converted into a 6-bit digital signal. The signal K is converted into f and is supplied to the latch circuit 4c, where the timing is aligned and output as a digital signal ED.The comparator 4a, the encoder circuit 4b, and the latch circuit 4C each receive a clock signal from the input terminal 5. The digital signal ED is supplied from the latch circuit 4c for each clock, but the analog signal ED is a mirror image signal and the frequency of the clock signal is approximately 11 MHz to 1 MHz.
If it is very high like 5MHZ, comparator 4 a + encoding l
1g circuit 4b.

Due to the AD conversion by the latch circuit 4C, the digital signal E is delayed by one clock or more from the difference signal +9D.

Therefore, the analog signal e is supplied from the DA converter 6 to the differential amplifier 2. Since the analog signal e□ supplied from the input terminal 1 is redder than the analog signal e□ by two or more clocks, high-speed data compression is impossible.

There was a drawback.

The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described with reference to FIG. 6 and subsequent figures.

FIG. 5 shows a block system diagram of one embodiment of the differential data compression method according to the present invention. In the figure, the same parts as in FIG. 1 are given the same reference numerals. In FIG. 5, an analog signal e1 input from the input terminal 1 is supplied to a correction circuit 12 and a delay circuit 15. The delay circuit 15 mainly includes A and D converters 4. Adder 6. When the signal is delayed by the DA converter 6, an equal delay time t is set, and the analog signal ei is delayed by the delay time t1 and is supplied to the differential amplifier 14 as an analog signal e'. The differential amplifier 14 receives this analog signal e/1 and the analog signal e/1 from the DA converter 6.
is delayed by a time t1 and is differentially amplified by the AD converter 4 and an analog signal e0 containing an error due to a transmission error to obtain an error signal e, which is supplied to the correction circuit 12. The correction circuit 12 is, for example, AG
The amplification degree of this AGC circuit is controlled by the error signal e to correct the analog signal e to produce an analog signal eA, and this analog signal eA is input to one input of the differential amplifier 2. Terminal and delay circuit 15. The delay circuit 15 inputs the delay time to the input terminal 5.10.
．． 11, and the analog signal eA is delayed by one clock to produce an analog signal e'. and supplies it to the other input terminal of the differential amplifier 2.

The differential amplifier 2 subtracts the analog signal eA from the analog signal e'□ delayed by one clock to obtain a difference signal eD. This difference signal e D It's AD converter 4
After being converted into a digital signal ED, it is output from the output terminal 7 and easily supplied to the adder B. Adder 6 is AD
The latch circuit 9 latches the sum of the digital signal ED supplied from the converter 4 and the digital signal ED up to one clock before this digital signal ED, and the predictor 8 multiplies it by a predetermined coefficient (for example, 0.90 to 0. 98) and the obtained digital signal E'ADD to obtain a digital signal "ADD" (approximately equal to the analog signal ei digitized after being spread over the establishment time), which is then added to the digital signal E'ADD obtained by the latch circuit 9. and supplied to the DA converter 5.D
A converter 5 receives digital signal EADD and 7 analog signal e.
. The signal is converted to VcK and supplied to the differential amplifier 14.

Here, the number of bits of the digital signal ED output from the AD converter 4 is n (n is a positive integer), and the number of bits of the digital signal EADD supplied to the DA converter 6 is m (mt is a positive integer). m), the maximum output of DA converter B is e. m
When aX is assumed, the maximum value of the error due to AD conversion of 1[[] (one clock) is 8omax/2 (m−n).

Also, the error allowed within the period of delay time t is the value obtained by multiplying the number of clocks within time t0 by eomax/2(!o-n), so conversely, the delay time t is 2(!on) of one clock period.
m−n) times or less.

In this way, the difference signal eD obtained by the differential amplifier 2 is based on the analog signal (IIA and the analog signal eI delayed by one clock), and the difference signal eD obtained by the differential amplifier 2 is generated by the analog signal (IIA) and the analog signal eI delayed by one clock.
Adder 6. Since the delay time due to DAf conversion er5 etc. is irrelevant, if the clock signal frequency is very high (like a video signal)
Even if C height<the delay time by the AD converter 4 is one clock or more, the W signal eD between the analog signals eA delayed by one clock is always obtained, and high-speed data compression is possible. In addition, AD converter 4. Adder 6. By DA converter °5 etc.! The analog signal ei from the delay circuit 13 and the analog signal e from the DA converter 3 are set equal to the delay time. In order to obtain the error signal e, this error signal G
O eAGO is an error generated during AD conversion, and this error signal e is supplied to the correction circuit 12 to control the next analog signal e□ delayed by time t GO to correct this error in real time.

Note that the correction circuit 12 is not an A()C circuit, but a difference 1: increase i that takes the difference between the analog signal e and the error signal e.
It may be an AGO hataki,
It is not limited to the above embodiments.

In addition, if the 5 analog signal e1 is a video signal, it is sufficient to periodically correct the sync tip level or pedestal level of the horizontal synchronization signal to a constant value during each horizontal erasing period. When making corrections, DA
Converter 3. Adder 6. Latch circuit 9#predictor 8. Delay circuit 13. The difference W and the amplifier 14 are not necessarily necessary and are not limited to the above embodiment.

As described above, the differential data compression method according to the present invention obtains a difference signal between an input analog signal and an analog signal obtained by delaying this input analog signal by a certain period of time, and converts the difference signal into a digital signal. Even if the signal is a video signal or the like and the clock frequency is very high, the difference signal is made up of the occasionally input analog signal and the analog signal delayed by one clock, so high-speed data compression is possible. The difference between the converted analog signal and the analog signal obtained by delaying the input analog signal by a predetermined time is determined as an error signal by adding the sum of the digital signals obtained by adding the above to the digital signal converted up to the previous time. Since the difference signal is obtained after correcting the input analog signal, it has the advantage of being able to correct errors that occur when converting the difference signal into a digital signal in real time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional differential data compression method, FIG. 2 is a block diagram 1 of the AD converter shown in FIG. 1, and FIG. 3 is a block diagram of an example of the differential data compression method of the present invention. 1
It is a block yarn M of an example, a figure. 1.5, 10.11... Input terminal, 2, 14... Differential amplifier, 5... DA converter, 4... AD converter,
6... Adder, 7... Output terminal, 8... Predictor,
9... Latch circuit, 12... Correction circuit, 13.15
...α extension circuit.

Claims (2)

[Claims] (1) A one-minute differential data compression method characterized by obtaining a difference signal between an input analog signal and an analog signal obtained by delaying the input analog signal by a certain period of time, and converting the difference signal into a digital signal. (2) Obtain a difference signal between an input analog signal and an analog signal obtained by delaying the input analog signal for a certain period of time, convert the difference signal into a digital signal, and add the digital signal to the previously converted digital signal. The difference between the analog signal converted from the sum of the digital signals obtained by the process and the analog signal obtained by delaying the input analog signal by a predetermined time is calculated as an error signal, and the input analog signal is corrected using the error signal. A differential data compression method characterized by obtaining the difference signal.