JPH04103222A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To improve the conversion accuracy by detecting a level of a horizontal synchronizing signal and allowing a subtractor circuit to correct a level of a digital video signal based on the result of detection. CONSTITUTION:A divider circuit 28 detects a mean value as to 7-samples of digital MUSE signals SD. The mean value is subtracted at a reference clamp level CL and latched based on a horizontal synchronizing pulse PHD and a difference from the mean level of the horizontal synchronizing signal is detected based on the reference clamp level CL. Thus, a fluctuation in the DC level for each horizontal scanning period of the digital MUSE signals SD is detected. The fluctuation is subtracted from the digital MUSE signals SD at a subtractor circuit 34 to correct the fluctuation in the DC level even when the DC level of the digital MUSE signals S, is fluctuated for a short period. Thus, the MUSE signal SMUSE is converted correctly to a digital signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog/digital conversion device, for example, M
U S E (nut it 1ple 5ubny
The present invention can be applied to a decoder based on the QUST SAMPL INGEN CODING method.

[Prior Art] Conventionally, in the MUSE system, a video signal is converted into a digital signal, band-compressed, and then converted into an analog signal and transmitted.

Correspondingly, a MUSE type decoder converts a received video signal (hereinafter referred to as a MUSE signal) into a digital signal and performs various signal processing.

Therefore, in order to correctly decode the muse signal on the decoder side, it is necessary to correctly convert the muse signal into a digital signal.

For this reason, in the MUSE type decoder, after holding the Muse signal at a predetermined reference clamp level, the Muse signal is converted into a digital signal so that the subsequent circuit can reliably decode the Muse signal.

Note that a clamp level instruction signal is inserted into the muse signal at a predetermined position in each field, and is used to control the reference clamp level.

Figure 3 shows the conventional analog/
1 shows the configuration of a digital conversion device 1. As shown in FIG. 3, in this analog/digital converter 1, the received muse signal S HUSE is applied to a low-pass filter circuit (LPF) 2, where the noise component is suppressed, and then output to the clamp circuit ¥84. do.

The clamp circuit 4 clamps the muse signal SHυS[ at a predetermined reference clamp level.

The analog/digital conversion circuit 6 converts the output signal of the clamp circuit 4 into a digital signal (hereinafter referred to as digital muse signal) SD, and then performs the following digital signal processing circuit F#!
(not shown).

Clamp level detection circuit 8 detects the value of the clamp level instruction signal in digital signal SD, and controls the reference clamp level of clamp circuit 4 based on the detection result.

As a result, the muse signal S)tU is adjusted so that the DC level of the digital muse signal SD becomes the reference clamp level.
This means that the signal level of sE has been corrected and analog/digital conversion has been performed with high accuracy.

That is, the clamp level detection circuit 8 adjusts the muse signal S so that the value of the converted clamp level instruction signal becomes 128 (the median value of the 8-bit dynamic range).
Correct the signal DC level of tUsE.

[Problems to be Solved by the Invention] By the way, in the muse signal SHl)SE, the DC level may fluctuate over a short period of one field period or less due to power supply noise or dispersal signal components.

Therefore, based on the clamp level instruction signal inserted in a predetermined period of each field, the muse signal SHU
When converting SE to a digital signal, muse signal S
There is a problem in that it is difficult to correctly convert MUSE into a digital signal. That is, conventionally, the DC level is reviewed once per field for a short period of time, and DC fluctuations within one field cannot be responded to. As a result, the accuracy of analog/digital conversion is reduced, and the accuracy of digital signal processing performed thereafter is also reduced.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide an analog/digital conversion device that can correctly convert an analog video signal into a digital signal even if DC fluctuation occurs between clamp level instruction signals. That is.

[Means for Solving the Problem] In order to solve the problem, the present invention includes a clamp circuit that clamps a video signal including a clamp level instruction signal in each field at a predetermined reference clamp level, and a clamp circuit that clamps a video signal including a clamp level instruction signal in each field. An analog/digital conversion circuit that converts the output signal of the circuit into a digital video signal, and a clamp level detection circuit that detects the signal level of the clamp level instruction signal in the digital video signal and controls the reference clamp level based on the detection result. and a subtraction circuit that subtracts predetermined correction data from the digital video signal, and detects the signal level of the horizontal synchronization signal of the digital video signal, and based on the detection result, the signal level of the horizontal synchronization signal reaches a predetermined reference level. A horizontal synchronization level detection circuit for setting correction data is provided.

In the present invention, in order to improve analog/digital conversion accuracy, the clamp circuit clamps the analog video signal to the reference clamp level, and then the analog/digital converter circuit performs conversion processing.At this time, the clamp level detection circuit The reference clamp level is controlled by detecting the level of the clamp level instruction signal after conversion to improve clamp accuracy.

In addition to these basic functions, the horizontal synchronization level detection circuit detects the level of the horizontal synchronization signal of the digital video signal, and based on this detection result, the subtraction circuit corrects the level of the digital video signal.

Therefore, it is possible to review the DC level for each field based on the clamp level instruction signal, and also to correct for DC fluctuations that occur during that time, making it possible to improve analog/digital conversion accuracy compared to the conventional method.

[Example] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG. 3 are given the same reference numerals, 20 indicates an analog/digital converter of this embodiment. In this embodiment, the digital muse signal SO
is not directly provided to a digital processing circuit (not shown), but is provided via a delay circuit 35 and a subtraction circuit 34. The subtraction circuit 34 is for correcting the DC level of the digital muse signal SD, and is supplied with correction data from the HD level detection circuit 822.

The HD level detection circuit 22 receives the digital muse signal S.
This is to detect the signal level of the horizontal synchronizing signal of D.

The HD level detection circuit 22 receives the digital muse signal SO.
is applied to a series connection circuit formed of six stages of delay circuits (D) 24A to 24F, and the digital muse signal SD and the output signal of each delay circuit 24A to 24F are added to an adder circuit 26.
Add from A to 26E.

Delay diagrams 824A to 24F are digital muse signals SD
The input signal is delayed and outputted with a clock cycle of , and seven consecutive samples of the digital muse signal SD are added together via the adder circuits 26A to 26E.

The division circuit 28 detects the average value of the seven samples of the digital muse signal SO by reducing the sum of the addition circuits 26A to 26E to 1/7.

The subtraction circuit 30 calculates a reference clamp level C from this average value.
By subtracting L, an error in the average value with respect to the reference clamp level CL is detected.

Latch times #! 32 is a timing generation circuit (not shown)
The output data of the subtraction circuit 30 is latched at the timing of the horizontal synchronization pulse PH[) input from This is also 128
) latches the error.

By the way, as shown in FIG. 2, the muse signal S HU
In the SE horizontal synchronization signal, the signal level is inverted for each line (Fig. 2 (A> and (B)), and in the m line, it rises from the first signal level to the second signal level. In the following m+1 line, the signal falls from the second signal level to the first signal level.

Utilizing this feature, the analog/digital converter 20 of this embodiment detects the intermediate signal level (128>) between the first and second signal levels, and the horizontal synchronization signal crosses this intermediate signal level. A clock signal is generated based on timing.

As a result, the muse signal S HUSE is sequentially sampled and converted into a digital muse signal, as shown by the black circles in FIG.

At this time, in the analog/digital converter 20,
The horizontal synchronization pulse PHD is generated so that the horizontal synchronization signal rises at the timing when the horizontal synchronization signal crosses this intermediate signal level.

Therefore, the 7-sample digital muse signal SD (
After subtracting the reference clamp level CL from the average value of SPn-3 to SPn+3, the error in this average value is latched based on the horizontal synchronizing pulse (corresponding to the sampling point SPn) PH[). It turns out.

By the way, when the digital muse signal is maintained at the correct signal level, the value SPO at the central sampling point in the horizontal synchronization period is 128 expressed in an 8-bit dynamic range, and the value SPO at the center sampling point in the horizontal synchronization period is 128, and the value SPO at the center sampling point in the horizontal synchronization period is 128, and
The value of Pn-3 to 5Pn-1 is 64 or 192, and the three sampling points S Pn+1 to S immediately after that are 64 or 192.
The value of Pn+3 is 192 or 64. As a result, when the digital muse signal is maintained at a correct signal level, the average level of seven sampling points centered on the intermediate sampling point of the horizontal synchronization signal becomes 128, which is equal to the reference clamp level CL.

Therefore, when the digital muse signal is maintained at the correct signal level, data with a value of 0 is latched into the latch circuit 832.

On the other hand, when the DC level fluctuates, the signal level corresponding to the fluctuation is stored in the latch circuit 32.

Therefore, if the signal level of the digital muse signal SD is changed by the signal level stored in the latch circuit 32 and output, even if the DC level of the digital muse signal SD fluctuates in a short cycle, the DC level will change. can be corrected. Accordingly, the muse signal SHU can be correctly converted into a digital signal and reliably decoded.

In order to execute such a correction operation, the latch circuit 32
outputs the latched data to the subtraction circuit 34 as correction data. Further, the delay circuit Fi@35 delays the digital muse signal SD outputted from the analog/digital conversion circuit 6 so as to be synchronized with the correction data from the HD level detection circuit #I22, and outputs the delayed signal to the subtraction circuit 34.

Thereby, the correction data can be sequentially subtracted and output from the digital muse signal SD via the subtraction circuit 34, and fluctuations in the DC level of the digital muse signal SO can be corrected every horizontal scanning period.

In the above configuration, analog muse signal 5) 1tl
sE is input to an analog/digital conversion circuit 6 via a low-pass filter circuit 2 and a clamp circuit 4 in order, and is converted there into a digital muse signal SO.

At this time, the muse signal 5HuSE is clamped by the clamp circuit 4 based on the detection result of the clamp level detection circuit 8 so that the value of the clamp level instruction signal in the digital muse signal SD becomes the reference clamp level, and then the digital muse signal Converted to SD.

The digital muse signal SD is transmitted to the HD level detection circuit 22.
, an added value of seven consecutive samples is obtained via the series connection circuit of the delay circuits 24A to 24F and the adding circuits 26A to 26E, and the added value is divided by 1/1 in the division circuit 828.
7, and the average value of the 7 samples of the digital muse signal SD is detected.

After this average value is subtracted by the reference clamp level CL, it is latched with reference to the horizontal synchronization pulse PHD, and thereby, a difference in the average level of the horizontal synchronization signal is detected with reference to the reference clamp level CL. Ru.

As a result, the amount of variation in the DC level of the digital muse signal SD for each horizontal scanning period is detected, and the amount of variation is subtracted from the digital muse signal SD in the subtraction cycle fI@34, so that the DC level of the digital muse signal SD is Even if the level fluctuates in a short period, the muse signal SMUSE can be correctly converted into a digital signal by correcting the fluctuation in the DC level.

According to the above configuration, after converting the muse signal into a digital signal using the clamp level instruction signal as a reference, the signal level is corrected so that the signal level of the horizontal synchronization signal of the digital signal becomes the reference clamp level. ,
It is possible to correctly convert a muse signal into a digital signal and reliably decode it.

In the above embodiment, a case was described in which a MUSE signal is converted into a digital MUSE signal by applying it to a MUSE method decoder, but it can also be applied when converting other video signals having a similar format into a digital signal. Can be widely applied.

[Effects of the Invention] As described above, according to the present invention, after a video signal is converted into a digital video signal based on the clamp level instruction signal inserted for each field, the signal level is converted based on the signal level of the horizontal synchronizing signal. In this way, the signal level of the digital video signal is corrected by adjusting the signal level of the digital video signal, so that not only the fluctuation of the DC level seen from field to field, but also the fluctuation of the DC level from horizontal scanning period to horizontal scanning period is absorbed, and the analog video signal is correctly converted into digital video. It can be converted into a signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an analog/digital conversion device according to the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, and FIG. 3 is a block diagram showing a conventional device. 4... Clamp circuit, 6... Analog/digital conversion circuit, 8... Clamp level detection circuit, 20
...Analog/digital converter, 22...
HD level detection circuit, 34... subtraction circuit.

Claims (1)

[Claims] A clamp circuit that clamps a video signal in which each field includes a clamp level instruction signal at a predetermined reference clamp level; and an analog/digital that converts the output signal of the clamp circuit into a digital video signal. a conversion circuit; a clamp level detection circuit that detects the signal level of the clamp level instruction signal in the digital video signal and controls the reference clamp level based on the detection result; and a clamp level detection circuit that controls the reference clamp level from the digital video signal; a subtraction circuit that detects the signal level of the horizontal synchronization signal of the digital video signal, and based on the detection result, adjusts the correction data so that the signal level of the horizontal synchronization signal becomes a predetermined reference level. An analog/digital conversion device comprising: a horizontal synchronization level detection circuit for setting.