JPS63278471A - Clamping circuit for video signal - Google Patents

Abstract

PURPOSE:To keep a prescribed clamping level without generating temperature change and secular change and applying adjustment and to prevent erroneous clamping from being generated even when a noise is mixed, by performing a clamping operation by a digital circuit. CONSTITUTION:An A/D conversion circuit 2 which converts an input video signal to a digital signal, a comparator 7 which inputs a digital video signal converted at the A/D conversion circuit 2 and compares it with a reference signal, a U/D counter circuit 6 which increases/decreases a number based on a binary up signal or down signal outputted from the comparator 7, and an adder circuit 3 which adds the output signal of the U/D counter circuit 6 on the digital signal are provided. The A/D conversion circuit 2 converts an analog input to a digital signal, and since all of the circuit behind the circuit are formed in the digital circuits, the clamping circuit is operated only digitally. In such a way, no temperature change and no secular change are generated, and the clamping circuit scarcely affected by a signal in which the noise is mixed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal clamp circuit, and more specifically, to a video signal clamp circuit for making the DC\L level of a video signal constant in a machine that handles TV signals such as a VTR. This relates to a clamp circuit.

[Summary of the invention]

The video signal clamp circuit of the present invention controls an up/down counter that operates only during the clamp period using a binary signal output from a reference data and digital video signal comparison circuit, and uses the counting output as a clamp error signal. This is added to the digital video signal to simplify the circuit configuration of the digital circuit and to prevent misclamping from occurring due to the t r 'l'' line.

[Conventional technology]

In general, a clamp circuit is essential for regenerating the DC potential of a video signal in a machine that handles TV signals, such as a VTR. has been proposed.

(a) The clamp circuit is constructed from analog circuits.

(b) The clamp error detection section is configured with a digital circuit, and the digital error signal is fed back to the analog section.

(C), which is composed entirely of digital circuits and resets errors every horizontal synchronization cycle.

etc.

However, these conventional methods have the following problems.

In the case of (a), in which the clamp circuit is constituted by an analog circuit, the clamp level fluctuates due to temperature changes and changes over time, so it is necessary to adjust the pedestal level. Furthermore, since it is an analog circuit, it is difficult to integrate it into an IC.

In addition, in the case where the clamp error detection section (b) is configured with a digital circuit and the digital error signal is fed back to the analog section, the circuit system becomes complicated due to the coexistence of analog circuits and digital circuits.
It is difficult to convert into C.

Therefore, in recent years, various types of Cc) constructed entirely of digital circuits have been proposed.

FIG. 3 shows an example of a clamp circuit (Japanese Unexamined Patent Publication No. 61-161080) constructed by such a digital circuit, in which 12 is an A/D converter and 14 is a horizontal synchronizing signal separation circuit. The synchronization signal separated by the horizontal synchronization separation circuit 14 is input to the averaging period detection circuit 15, and the output of the clear pulse CP is used to detect the 8-number signal in the back porch period of the digital video signal input to the digital averaging circuit 21. Minutes of digital data are averaged. This equalized digital data is then input to the next digital comparison circuit 22, where it is compared with the output of the data generation circuit 23 which outputs the reference Bedastal level data. Then, the difference output is held for one horizontal period by the latch pulse LP, and added to the digital video signal (DVl) in the next digital clamp circuit 24.

Note that 25 is a digital limiter circuit for preventing the digital video signal from exceeding a standard level.

[Problem that the invention seeks to solve]

This clamp circuit has the advantage that it can be integrated into an IC because the clamping operation is performed entirely by digital circuits, but since one circuit is complicated, there is a problem that the scale of the IC circuit increases.

Also, the DC level of the video signal to be clamped is f
The digital averaging circuit 21 detects the average of 8 samples worth of Bedastal level data, but since this average value level is cleared every horizontal period, it is a period during which noise etc. are averaged. If the focus is concentrated on the image, there is a problem that a series of momentary large misclamps occur, resulting in image deterioration.

In order to solve the problems with the conventional clamp circuit, the present invention is constructed entirely of digital circuits, and the I
The purpose of this invention is to provide a clamp circuit that can be easily made into a C, can be made compact, does not change with temperature or change over time, and is less affected by signals mixed with noise or the like.

[Means for solving problems]

In order to achieve the above object, the present invention provides a lamp circuit as follows. That is, the present invention provides an A/D conversion circuit that converts an input video signal into a digital signal, and an A/D conversion circuit that converts an input video signal into a digital signal.
A comparison circuit that inputs the digital video signal converted by the D conversion circuit and compares it with a reference signal, a U/D counter circuit that increases or decreases based on the binary up signal or down signal output from this comparison circuit, and this An addition circuit for adding the output signal of the U/D counter circuit to the digital signal is provided.

[Function] In the above configuration, the A/D conversion circuit converts the analog input into digital and f-digitals, and the subsequent circuits are also all digital circuits, so that the clamp circuit performs processing only digitally.

Further, the comparison circuit inputs the A/D converted digital signal and compares it with a reference signal, and outputs a down signal when this input signal is larger than the reference value of the reference signal, and vice versa. When is smaller than the reference value, an up signal is output.

The U/D counter circuit increases the count value for the up signal or the down signal output from the comparison circuit only when a clamp pulse is input, and increases the count value for the up signal and decreases the count value for the down signal. .

Therefore, the output of this U/D counter circuit becomes data indicating the fluctuation tendency of the DC level of the video signal, so by supplying this output data to the adder circuit to which the digital video signal is input, the digital video signal can be converted into a reference signal. It will be possible to clamp at the Bedastal level.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Regarding embodiments of the present invention, how the configuration of the present invention is actually embodied will be described below with reference to the drawings, along with its operation.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the figure, l is an input terminal -T, into which an analog signal AY such as a TV signal is input.

2 is an A/D conversion circuit which converts the analog video signal input into the input terminal -1 into AV, digital, and digital video signals D;
Convert to V.

The digital video signal DV converted by this A/D conversion circuit 2 is input to an addition circuit 3 having latch circuits 3a, 3c, and an adder 3b, and its Bedastar level is
It is clamped to the standard value. In addition, latch circuit 3
a and 3b are provided to set the timing of addition.

4.5 indicates a horizontal periodic signal separation circuit and a pulse generation circuit, respectively, and for the U/D counter 6 described later,
Clamp pulse CL that performs counting operation only for a predetermined period
form P.

The U/D counter 6 counts the clock signal CLK only during the period of the clamp pulse CLP, and its count output CD is supplied to the adder circuit 3.

Further, the comparator circuit 7 compares the digital video signal outputted from the adder circuit 3 with reference data Dr indicating a reference Bedastal level, and depending on the magnitude thereof, outputs an up signal pH or a down signal to the U/D counter 6. Provides signal PO.

Note that 8 indicates a D/A conversion circuit for converting into an analog signal, and a clamp-corrected analog video signal is obtained from an output terminal 9.

Since one embodiment of the video signal clamp circuit of the present invention has the circuit configuration described above, the input analog video signal AV is converted into, for example, an 8-bit digital video signal in the A/D conversion circuit 2. The signal is input to the adder circuit 3.

On the other hand, a horizontal synchronizing signal is extracted in the horizontal synchronizing signal separation circuit 4, and based on this extracted horizontal synchronizing signal, the horizontal synchronizing signal is detected during the Bedastar level period of the video signal (normally, as shown in FIG. 2, the back porch of the horizontal synchronizing signal is It is called part P.

) is output from the pulse generation circuit 5.

On the other hand, in the comparison circuit 7, the data (reference data) indicating the reference pedestal level is compared with the data of the digital video signal output from the adder circuit 3. For example, when this reference data Dr is high, , supplies the "H" level up signal P+1 to the U/D counter 6,
When the reference data Dr is low, the “L” level down signal F
D is supplied.

The U/D counter 6 receives this up or down signal PU.
The clock signal CLK is added or subtracted based on , or Po, but this counting operation is performed only during the period of the clamp pulse CLP, that is.

This is performed at the timing when a pedestal level signal is input to the comparator circuit 7.

Therefore, the count output CD of the U/D counter 6 increases every l horizontal period when the Bedastal level of the input video signal is lower than the reference data Dr;
When it is higher than r, it will decrease.

Then, this counting output CD is sequentially added to each sample data of the digital video signal in the adding circuit 3, so that the C component is added so that the pedestal level becomes the reference level.

Note that the U/D counter 6 holds its count output CD as shown in FIG. 2 except during the period of the clamp pulse CLP, and when the clamp operation is stable, the count output CD at this time n indicates approximately 0 data.

This digital clamp circuit has a type of low-pass filter characteristic in which the time constant is set by the frequency of the clock signal CLK supplied to the U/D counter 6, so that, for example, noise is superimposed on the input video signal. It is advantageous to be able to perform a precise operation such that the clamp level does not fluctuate rapidly even when the clamp level is being adjusted.

It is also possible to operate as a sync tip clamp circuit by generating the clamp pulse CLP only during the sync tip level period. Needless to say, it can also be used.

Furthermore, if the number of bits of the counting output of the U/D counter 6 is increased by one bit than the number of sampling bits of the video signal and the LSB of the counting output data is excluded from the addition data, a stable ramp operation that does not fluctuate at a minute level can be performed. can be set.

〔Effect of the invention〕

As explained above, in the video signal clamp circuit of the present invention, since the clamp operation is performed by a digital circuit, there is no temperature change or secular change, and a predetermined clamp level can be maintained without adjustment. Since it has low-pass filter characteristics, it has the effect of not causing misclamping even when noise or the like is mixed in.

Also, since it is composed of a simple digital basic circuit,
Not only can it be made into a single-chip IC, but it can also be incorporated into other digital video IC circuits, which has the advantage of reducing costs.

Furthermore, since the up/down counter is used, the circuit becomes simple, and the time constant of the clamp operation can be easily changed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a video signal clamp circuit showing an embodiment of the present invention, Fig. 2 is a waveform diagram of main parts, and Fig. 3 is a block diagram showing a conventional digital video clamp circuit. . In the figure, 2 is an A/D conversion circuit, 3 is an addition circuit, 4 is a horizontal synchronizing signal separation circuit, 5 is a pulse generation circuit, 6 is a U/D counter, and 7 is a comparison circuit. Video of this video, signal clamp 8 involved, mouthpiece 1, figure 2

Claims (1)

[Claims] An A/D conversion circuit that converts an input video signal into a digital signal, a comparison circuit that inputs the digital video signal converted by this A/D conversion circuit and compares it with a reference signal, and a binary signal output from this comparison circuit. The U/D counter circuit includes a U/D counter circuit that increases or decreases a count value according to A video signal clamp circuit characterized by: