JPS6072386A - Character multiplex signal extracting circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of signal processing in a later stage circuit, to digitalize entirely the extraction of character multiplex signal and to facilitate to form a integrated circuit by using the first and second A/D converters and doubling a sampling frequency. CONSTITUTION:An analog video signal VAS including character multiplex signal is added to A/D converters 14, 15 through an LPF buffer circuit, and the input signal is sampled at sampling clock phiS by the converter 14, and sampled at clock phiS by the converter 15. Digital signals DVS1, DVS2 from converters 14, 15 are added to a multiplexer 21, and the signal DVS1 is added to a synchronism detecting and timing pulse generating circuit 18 and a video signal processing circuit 27. The output of a multiplexer 31 is added to a latch circuit and sampled at sampling clock 2phiS, and sampling output is processed by an average value integrating circuit 33 and a coparator circuit 35. Thus, accuracy of signal processing in the later stage circuit is improved and the extraction of character multiplex signal is processed entirely digitally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a circuit for processing a character multiplex signal, and more particularly to a character multiplex signal extracting circuit capable of extracting a character signal using an all-digital circuit.

[Technical Background of the Invention and Problem No. 7] Conventionally, in a television receiver compatible with teletext broadcasting, a circuit for extracting a character signal from an incoming video signal is mainly composed of an analog circuit. For example, -fma
(fee: subcarrier frequency) clock generation means, video signal clamp system, timing pulse generation circuit for extracting character signals from the video signal, etc. are mainly analog circuits. For this reason, when integrating a character multiplex signal extraction circuit, two to three single analog ICs are required, whereas external components such as coils, resistors, and capacitors tend to require more components. .

Furthermore, such a character multiplex signal extraction circuit which is mainly based on analog circuits is expensive, and also has the problem of variations among offsets, which is an essential drawback of analog circuits.

τObjective of the invention] This invention was made in view of the above circumstances, and enables extraction of all digital character multiplexed signals, and
It is easy to implement, high performance can be achieved, and
It is an object of the present invention to provide a character multiplex signal extraction circuit that can improve cost and variation problems.

[Summary of the invention]

In this invention, an analog video signal is converted by first and second analog-to-digital converters a 14 r J 5, and clocks φS and B are used during this conversion. The converted digital video signal (DV, S, ?) (DVS2
) is introduced into the multiplexer 31 and converted into a digital video signal equivalent to that sampled with the clock 2φS. This doubles the sampling frequency, improves the signal processing accuracy in the subsequent circuit, and allows stable slice level setting and character multiplex signal extraction.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, which is a part that processes digital television signals and also extracts text multiplex signals. K' In Figure 1, an analog video signal (V
AS) is input to a band-limiting low-pass filter and buffer circuit 12 via an input terminal 11, and is band-limited according to the sampling theorem. The output of the low-pass filter and balance circuit 12 is input to a buffer amplifier 13. The output of this buffer amplifier 13 is input to a first analog-to-digital converter 14 and a second analog-to-digital converter 15.

The first analog-to-digital converter 14 samples the input signal using the sampling clock φS, and outputs a digital video signal (DV8J) converted into eight pits. Here, φS-4fm (5-4f: subcarrier frequency). On the other hand, the second analog-to-digital converter 15 samples the input video signal at a sampling clock n to obtain a 5-bit quantized signal (ovsz) for character multiplex signal processing. The sampling clock “T1 is
It is obtained by inverting the sampling clock φS generated by the clock generation circuit 16 using the inverter 17.

The digital video signal (ovsz) output from the first analog-to-digital converter 14 is guided to a subsequent circuit that performs digital video signal processing, synchronization processing, and the like.

First, the digital video signal (nvsl) is input to the synchronization detection and timing pulse generation circuit 18. The synchronization detection and timing pulse generation circuit 18 separates synchronization I from the incoming digital video signal (DV8J),
Horizontal synchronization detection signal (H8D) and vertical synchronization detection signal (V
SD) is output. The synchronization detection and timing pulse generation circuit 18 also includes a pedestal level detection pulse (PL).
D) and applies it to the pedestal clamp logic circuit 19. The synchronization detection and timing pulse generation circuit 18 also applies video signal processing pulses (VSP) as various timing pulses to the digital video signal processing door circuit 27. The phase locked loop (PLL) logic circuit 22 that performs phase manipulation receives a timing pulse (P
CT).

The pedestal clamp processing system will be explained.

The pedestal clamp logic circuit 19 detects the pedestal level of the digital video signal (DVS 1 ) as a digital value at the timing of the pedestal level detection pulse (PLO), compares it with the required reference data, and determines that the pedestal level is the reference level. This is a logic circuit that outputs error data that converges to . The error data has a 10-bit configuration and is analyzed by a digital-to-analog converter 20. The clamp voltage is applied to the buffer amplifier 1 via a resistor 21.
3 input end, analog video signal (VAS)
can be clamped.

Next, a carrier phase manipulation system will be explained. P.L.
The L logic circuit 22 detects the sampling phase of the burst from the digital video signal (DVSJ) according to the timing pulse (PCT), and selects 9 bits so that the sampling phase is 33° of the burst, that is, sampling is performed on the I axis and the Q axis. Outputs an error signal consisting of This error signal is converted into an analog voltage by a digital-to-analog converter 23, and the converted analog voltage is used as a control voltage for a voltage controlled crystal oscillator (VCXO) 24.

VCXOj 4 has a center frequency of 8fse (-2φS)
Oscillator with frequency and phase controlled oscillation output 2φ
Get S.

The oscillation output 2φS is guided to the clock generation circuit 16.

The clock generation circuit 16 generates the previous sampling clock -
Clock for extracting S1 character multiplexed signal (frequency - fac
) occurs.

FIG. 2 shows a time chart of various clocks generated by the clock generation circuit 16.

Clock φS (=4fnc) is clock 2φ5
(-=8fse).

can get. Furthermore, the above-mentioned pedestal clamp system,
The PLL logic system is disclosed in Japanese Patent Application Laid-Open No. 56-169478.
This method is also disclosed in Japanese Patent Application Laid-Open No. 57-73584.

Next, the digital video signal processing circuit 27 will be explained.

The digital video signal processing circuit 27 receives an 8-bit digital video signal (DVBI) and video signal processing pulses (vsp) at various timings. Examples of the video signal processing pulse (vsp) include a burst gate pulse and a color detection clock (for example, a clock indicating the I-axis phase). In the digital video signal processing circuit 22, predetermined processing regarding the luminance signal and one color signal is performed,
Primary color signals (RD, CD, BD) are obtained. Primary color signal R
D, CD, and BD are 9-bit signals each, which are introduced into three sets of digital-to-analog converters 28, and each is converted into an analog signal. Primary color analog signal (RA, GA
.

BA) is led to the color drive 41 circuit.

Next, the horizontal synchronous reproducing circuit 25 and the vertical synchronous reproducing circuit 22 will be further explained.

The horizontal synchronization reproducing circuit 25 receives the aforementioned horizontal synchronization detection signal (H8D) and horizontal flyback signal (FBS). The horizontal synchronization reproducing circuit 25 receives a clock φ5(-
4ft+) to obtain a horizontal scanning frequency output, the horizontal synchronous playback signal (HD)
This is a circuit that obtains the following. In this case, the horizontal synchronization reproducing circuit 26 is controlled so that the phase position of the horizontal synchronization detection signal (H8D) is at the center of the pulse section of the horizontal flyback signal (FBS). As a result, the horizontal counter in the horizontal synchronization reproducing circuit 25 can obtain various timing signals related to the horizontal scanning period, and can use this to generate a timing signal (TOV) for detecting the character multiplex signal position. I can do it.

The vertical synchronization regeneration circuit 26 receives the vertical synchronization detection signal (
V8D) is input. The vertical synchronization reproducing circuit 26 is configured, for example, by a counter that is reset by the vertical synchronization detection signal (V8D)K, counts down the horizontal synchronization reproduction signal, and generates the vertical synchronization □ reproduction signal (VD).

Further, the vertical synchronization reproducing circuit 26 can generate a timing signal (TOV) for detecting the superimposition position of the character multiplication signal.

The timing signals (TOH) and (TOY) mentioned above are
The signal is input to the character multiplex timing signal generation circuit 29. The character multiplex timing signal generation circuit 29 generates a timing signal (TJ
)(Tj).

Figure 3 shows the character multiplex signal (Dt) and timing signal (Dt) superimposed on the horizontal scanning period with the vertical blanking period.
A time chart of T1) and (T2) is shown. The character multiplex signal (Dt) includes a header part (ntt), a data part (ntt
), and a part of the header (Dtl) includes a 2-byte clock 2-in signal (CRI). The timing signal (T) is generated to correspond to the clock run-in signal (CRI) portion, and the timing signal (T2) is generated to correspond to the remaining portion excluding the clock run-in signal (CRI) portion. (SH) is a horizontal synchronization signal, and (BU) is a color burst signal. Although not shown in □ in FIG. 1, a clock φS is also input to the character multiplex timing signal generation circuit 29, and the timing signal (
T))(T2) is 1 and is generated in synchronization with the clock φS.

Next, referring back to FIG. 1, the system for digitally processing the character multiplex signal (see FIG. 3) superimposed on the analog video signal (VAS) will be explained.

As shown in FIG. 1, a first analog-to-digital converter 1
Of the 4 output lines, the quantized signal of the upper 5 bits (D
VS,? ) and the quantized signal (pvsz) from the second analog-to-digital converter 15 are input to the -multiplexer 31.

The multiplexer 31 receives the input quantized signal ('DVS
,? ) (DVS, ?) are mixed according to the timing of the CF check φs and latched by the latch circuit 32. The output of multiplexer 3 is 5 bits. As a latch clock for the latch circuit 32, a clock 2φS is used. Therefore, the output of the latch circuit 32 is 2φ5 (=8
fse) clock rate. Therefore, the latch output corresponds to a digital video signal sampled at a clock rate of 2φS, and the accuracy of digital processing at the subsequent stage is improved.

FIG. 4 specifically shows the multiplexer 31 and latch circuit 3. The multiplexer 31 outputs a quantized signal, that is, a digital video signal (DVSj) (DVS, ?
), there are two AND circuits and an OR circuit whose outputs are input. That is, the AND circuit (J
A) The combination of (JB) and OR circuit (JC) is the signal (DVS
2) This is a set in which the most significant bit of (DVSj) is input, and the most significant pit of each signal is connected to an AND circuit (Z A
) (IB) is input to one input terminal of each. Also, AND circuit (15A) (5B) and OR circuit (5C)
Group O is a group into which the least significant bit of the signal (DVS2) (DVS, 9) is input. The other parts have the same structure and will therefore be omitted. Next, the multiplex timing is set by the clock (φS). For example, the clock φS is applied to the other input terminal of the AND circuit (znj...(5B), and the AND circuit (IA
)...The other input terminal of (5A) has a clock (φS
) is inverted by the inverter (ID) (□)
is given. This relationship may be reversed. The output (5 bits) of multiplexer 31 is input to latch circuit 32. The 2' latch path 3 is composed of a 5-stage D-type flip-flop circuit corresponding to the number of input bits, and its latch clock is 2φS (-8fmc
) is used.

The output of the latch circuit 32 is input to the average value integration circuit 33.

Next, since it is necessary to set a slice level in order to extract a character multiplex signal superimposed on an analog video signal, digital processing for determining this slice level will be explained.

' First, the clock run-in signal will be explained with reference to FIG. 5. The clock run-in signal (CRI) includes phase information and slice level information that serve as a reference for data sampling. The period of the clock run-in signal (CRI) is 16 times the clock (-φS) of frequency ify+e.
(to aim for) individually.

Therefore, during this period, clock 2φ8 (= 8 fsc
), it corresponds to 16×5-80 pieces. The dashed line shown in FIG. 5 indicates the ideal slice level for the clock run-in signal (CRI), and if the slice level is set at this point, a signal with a duty of 50% can be obtained. In this embodiment, to detect the slice level, 6 bits (3 periods) of the clock run-in signal, that is, 30 periods of clock 2φS are used.

FIG. 6 specifically shows the average value integration circuit 33 for digitally detecting the slice level as described above. The average value integration circuit 33 receives various timing signals (Tll, T12.T) from the timing pulse generation circuit 34.
13) and data of the clock run-in signal (CRI) to detect data corresponding to the average level of the clock run-in signal (CRI). In Figure 6, (
J, 9A) is a 10-bit adder, (, 93B) is a 10-bit adder.
This is a bit latch circuit. The adder (JJA) adds the output of the latch circuit (33B) and the output from the latch circuit 32 described above, and inputs the result to the latch circuit 32. The latch operation is performed using a timing signal (Tll) (TMj
) according to the following. Timing signal (TJJ) (
T.J.? ) is shown in FIG. Furthermore, FIG. 7 shows the timing signal (T)) and the timing signal (TJ
J), clock 2φS is also shown. The timing pulse generation circuit 34 uses the clock 2φS and the timing signal (T1) to generate the timing signal (TJJ) (TJ
') ('rMJ) is generated. Latch circuit (,93B
) is released from the latched state during the high level period of the timing signal (TJJ).

The period of the timing signal (TJJ) corresponds to three periods of the clock run-in signal (CRI). by this,
The latch circuit (JJB) repeats the latch operation at the rising edge of the timing signal (T12) (the frequency is the same as the clock 2φS). As a result, as the output of the latch circuit 33, integral value data for three cycles of the clock run-in signal (CRI) is obtained. Therefore, the latch circuit (JJB)
The upper 5 bits of the output are the average level data of three cycles of the clock run-in signal.

The above average level value data obtained in one horizontal period is
The signal is input to an error integration circuit section consisting of an adder (33C) (33D) and a latch circuit (33E).

In this circuit section, average level value data is integrated with a predetermined time constant. Then, the upper five bits of the output of the latch circuit (33E) are taken out as data indicating the slice level, and this data is applied to one input terminal of the comparison circuit 35.

As shown in FIG. 1, the higher 5 bits signal (DVS3) from the analog-to-digital converter 14 is input to the other input terminal of the comparison circuit 35. The comparison circuit 35 is
The value (4) of the signal (DVS 3 ) and the slice level value 03) are compared, and when A2B, '1' is output, and when A<B, 'On' is output.

That is, this results in obtaining a digital character multiplex signal (Dt) stabilized by the slice level.

The digital character multiplex signal (Dt) is further input to a sampling phase determining circuit 36. The chimpling phase determining circuit 36 is a circuit for setting the phase of the sampling pulse for sampling the digital character multiplex signal (Dt) to the best phase. First, 36 sampling phase determination circuits take in data corresponding to three cycles of the clock run-in signal (CRI). Therefore, from the timing pulse generation circuit 34, the previous timing signal (T11) is generated.
A timing signal (TJZ) having the same phase as the clock run-in signal (CRI) is applied during this period. The sampling phase determining circuit 36 measures the data of the captured clock run-in signal (CRI) and determines the most appropriate phase of the sampling pulse (φt). The sampling frequency of the character multiplexed signal (old → It is set at a rate of 2φ5 (-8fac). FIG. 8 shows the relationship among the clock 2φS1 clock run-in signal (cR■), the timing signal (Tll), and the sampling pulse (φt).

The sampling phase determining circuit 36 includes, for example, a counter that detects the phase position of the sampling pulse φt (--fac). This counter is reset at the rising edge of the clock run-in signal (CRI), counts the clock 2φS, and is stopped at the rising edge of the sampling pulse φt. Here, if you judge whether the count value is larger than, smaller than, or equal to a predetermined value,
It can be determined whether the phase of the sampling pulse φt is appropriate. Based on the determination result, the output extraction stage of the shift register is determined, thereby making it possible to modify the phase of the sampling pulse φt.

Sunburi jig pulse (φt), timing signal (T2)
, the digital character multiplex signal (Dt) is input to a decoder circuit 37, where sampling of the character multiplex signal is performed.

The present invention is not limited to the above-mentioned embodiment, but the analog-to-digital converter 1 is used to extract a character multiplexed signal.
From 4.15, a 5-bit quantized signal was used, but from 4 to
If it is 6 bits, there is no practical problem. Further, although three cycles of the clock run-in signal were used to obtain the average value for setting the slice level, further improvement in performance is possible by using more cycles.

Furthermore, although the originally used digital television signal has 8 bits, there is no practical problem as long as it has 7 bits or more. Further, various embodiments of the multiplexer, latch circuit, and average value integration circuit are possible.

〔Effect of the invention〕

According to the present invention, a character multiplex signal can be extracted by digital processing, and the extraction accuracy is good. In this system, first and second analog-to-digital converters 14 and 15 are used to convert an analog video signal into a quantized signal. Then, the clock φ5 (-4f
aa) of opposite polarity to each other, and one converted output (digital video signal) is directly led to the video signal processing section. Next, the outputs of the first and second analog-to-digital converters 14 and 15 (5' bit in the embodiment) are led to a multiplexer 3 and are march-braxed to 2φS.
is guided to the latch circuit 32 at a clock rate of .

As a result, the digital video signal (character multiplex signal) is 2φ
This is equivalent to sampling and quantizing at a clock rate of S ("8fsa)".

This means that it is possible to improve the detection accuracy when calculating slice level data in the average value integrating circuit 33 at the next stage. = For accurate setting of rice level, please refer to the 6th
As explained in the figure, this is an important element for accurately sampling data. In order to meet these expectations, the present invention is configured to be able to quantize the clock run-in signal portion of a character multiplex signal at a clock rate of 2φS, which is sufficiently higher in frequency than the character signal band. be. On the other hand, in the analog-to-digital conversion 514.15, it is difficult to use the clock 2φS (-8f8e) with the current technology, but the clock φS (-41
sa), it can be easily realized.

Further, according to the present invention, a character multiplex signal extracting means with good performance can be easily incorporated into all digital television receivers, and the entire system can be integrated into an IC. Furthermore, the pulse generation means used for the original signal processing of the digital television signal can be shared, which is effective for simplifying the entire system and achieving accuracy in signal synchronization. Furthermore, this system is flexible depending on the signal processing method of digital television signals.

As described above, the present invention enables easy connection with a digital television receiver to perform character multiplex signal extraction, enables the entire system to be converted to a digital IC, and improves the offset and cost problems of the conventional analog system. Therefore, it is possible to provide a multi-character single signal extraction circuit which can realize high-precision sampling processing.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the character multiplex signal extraction circuit of the present invention, FIG. 2 is a signal waveform diagram shown to explain the operation of the clock generation circuit of FIG. 1, and FIG. Figure 1 is a signal waveform diagram shown to explain the operation of the character multiplex timing signal generation circuit, Figure 4 is a circuit diagram specifically showing the multiplexer and latch circuit section of Figure 1, and Figure 5 is a diagram showing the character multiplex timing signal generation circuit. A signal waveform diagram showing the clock run-in signal. Figure 6 is a circuit diagram specifically showing the average value integration circuit in Figure 1. Figure 7 is shown to explain the operation of the average value integration circuit in Figure 6. Circuit Diagram FIG. 8 is a signal waveform diagram shown for explaining the operation of the sampling phase determining circuit of FIG. 1. 14, J5...Analog-digital converter, 27...
Video signal processing circuit, 3... multiplexer, 3...
・2...Latch circuit, 33...Average value integration circuit, 3
4...Timing pulse generation circuit, 35...Comparison circuit, 36...Sampling position (eye determination circuit) Applicant's agent, patent attorney Takehiko Suzue

Claims (1)

[Claims] Means for obtaining a sampling clock φS (however, φ-4fee, f*a: f carrier frequency) and a clock 2φS twice this, and means for introducing an analog video signal including a character multiplex signal. , a first analog-to-digital converter to which the analog video signal is input and quantizes it into N bits (N is a positive integer) using the clock φS; M with inverted clock φS
a second analog-to-digital converter for quantizing into bits (N, where M is a positive integer); and at least the output of the first analog-to-digital converter is directed to a horizontal synchronization signal of the television receiver. means for generating a timing signal corresponding to at least a clock 2-in signal of the character multiplex signal by obtaining a predetermined timing pulse from a horizontal synchronization reproducing means for reproducing a horizontal synchronization signal and a superposition synchronization reproduction means for reproducing a vertical synchronization signal; The upper M bits of the N-pit output of the first analog-to-digital converter and the M-bit output of the second analog-to-digital converter, the clocks φS and 2φS are introduced, and as a result, the M bits sampled by the clock 2φS means for outputting a digital video signal including a character multiplexed signal of bits; a digital video signal sampled at the clock 2φS is input, and a timing signal corresponding to the clock run-in signal is input, and a slice level is set; A character multiplex signal extraction circuit comprising: an average value integrating means for outputting average value data; and a comparison means for comparing the average value data with a digital video signal and outputting the character multiplex signal. .