JP3043095B2 - Digital video signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing apparatus used for digital video equipment such as a digital VTR for HDTV, and more particularly to a serial / parallel conversion circuit for converting a digital video signal from serial to parallel.

[0002]

2. Description of the Related Art VT for HDTV (High Definition Television)
In R, digital signal processing that does not cause signal degradation compared to analog signal processing is often used. Along with this, video signal transmission between devices is desired to be transmitted by digital signals in addition to transmission by analog signals.

FIG. 10 is a block diagram showing a typical configuration of a recording signal processing system of a digital VTR for HDTV. An analog video input Y signal (luminance signal) and Pb and Pr signals (color signals) are A signals. / D converters 1, 2, 3 respectively convert digital signals into digital signals.
The signal is input to the multiplexer 5, and the digital Pb,
The Pr signal is combined into one system of P signal by the mixer 4 and then input to the multiplexer 6. On the other hand, the Y and P signals of the digital video input are input to multiplexers 5 and 6, respectively. The multiplexers 5 and 6 select one of a digital Y signal and a digital P signal obtained by converting an analog video input into a digital signal, and a digital Y signal and a digital P signal of the digital video input. 7 is input.

[0004] The serial-parallel conversion circuit 7 is a circuit for serial-parallel conversion of an input digital video signal (digital Y signal, digital P signal) to lower the bit rate. For example, if both the digital Y signal and the digital P signal are 8-bit parallel data with a word transmission rate of 74.25 Mbps, the serial-parallel conversion circuit 7 as a whole
By converting the data into parallel data of 8 bits × 8 channels, the bit rate is reduced to 1/4 of the sampling rate.
Down to 8.5625 Mbps.

[0005] After the digital video signal of eight channels obtained in this way is subjected to various processes required for recording in the digital signal processing circuit 8, the tape 1 is read by the magnetic head 11.
2 recorded. In this way, a digital video signal having a total bit rate of about 1.2 Gbps is divided into eight channels and recorded on a multi-track on the tape 12.

The clock generating circuit 9 generates a clock synchronized with the synchronizing signal by an external reference signal, a synchronizing signal in the Y signal of the analog video input, and a digital synchronizing signal output from the serial-parallel conversion circuit 7. This clock and a clock input in synchronization with the digital video input are selected by the multiplexer 10 and supplied to the serial-parallel conversion circuit 7.

Here, when recording a digital input video signal, in order to effectively use a tape, a period corresponding to a horizontal blanking period of an analog video signal is excluded from the composite video signal as shown in FIG. Only data of the valid video period (referred to as valid video data) is recorded. Therefore, as shown in FIG. 14, before and after the effective video data period, SAV (Start of Active Video data) and EAV
A reference signal called (End of Active Videodata) is inserted. These SAV signals and EAV signals are also used in the serial / parallel conversion circuit 7, and are also necessary for synchronizing the VTR with a digital input video signal (digital Y signal) during recording.

FIG. 11 shows an example of the configuration of the serial-parallel conversion circuit 7 according to the prior art, and FIGS. 12 and 13 are timing charts showing the operation thereof. The digital P signal and the digital Y signal are supplied to shift registers 900, 900, respectively.
901 performs serial / parallel conversion. Shift register 901
, Three words of the preamble are detected by the pattern detection circuit 902 and the latch 903, and b = FFh, c = 00h, d = 0 in hexadecimal notation.
When the pattern of 0h is detected, a preamble detection signal is output. Next, F, V, and H (the sixth, fifth, and fourth bits of the output data d of the shift register 901) of the fourth word are detected by the pattern detection circuits 904 to 908, and the fields FIELD1, FIELD2, and FIG. V, EAV,
Each signal of SAV is obtained. These signals are input to the synchronization generation circuit 911, and signals necessary for synchronization are generated.

The SAV signal is supplied to a clock frequency divider 909.
As a trigger pulse. In the clock divider 909, a clock synchronized with the phase of the digital input video signal and having a rate of 1/4 of the word transmission rate of the video signal is generated, and the output data of the shift register 901 is generated at the timing of the clock. By being latched by the latch 910, the parallel video data shown in FIG. 12 is obtained. On the other hand, for analog input video signals,
The analog trigger signal is supplied to the clock divider 909, and the parallel processing is performed in the same manner.

This conventional serial-parallel conversion circuit operates at the same speed as the word transmission rate (74.25 Mbps) of the digital video signal except for the synchronization generation circuit 911. To realize such high-speed processing, ECL is used as a circuit element.
(Emitter-coupled logic) elements are required. Currently, E
Only the SSL (small-scale integrated circuit) is realized as the CL integrated circuit, and the circuit must be configured using a large number of ECL integrated circuits and pull-down resistors. Therefore, the circuit scale of the serial-parallel conversion circuit becomes very large, and the power consumption increases accordingly.

[0011]

As described above, in the conventional serial-parallel conversion circuit, the circuit portion processes at the same speed as the word transmission rate of the digital video signal.
When handling a digital video signal having an extremely high word transmission rate such as a TV signal, a high-speed element such as an ECL element is required, and a circuit must be formed using a large number of ECL integrated circuits and pull-down resistors. There is a problem that the circuit scale becomes very large and the power consumption is large.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a digital video signal processing apparatus capable of performing serial-parallel conversion processing at a speed lower than the word transmission rate of a digital input video signal. Aim.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention uses n-phase clocks at a rate of 1 / n of the word transmission rate of a digital input video signal, and uses n consecutive clocks of the digital input video signal. Are sequentially latched one word at a time, and the latch outputs are simultaneously re-latched at an arbitrary one-phase clock timing of the n-phase clocks to obtain n-channel parallel data. The parallel data of n channels obtained by the means is converted to 1/1 / the word transmission rate synchronized with the digital input video signal.
conversion means for converting into n-channel parallel data having a bit rate of n.

[0014] More specifically, the conversion means, for example, n-1 of the n-channel parallel data obtained by the parallelization means.
Delay means for delaying the parallel data of the channel by one cycle of the n-phase clock; and first and second inserted before and after the effective video data period of the digital input video signal from the output data of the parallelization means and the delay means. Reference signal detection means for detecting a reference signal, data selection means for selecting n-channel parallel data from output data of the parallelization means and the delay means in accordance with the detection output of the reference signal detection means, and detection of the reference signal detection means A clock selecting means for selecting a one-phase clock from the n-phase clocks generated by the clock generating means in accordance with the output; and retiming output data of the data selecting means using the clock selected by the clock selecting means. An n-channel having a bit rate of 1 / n of a word transmission rate synchronized with a digital input video signal Constituted by the retiming means for obtaining parallel data.

[0015]

As described above, according to the present invention, the serial-to-parallel conversion processing is performed at a bit rate lower than the word transmission rate of the digital input video signal except for the generation of the n-phase clock. It can be composed of low-speed elements such as elements.

Further, by performing the processing while lowering the bit rate of the signal from the word transmission rate of the digital input video signal, it is possible to perform error correction using the protection bits when detecting the reference signal.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the serial-parallel conversion circuit 7 of FIG. 10 in a digital video signal processing device according to one embodiment of the present invention. FIGS. 2 to 5 are time charts for explaining the operation of FIG.

The serial-parallel conversion circuit shown in FIG. 1 has a word transmission rate of 74.25 Mbps, which is a digital input video signal.
A digital Y signal and a digital P signal composed of 8-bit parallel data are respectively converted to a bit rate (1 / 8.5625 Mbps) of 1 / n = 1/4 of the word transmission rate.
) To convert the data into parallel data of n = 4 channels. The serial / parallel conversion circuit includes a clock frequency divider 100, parallelization circuits 101 and 102, delay latches 103 and 104, a SAV / EAV detector 105, data selection multiplexers 106 and 107, a clock selection multiplexer 108, and a Latch for timing 1
09,110.

As shown in FIG. 2, the clock divider 100 has the same rate as the word transmission rate, that is, 74.25M.
Frequency of the original clock of 1/4 and the frequency of 18.56.
At 25 MHz, four-phase clocks φ1 to φ4 whose phases are shifted by one clock of the original clock are generated.

The digital Y signal and digital P signal are
The signals are input to parallel circuits 101 and 102, respectively. The parallelizing circuit 101 has four 8-bit latches 111 to 114
And one 32-bit latch 115, and 8
In the bit latches 111 to 114, the four-phase clock φ1
At the timing of φ4, n =
4 words are individually latched, and an 8-bit latch 11
3 to 5 (e, f, g,
h) is output to the 32-bit latch 115 by the four-phase clock φ.
An arbitrary one-phase clock from 1 to φ4 (in this example, φ
By re-latch simultaneously at the timing of 1), n
= 8-bit parallel data of 4 channels (a,
b, c, d).

Similarly, the parallelizing circuit 102 also includes four 8-bit latches 121 to 124 and one 32-bit latch 1
In the 8-bit latches 121 to 124, four consecutive words of the digital P signal are individually latched at the timing of the four-phase clocks φ1 to φ4. At the same time at the timing of clock φ1, thereby outputting 4-channel 8-bit parallel data.

The parallel circuits 101 and 102 output parallel data. Where VTR
When the power supply is turned on, the phase relationship of the four-phase clocks φ1 to φ4 differs with respect to the input digital Y signal and digital P signal, and becomes one of A and B in FIG. 3 and C and D in FIG. . Therefore, the contents of the data latched by the latches 115 and 125 of the parallelizing circuits 101 and 102 are also shown in FIGS. 3A and 3B and FIG. , D.

That is, depending on the state when the power is turned on, the parallel data output from the parallelizing circuits 101 and 102 is:
For example, it is not always synchronized with the digital input Y signal and the P signal in a predetermined phase relationship as shown in FIG. 3A, and has a phase relationship as shown in FIGS. 3B and 4C and 4D. There is also. In the case of a phase relationship such as B, C, and D, the phases of four-word data marked with a circle that constitute the SAV in the data output from the parallelization circuits 101 and 102 are not aligned. Therefore, the parallel data output from the parallelization circuits 101 and 102 are processed as follows so that the phases of the data of the four words constituting the SAV are aligned.

Of the parallel data a to d of n = 4 channels output from the parallelizing circuit 101, the parallel data b, c and d of n-1 = 3 channels are supplied to the delay latch 103 comprising a 24-bit latch. By being latched at the timing of the clock φ1, the signals are delayed by one cycle of the clocks φ1 to φ4, as indicated by b ', c', and d 'in FIGS. Similarly, of the four channels of parallel data output from the parallelizing circuit 102, three channels of parallel data are latched at the timing of the clock φ1 in the delay latch 104 composed of a 24-bit latch, respectively, so that the clocks φ1 to φ4 Is delayed by one cycle (one word).

Parallelizing circuit 101 and delay latch 10
The output data of No. 3 is input to the SAV / EAV detector 105, where the SAV signal (first reference signal) and the EAV signal (second reference signal) are detected.

Parallelizing circuit 101 and delay latch 10
3 is output to the data selection multiplexer 106.
And the parallelizing circuit 102 and the delay latch 10
Similarly, the output data of the multiplexer 4 for data selection is
07. These multiplexers 106, 1
07 selects n = 4 channels of parallel data among 2n−1 = 7 channels of parallel data input according to the multiplexer selection signals SA to SD output from the SAV / EAV detector 105.

That is, the data selection multiplexer 1
At 06, when the phase relationship between the parallel data output from the parallelization circuit 101 and the digital input Y signal is B in FIG. 3, d 'delayed by one word is selected instead of d,
In the case of C in FIG. 4, c 'and d' delayed by one word are selected instead of c and d, and in the case of D in FIG. 4, one word is delayed instead of b, c and d. B ', c',
d 'is selected. Data selection multiplexer 107
However, data is similarly selected according to the phase relationship.
In this manner, in any of the cases A to D, the parallel data in which the phases of the data of the four words constituting the SAV are aligned are output from the data selection multiplexers 106 and 107.

The clock selection multiplexer 108 includes:
According to the multiplexer selection signals SA to SD from the SAV / EAV detector 105, a one-phase clock (hereinafter, referred to as １ ／ clock) is selected from the four-phase clocks φ1 to φ4 generated by the clock frequency divider 100.

Data selection multiplexers 106 and 10
The output data of No. 7 is input to the retiming latches 109 and 110 composed of 32-bit latches, and is latched at the timing of 1/4 clock from the clock selection multiplexer 108. Thus, the retiming latches 109 and 110 synchronize with the digital Y signal and digital P signal input to the serial / parallel conversion circuit, respectively, and have a data rate of 18.5625 Mbps.
= Digital Y signal and digital P signal composed of 8-bit parallel data of 4 channels, that is, C shown in FIG.
The parallel video data of eight channels H1 to CH8 is output.

Note that the SAV / EAV detector 105 also outputs an FVH detection signal, and the FVH retiming circuit 2
At 01, retiming is performed by the 1/4 clock from the clock selecting multiplexer 108. The retimed FVH signal is supplied to the synchronization generation circuit 202, and a necessary digital synchronization signal is generated by, for example, the clock generation circuit 9 in FIG.

Next, the configuration of each unit in FIG. 1 will be described in detail. FIG. 6 is a block diagram showing details of the SAV / EAV detector 105, and includes preamble detectors 300 to 30.
3, 1-bit error correction data generation / 2-bit error detectors 304 to 307, 1-bit error correctors 308 to 311,
It comprises FVH discriminators 312 to 315, latches 316 to 319, and a selection signal latch 320.

As shown in FIG. 7, the preamble detectors 300 to 303 are logic circuit blocks 500 to 50, respectively.
It is configured by a 2- and 3-input AND circuit 512, and detects a 3-word preamble as shown in [Table 1]. The logic circuit blocks 500 to 502 have the same configuration, and each has eight 2-input EX-ORs (exclusive OR).
It comprises circuits 503 to 510 and an 8-input AND circuit 511. Each of the preamble detectors 300 to 303 outputs a preamble detection signal when a combination of input 3-word 8-bit data is FFh, 00h, and 00h in hexadecimal notation. Note that the EX-OR circuits 503 to 5
Input Dn (n = 0 to 7) which is not the data input of 10
Is fixed to “H” in the logic circuit block that detects FFh and “L” in the logic circuit block that detects 00h.
It is fixed to.

[0033]

[Table 1]

1-bit error correction data generation / 2-bit error detectors 304 to 307, 1-bit error correctors 308 to 307
Reference numeral 311 denotes F, F, of the fourth word (timing signal) input after the preamble as shown in [Table 2].
For V and H (sixth, fifth, and fourth bits), 1-bit error correction data is generated, 2-bit errors are detected, and 1-bit errors are corrected using the protection bits P0 to P3.
As shown in Table 1, F is a timing signal that is "0" in the first field, "1" in the second field, V is "1" in the vertical flyback period, and "0" in other periods. Is a timing signal which becomes "0" in SAV and "1" in EAV during the horizontal flyback period.

[0035]

[Table 2]

The 1-bit error correctors 308 to 311
It is composed of an X-OR circuit. Outputs of the one-bit error correctors 308 to 311 are output from FVH discriminators 312 to 31.
5 and the fourth word F, V, H (sixth, fifth, fifth)
4th bit) is identified. The identified F, V, H are latched by the latches 316 to 319 at the timing of the clock φ1, and the SAV detection signals SAV-A to SAV-D shown in A and B of FIG. 3 and C and D of FIG. Is output. SAV detection signal SA from latches 316-319
VA to SAV-D are supplied to the selection signal latch 320 and are converted into DC level multiplexer selection signals SA to SD.

As shown in FIG. 8, the selection signal latch 320 includes RS flip-flops 600 to 6 for latching the SAV detection signals SAV-A to SAV-D, respectively.
03, and OR circuits 604 to 607. The SAV detection signals SAV-A to SAV-D are flip-flop 600
603, and the outputs of the OR circuits 604 to 607 are input to the reset terminal R of the flip-flop 600. OR circuits 604 to 607
When any one of the SAV detection signals SAV-A to SAV-D is detected, it is provided to reset flip-flops other than the flip-flop for latching the SAV detection signal. Thus, the DC-level multiplexer selection signals SA to SD are selectively output from the flip-flops 600 to 603.

The multiplexer selection signals SA to SD are supplied to the data selection multiplexers 106 and 107 in FIG.
And the clock selection multiplexer 108. The clock selection multiplexer 108 includes NAND circuits 700 to 704 as shown in FIG. 9 and selects one of the four-phase clocks φ1 to φ4 according to the state of the multiplexer selection signals SA to SD. The data selection multiplexers 106 and 107 are also basically the clock selection multiplexers 10 only by increasing the number of inputs.
8 has the same configuration as that of FIG.

For example, when the multiplexer selection signal SD is on (“H”), the clock selection multiplexer 1
08, the clock φ2 is selected, and in the data selection multiplexer 106, b ', c', d ',
It is selected as the parallel Y signal data output of H1, CH2, CH and CH4.

[Table 3] shows the multiplexer selection signal SA
To SD, the clocks φ1 to φ4 selected by the data selection multiplexer 106 and the clock selection multiplexer 108, and the parallel Y signal data output.

[0041]

[Table 3] Note that, also in the data selection multiplexer 107,
The parallel P signal data output is selected in a similar manner.

The clock selected by the clock selection multiplexer 108 is supplied to the retiming latches 109 and 1.
10 and supplied to the FVH retiming circuit 201. Thereby, the parallel video data (parallel Y signal data and parallel P signal data) and the SAV detection signal are retimed as shown in FIG. With this retiming,
Four-phase clock φ1 output from clock frequency divider 100
Even if the phase relationship between .phi.4 and the digital input video signal (digital Y signal and digital P signal) is different each time the power is turned on, the digital input video signal and the parallel video signal data can be synchronized, and Conversion is performed.

In the serial / parallel conversion circuit of FIG. 1 described above, except for the clock frequency divider 100, the word transmission rate (74.25 Mbps) of the digital input video signal is one.
The processing is performed at a bit rate of (18.5625 Mbps). Therefore, most of the serial-parallel conversion circuit
It can be configured by using a low-speed element such as an S element, and it is easy to implement an LSI.

[0044]

According to the present invention, most of the serial-parallel conversion processing can be performed at a bit rate lower than the word transmission rate of the digital input video signal. Therefore, most of the serial-parallel conversion circuit is compared with the ECL element,
The present invention can be realized by using an OS element or the like, which is advantageous for an LSI and can greatly reduce power consumption.

Further, by performing processing by lowering the bit rate of the signal from the word transmission rate of the digital input video signal, detection of reference signals such as SAV and EAV necessary for serial-parallel conversion can be corrected by using error correction using protection bits. And can be performed with high reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial-parallel conversion circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the clock divider in FIG. 1;

FIG. 3 is a time chart showing a SAV signal detection operation.

FIG. 4 is a time chart showing a SAV signal detection operation.

FIG. 5 is a time chart showing a relationship between a digital input video signal and parallel video data in FIG. 1;

FIG. 6 is a block diagram showing details of a SAV / EAV detector in FIG. 1;

FIG. 7 is a block diagram showing details of a preamble detector in FIG. 6;

FIG. 8 is a block diagram showing details of a selection signal latch in FIG. 6;

FIG. 9 is a block diagram showing details of a clock selection multiplexer in FIG. 1;

FIG. 10 is a block diagram of a digital video signal processing device of a recording signal processing system of a digital VTR for HDTV.

FIG. 11 is a block diagram of a conventional serial-parallel conversion circuit.

FIG. 12 is a time chart illustrating the operation of the serial-parallel conversion circuit in FIG. 11;

FIG. 13 is a time chart showing a relationship between an analog composite video signal and various timing signals.

FIG. 14 is a diagram showing the contents of a video signal section of the bit parallel interface.

[Explanation of symbols]

 Reference Signs List 100: Clock divider 101, 102: Parallel circuit 103, 104: Delay latch 105: SAV / EAV detector 106, 107: Data selection multiplexer 108: Clock selection multiplexer 109, 110: Retiming latch 111 ... 115, 121-125 ... Latch for parallelization

Claims (2)

(57) [Claims] A bit-parallel digital input video signal input at a predetermined word transmission rate is converted into parallel data of n channels each having a bit rate of 1 / n (n is an arbitrary integer) of the word transmission rate. A clock generating means for generating an n-phase clock having a rate of 1 / n of the word transmission rate, and using the n-phase clock generated by the clock generating means to generate the digital input signal. The n successive words of the video signal are individually latched one by one in order, and the latch outputs are simultaneously re-latched at the timing of any one of the n-phase clocks to obtain n-channel parallel data. Means for converting the n-channel parallel data obtained by the parallelizing means into words synchronized with the digital input video signal. Digital video signal processing apparatus characterized by comprising a conversion means for converting the parallel data of n channels with a bit rate of 1 / n of the transmission rate. 2. A bit-parallel digital input video signal input at a predetermined word transmission rate is converted into n-channel parallel data having a bit rate of 1 / n (n is an arbitrary integer) of the word transmission rate. A clock generating means for generating an n-phase clock having a rate of 1 / n of the word transmission rate, and using the n-phase clock generated by the clock generating means to generate the digital input signal. The n successive words of the video signal are individually latched one by one in order, and the latch outputs are simultaneously re-latched at the timing of any one of the n-phase clocks to obtain n-channel parallel data. Means for converting the n-1 channel parallel data of the n channel parallel data obtained by the Delay means for delaying one cycle of the clock, and first and second reference signals inserted before and after an effective video data period of the digital input video signal from output data of the parallelization means and the delay means. Reference signal detecting means for detecting, data selecting means for selecting parallel data of n channels from output data of the parallelizing means and the delay means in accordance with a detection output of the reference signal detecting means, and detecting of the reference signal detecting means Clock selecting means for selecting a one-phase clock from n-phase clocks generated by the clock generating means in accordance with the output; and retiming output data of the data selecting means using the clock selected by the clock selecting means. Thus, n having a bit rate of 1 / n of the word transmission rate synchronized with the digital input video signal Digital video signal processing apparatus characterized by comprising a retiming means for obtaining a parallel data Yaneru.