JP3001959B2 - Synchronous signal generating method and synchronous signal generating device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method and an apparatus for generating a ternary synchronization signal for a high definition television receiver.

[Prior art] Conventionally, for example, an MU based on sample value analog transmission
In the high definition television of the SE system, it is necessary to accurately reproduce the phase of the resampled clock in order to prevent color shift and resolution degradation due to the influence of the transmission path, and a ternary synchronization signal is used as a synchronization signal. .

Taking the case of a MUSE decoder as an example of a ternary synchronization signal synchronizing signal generator, a horizontal (line) counter that operates with a clock of 16.2 MHz and a vertical (frame) counter that operates with a line cycle are provided. The output of the counter is decoded by a ROM to extract 2-bit data, and the D / A conversion is performed as it is to obtain a ternary synchronization signal.

As for the standard of the ternary synchronization signal, an example can be found in the studio standard BTA S-001 in Hi-Vision in Japan, but the above generator satisfies the standard,
It did not apply to the specification of the waveform at all.
In order to satisfy the definition of the waveform based on the signal from the synchronous signal generator, it is necessary to add a large-scale and wide-band analog filter. Moreover, since the standard at the point of the level change of the BTA S-001 is not fixed at the slew rate, but stipulates that the time required for the level change is fixed, in an analog filter, for example, a negative level is used. There is a problem that the time required to change the level differs between the change to the 0 level and the change from the negative level to the positive level.

In addition, other commercial high-definition television devices require a counter that operates with a high-frequency clock and a high-speed, large-capacity ROM accordingly.

[Problems to be Solved by the Invention] The conventional synchronizing signal generator of a high-definition television receiver has a problem that a large-scale and high-speed operation circuit is required to obtain a waveform satisfying the standard. Had.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a synchronization signal generator for generating a high-precision ternary synchronization signal with a small-scale circuit.

[Means for Solving the Problems] Accordingly, in order to achieve the above object, a first aspect of the present invention is a method for generating a ternary synchronization signal from a demodulated high-definition television signal. The first of T
The sampling rate of the ternary synchronization signal having the quantization bit number A generated using the clock frequency is converted by a second clock frequency of n times (n is a rational number greater than 1) the period T, and the quantization is performed. The data is interpolated m times the number of bits A (m is a rational number greater than 1).

According to a second aspect of the present invention, there is provided a synchronizing signal generator for generating a ternary synchronizing signal of a high-definition television receiver. A counter, a vertical counter that receives vertical load data and a vertical synchronization signal and operates at a second clock frequency of a horizontal cycle output from the horizontal counter, and inputs the outputs of the horizontal counter and the vertical counter, A decoder for decoding into a ternary synchronization signal having a first clock frequency and the number of quantization bits A;
A sampling rate conversion circuit for interpolating data at a third clock frequency n times (n is a rational number greater than 1) and m times the quantization bit number A (m is a rational number greater than 1); A D / A converter for inputting an output from the rate conversion circuit and converting the output to an analog signal.

According to the present invention, a horizontal counter and a vertical counter,
A decoder decodes a change in the ternary synchronization signal at a low clock frequency and a low quantization bit number necessary to satisfy the timing standard of the ternary synchronization signal of the high definition television, and converts the signal into a sampling rate conversion circuit. By interpolating the data with a higher clock frequency and a higher quantization bit number, a ternary synchronization signal that satisfies the standard (waveform standard) for the time required for the level change of the ternary synchronization signal is obtained. Therefore, a high-precision ternary synchronization signal that satisfies the timing and waveform standards can be generated with a small-scale circuit configuration.

[Embodiment] Next, a case where the present invention is applied to a MUSE decoder will be described with reference to FIGS.

FIG. 1 is a block diagram of a synchronizing signal generator according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each section related to FIG.

In the figure, reference numeral 1 denotes a 9-bit horizontal (line) counter, which is 1 based on a horizontal synchronizing signal (hereinafter abbreviated as HD signal).
It counts with the line cycle. Numeral 2 denotes a 6-bit vertical (field) counter, which starts counting when receiving a vertical synchronizing signal (hereinafter abbreviated as VD signal), and uses only one pulse per line from the line counter 1 as a clock during a vertical blanking period. Count. Reference numeral 3 denotes a decoder for decoding 9-bit data from the line counter 1, 6-bit data from the field counter 2, and a 2-bit ternary synchronization signal from the field index FI. Reference numeral 4 denotes a sampling rate conversion circuit for converting a 2-bit signal sampled at 16.2 MHz from the decoder 3 to a triple sampling rate of 48.6 MHz and a quantization bit number to 4 bits. Reference numeral 5 denotes a D / A conversion circuit for converting a digital signal from the sampling rate conversion circuit 4 into an analog signal. Reference numeral 6 denotes a low-pass filter for smoothing the signal from the D / A conversion circuit 5.

In the synchronous signal generator configured as described above, the line counter 1 is reset when the count value reaches 479 because the number of samples per line at 16.2 MHz is 480, and furthermore, the position of the synchronous signal is arbitrarily set. 9-bit horizontal (H) load data from 0 to 479 is input so that it can be changed, and loaded by the HD signal.

Field counter 2 is similar to line counter 1
The vertical (V) load data is loaded by the VD signal. However, since the vertical variable amount of the synchronization signal is not necessary as much as the horizontal direction, the 4-bit V load data of 0 to 15 is used, and the count range of the counter is also vertical. Since it is sufficient to cover the blanking period, a 6-bit counter is used, and when the vertical blanking period ends, the counting operation is stopped until the next VD signal is input.

The 9-bit horizontal and 6-bit vertical data output in this way are different in the decoder 3 because the timing of the VD signal is different between the odd field and the even field in the decoder 3.
The field is determined based on the level of the field index FI, and is decoded into a two-bit ternary synchronization signal having three values of 0, 1, and 2 shown in FIG.

This 2-bit ternary synchronization signal is sent to the sampling rate conversion circuit 4, and the sampling rate conversion circuit 4
When the sampling rate is tripled from 6.2 MHz to 48.6 MHz, the interpolation data shown in FIG. 2 is generated and output as a 4-bit ternary synchronization signal having a value of 0 to 8.

The 4-bit ternary synchronization signal is converted by the D / A conversion circuit 5 into a second
The signal is converted into an analog signal shown in FIG. 11 and passed through the low-pass filter 6 to obtain a smooth ternary synchronization signal shown in 12 in FIG.

When the field counter 2 is a 9-bit counter and a full-field counter for switching between 562 and 563 counts for each field or an 11-bit frame counter, the size of the circuit is large, but the design of the decoder 3 is not sufficient. It's easy.

[Effects of the Invention] As described above, the synchronization signal generating apparatus of the present invention
Choose a low enough clock frequency to satisfy the timing standard of the ternary synchronization signal,
A signal having a minimum quantization bit number required to indicate a ternary level is generated, and this signal is sampled at a sampling rate and a quantum level required to satisfy a standard for a waveform such as a slope at a transition point of a ternary synchronization signal. By converting the signal into a signal having a digitized number of bits, there is an excellent effect that a high-precision ternary synchronization signal satisfying the BTAS-001 standard can be generated with a small circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the MUSE decoder of the device of the present invention. FIG. 2 is a signal waveform diagram of each part related to FIG. 1 ... horizontal (line) counter, 2 ... vertical (field) counter, 3 ... decoder, 4 ... sampling rate conversion circuit, 5 ... D / A conversion circuit, 6 ... low-pass filter, 7 ... 1 clock frequency (16.2 MHz clock), 8... Ternary synchronization signal with quantization bit number A (2 bits), 9 second clock frequency (48.6 MHz clock), 10 quantization bit number A M times (4 bits) of 3
Value synchronization signal, 11: D / A conversion circuit output, 12: Low-pass filter output.

Claims (2)

(57) [Claims] 1. A method for generating a ternary synchronization signal from a demodulated high-definition television signal, comprising: a ternary synchronization of a quantization bit number A generated using a first clock frequency of a period T. The signal is sampled at a second clock frequency that is n times (n is a rational number greater than 1) the period T, and is m times the number of quantization bits A (m
Wherein a data ratio is a rational number greater than 1. 2. A synchronization signal generator for generating a ternary synchronization signal for a high-definition television receiver, comprising: a horizontal counter which receives horizontal load data and a horizontal synchronization signal and operates at a first clock frequency of a period T. A vertical counter which receives vertical load data and a vertical synchronization signal and operates at a second clock frequency of a horizontal cycle output from the horizontal counter; and inputs the outputs of the horizontal counter and the vertical counter to At a clock frequency of 1 and a quantization bit number A of 3
A decoder for decoding into a value synchronization signal, and a ternary synchronization signal from the decoder,
A sampling rate conversion circuit for interpolating data at a third clock frequency twice (n is a rational number greater than 1) and m times the quantization bit number A (m is a rational number greater than 1); A synchronizing signal generator, comprising: a D / A converter that inputs an output from a circuit and converts the output into an analog signal.