JPS6016769A - Pedestal clamp circuit - Google Patents

Abstract

PURPOSE:To obtain a clamp circuit omitting a D/A converter for generating clamp signal by converting an error level obtained through the comparison of a pedestal level extracted from a digital video signal with a reference level into a PWM signal. CONSTITUTION:A digital video signal outputted from an A/D converter 105 is fed to a synchronism detection timing generating circuit 109. A timing signal 111 generated at the circuit 109 is fed to a pedestal extracting circuit 220, from which a pedestal level signal 221 is outputted. The pedestal level signal is fed to an error operating circuit 224 together with a reference level signal 223 and a difference is obtained at the circuit 224. After an error signal 225 is subject to digital integration, the result is fed to a PWM generating circuit 228 and converted into a PWM clamp signal 229. This PWM clamp siganl is smoothed by an analog integration circuit 230 and an analog clamp signal 103 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The invention of Hitoshi relates to a digital television receiver that performs video signal processing digitally, and relates to a bedside clamp circuit for a digital television receiver suitable for a bamboo VC11 circuit.

[Technical background of the invention and its problems]

As is well known, all signal processing in conventional television receivers is performed by analog signal processing.
In particular, regarding analog signal processing after the video stage, there were the following problems that should be improved. In other words, this is a problem caused by processing on the time axis, which is a general weakness of analog signal processing in terms of performance. Specifically, the ability to separate luminance signals and chromaticity signals that appear on the screen as cross-color/dot interference, and the ability to improve image quality in each area.

Synchronization performance, etc. On the other hand, when converting such an analog signal processing circuit after the video stage into an IC.

Disadvantages: There are many adjustment points and the cost is high.
5th cup occurs.

So, to solve the above problems.

It is being considered to make the signal processing and synchronization processing after the video stage all digital.

In such a so-called digital television receiving branch (e), the video signal is transferred to an analog/digital converter (also referred to as
When converting to a digital circuit using an A/D converter (referred to as an A/D converter), must the DC component of the television signal be regenerated to match the dynamic range of the A/D converter? In order to regenerate the DC component of the
An analog video (1) hard destal flang that controls the direct current component of the bow has been developed to keep the l level at a predetermined value. 1985-+24 (Publication No. 180 VC failure)

f, -; The figure shows a conventional destination frang circuit.
The analog video signal 101, which is 1, J1), is supplied to the non-converting adder circuit 02, and in this analog adder circuit 102, a clamp signal 103 is added to control the DC component.

The output signal 104 of this analog adder circuit 102 is an A/D
is supplied to converter 105. This A/D converter 105 is supplied with a sampling signal 107 having a frequency four times that of the color subcarrier.
The annotated video signal 104 is sampled into, for example, an 8-bit digital video signal 106. All the circuits of this digital video signal 106d are supplied to the digital signal processing circuit 12B in the digital circuit unit 10BVC composed of digital circuits.

The signal is supplied to the synchronization detection timing generation circuit 109 and the two-amp signal generation circuit IJO. Of these, the synchronization detection timing generation circuit 109 detects a synchronization pulse signal from the digital video signal 106, and generates various timing signals 111, 114°xzo, xzJf according to the detected synchronization pulse signal. Also.

l'lll nl' clan 1-1 generation circuit 110
Timing 4f: The basic level of the digital video signal 10G is detected according to 4th Ill, and when this pedicle level becomes a predetermined value, the ramp jLI W:lI (F; fj 7 'I Z This Franz' control signal yi2t
rJ Digicle/Analog Laboratories: < u, −+−,
I)/A converter) 113 A]) fed No.1. Converted to analog Hakugo. But-C, this I'll/
The analog signal 13 and the clamp signal 103 are outputted from the A converter 113.

This clamp signal 103 causes the analog bidet 71 to be clamped.

1st stage detection timing generation circuit 1093
The timing signal 114 that is output as 1' is output by PLL (P
hase Locked Loop) control circuit 115
11. be provided. This PT, LllII Tsukuda 1 circuit 1
15 is the one that increases the frequency and phase of the ringing signal 1070, and this P L T,
The control signal 116 output from the control circuit 71.5 is D/
Analog PLL control signal 1 supplied to A converter 1 Noah
Converted to 18. This analog voltage is supplied to a voltage controlled crystal oscillator (V(1'XO) 119vc).
07 is output, and this signal 107 is.

The signal is supplied to the A/D converter 105. However.

This thread path forms a PLL circuit.

Further, the synchronization detection timing generation circuit 109 outputs multiple timing signals 120° 1211-J, respectively, for horizontal countdown times yB Jzz .

The signal is supplied to the vertical countdown circuit 123.

When the horizontal countdown circuit xzzVctd flyback/or pulse signal 124 is supplied, a horizontal synchronization signal is regenerated from the flyback i4 pulse signal 124 and the timing signal 120 (synchronization separation signal), and a horizontal synchronization signal is regenerated based on this signal VC. A horizontal drive signal 125 is output. Still, before l1lL! Tari B1 countdown H road 123Vc
The iQM horizontal countdown circuit 122 is supplied with the horizontal synchronization signal 126, and this horizontal synchronization signal 41
26 and the MiJ timing signal 121 are generated and output by vertical synchronization A3 No. 27.

In addition, I'll gll', Deinotal signal processing circuit 1
In 28, the human-powered digital camera 106 is Dituta ybt+, G, T34p, ? jlzz,
73o, 7,? Jtζ conversion 2. These people's signal nozz, 1so.

J31ζ′j+:i′L 1st D/A cheap converter 7,?
2, 733, I, No. 4, analog t<,
o, B signal r (converted. These (No. 7i (
d, is supplied to a cathode ray tube (not shown) via an output circuit 135.

By the way, the conventional destabilized clamp circuit described above has the following advantages. I(, to 1.

In this method, since the KA/D converter 105 is included in the constraint loop, an automatic black adjustment is performed that also includes the skin movement outside the city due to changes in the A/D converter 105, changes over time, etc. ].Secondly, in order to perform surface current gain control under the illusion of an analog signal '-', :, the input dynamic range of the A/D converter I/'ζ no θ5 is effectively used. ．． It is f'i thing.

However, the conventional destabilized clamp circuit C1
Two D/A exchangers 11 for the 4-langage No. 1-1 θ3 and the analog PLL control signal 11B: (.

117;
2.4'7 Rudame Vr is 10 Pino i-Chen's number of bits! It is set to V p7. Then, when converting the circuit of B into an IC.

Two 1)/A converters J l 3. l The analog circuit section IS including 77 and the Deinocle circuit section are installed on separate chips.
When trying to convert to C, clamp l+! l i+111(
, -i) Since the number of bins increases in response to the bits i and p of the J2 and PLL control signals 116, there is also the disadvantage that the size of the socket increases and the cost increases. Furthermore, considering only the IC implementation of the analog circuit section, the circuit size of the D/A converter (D/A converter) is large, resulting in a disadvantage of 2 costs.

As described above, the conventional pedestal clamp circuit described above may have the problem of (φ/Z) that should be improved.

[Purpose of the invention]

This invention has been made based on the above circumstances, and its purpose is to reduce the number of individual A converters and to reduce the number of individual A converters in order to reduce Is it possible to significantly reduce the number of IIF fingers and at the same time suppress the increase in cost? The present invention attempts to provide a pedestal clamp circuit that achieves 1.

[Invention planting]

This invention utilizes the power/power generated by the 1st and 11th period detection timing generation circuit supplied by Dinotal Video (RI).
? Nitai Mini/G (based on No. 3)
Bit 1. - Extract the p-disk level in No. 1.

σ]−? Error between desk level and reference level)
+ Request this error level by digital fFf j
p-tQ l' W M (Pt+lse Widt
hλ4odula+1on) b1. Convert it to a bow and use this P
By performing analog integration on W M (4) to generate an analog clamp aunt, it is possible to eliminate the conventionally reliable clamp signal generation 1)/Δ bag changer.

[Example of digits and light]

An embodiment of the present invention will be described with reference to the drawings. Furthermore, η! In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and only the different parts will be explained.

In FIG. 2, a digital video signal 106 outputted from an A/I converter 105 is supplied to a synchronization detection timing generation circuit 109. In this synchronization detection timing generation circuit 109, the timing signals 1-4, 120,
121 and timing signal 111 are output. This timing signal 111 is supplied to the Libedestal extraction circuit 220. The pedestal extracting circuit 220 extracts and outputs a pedestal level signal 221 from the distal video signal 106 in accordance with the timing signal 111. The error oil is supplied to the output circuit 224 together with the reference level signal 223 corresponding to the value of the flange level outputted from the reference level generation circuit 222 for the destination level signal 2Z71-J. This error 610'1
In one circuit 224, the difference between the death level signal 221 and the paralysis level signal 223 is detected. This error '6'
p';Jlul:1': ,,'2(,l',re-output)! Mistake 1. B1. 22.5 lJ de 1/'go'le 柘分电路226测试C1给之。. This de1 notal appearance 1 minute [11th road,? 2 G 4-j-! ! This is what determines the IIQ value of the test clamp loop.

77 H77 constant and 1 analog 111 minutes to be described later? ,
< 230 (determined by the balance with 111 constant hinoki) This digital I・' (digital clamp signal 227 output from the division circuit 226 is I) W M generation circuit 228p ((jj supplied) t, PWM R2 signal 229
Convert to tei, l+ru. This P W M frang signal 229
1';1. Anna: ``I'm satisfied with the smoothness of the circuit 2.''

An analog flag signal 10.9 is output from the analog 1)1 minute circuit 230, and the clamp signal 03 is supplied to the analog adder circuit 102 VC.

FIG. 3 shows the error ld calculation shown in FIG. 2 [1i5 Z 24
.

Deinotal integration circuit 226. 71 schematically shows the configurations of the PWM generation circuit 228 and the analog integration circuit 230.

In the error calculation circuit 224, the discriminator 301 determines the disk level 4n 'F221 'l)'.
This is to subtract the left signal 223.Q, is this '13?
! '+' output signal 302 - average value circuit, v o s I
c supplied.

This average value circuit 303 operates at timing 01■ (Ft No. 2).
11, the reduced Ω output during the burst period No. 4u, 1
02, and this average value circuit 303
The error signal 225 outputted from the digital integrator circuit 2
An adder 304 comprising 26 VC is supplied. In this digital integration circuit 226, an adder 304 adds the input error signal 225 and the error signal held by the latch circuit 306 one cycle before. The latch circuit 306 is operated according to the timing signal 211 and holds the output signal 305 of the adder 304 for a predetermined period.

Therefore, in this latch circuit 306, the input signal 305 is 1/2n (n is an integer; in this case, for example, n = 4)! 1 is output. Digital clamp number 46 of 10 bits output from this digital integration circuit 226 227 pB I+ W
M generation circuit 228i (11+l) One side of the 10-bit comparator 307 is supplied with 1, and the other input terminal of this comparator 3θ7 is the IT number output signal 309 of the 10-bit counter 308. 1, the first thing to be paid.

The clock of the counter 308 with (g>2 manual 1"I+
' CL &'c is the clock signal 310 of the length ring ring 1 107 and l-1j, (l skin connection).

Seven-point convergence: Child R has timing 4 shown in Figure 4 (al).
,,'r,n2J ノ are supplied. However,
In the counter 308, timing 411 No. 211 1
0 to 909 in period (horizontal period of N i'SC signal)
Up to +fl number. This counting output signal 309 is supplied to I1.
0i13τ: In the comparator 307, as shown in FIG.
and digital clock 2 block 'LM 53' 227 are compared, and <t11↓ (output signal 309
But Digicuru Frang Shin'j 2. / 7 , the counting output (;, 'i: 309 is output from the digital clamp No. 46 227, and the PWM flag signal 229 becomes a low level.

A well-known analog integration circuit 2 consisting of this PWM clamp signal 229 CR integration circuit and an operational amplifier 313
30 and smoothed. Thus, this analog integration circuit 230 outputs an analog clamp signal 103.

According to the above embodiment, the destal level is extracted from the niJ digital video signal based on the timing signal generated by the synchronization detection timing generation circuit that is fully supplied with the digital video signal, and the descried level and the reference level are extracted. After digitally integrating this error level, convert it into a PWM crank f signal,
This PWM clamp signal is analog-integrated to generate an analog clamp signal. Therefore, since the D/A converter that was conventionally required to generate a clamp signal is not required, if this circuit is integrated into an IC, the number of bins can be significantly reduced and costs can be reduced. have. That is, according to the above embodiment, clamp'(it
The number of bins required for generation of
It is a good idea to provide one bin each corresponding to the 00 Å power end and the output end of the PWM generating circuit 228.
It is possible to significantly reduce the number of pins in the analog N path section and the digital circuit section, and also to suppress the increase in size of the package.

In addition, since the distal circuit section VC junction desk extraction circuit Z2θ and the level generation circuit 222 to PWM generation circuit 228 are small horizontal circuits, it is possible to suppress the increase in size and cost of the IC chip. It is possible to be a woman.

It should be noted that this invention is not limited to the above-mentioned embodiments.
For example, the counter 3 that constitutes the PWM generation circuit 228
08 uses a counter synchronized with the horizontal period, but this is also included in the horizontal countdown circuit 122 shown in FIG. 2, and it is also possible to share this counter.

others. Of course, various modifications can be made without departing from the gist of the invention.

〔Effect of the invention〕

Hereinafter, as described in detail, according to the present invention, D/A
When converting one circuit to ZC by reducing the number of converters, it is possible to significantly reduce the number of bins, and it is also possible to use a pedestal that can suppress cost increases.
A clamp circuit can be provided.

[Brief explanation of the drawing]

Figure 1 is the conventional one! ! Fig. 2 is a block diagram showing an example of the pedestal clamp circuit. This is a waveform diagram shown in order to explain the operation of the pWM generation circuit in Figure 4 and Figure 4. Analog adder circuit, )f1+3...analog flag (i
'No. 5. 105...A7D converter, 109...A7D detection timing generation circuit, 220...Wave texture extraction circuit. ZZ2... Reference level generation circuit, Z24... Error calculation circuit, 226... Digital integration circuit. 228...PWM generation circuit, 2.10...analog integration circuit.

Claims (1)

[Claims] An analog adder circuit that adds an analog crank f signal to a non-analog video signal, and an analog/digital converter that samples and codes the output G'4 of the analog adder i'11 circuit at a predetermined cycle. With the vessel. A synchronization detection timing generation circuit separates the Dino Tarbite 2 O signal outputted from this converter and generates various timing signals, and a predetermined timing f' outputted from this timing generation circuit. A pedestal extraction circuit extracts 4 levels from the digital video signal based on the signal, and an error circuit that subtracts the base IV level from the extracted Kr signal level to obtain an error signal. , a dinotal branch circuit that integrates this error signal, and a pulse width a of this integrated signal.
ff't? It is equipped with a relay width modulation signal generation circuit, and an analog integration circuit that smooths this pulse 1191 Atsushi Ir1 and generates the analog crank f signal (+
1 ”!!Destal clamp circuit.