JPS62268288A - Digital acc circuit - Google Patents

Abstract

PURPOSE:To phase-detect a color burst signal whose amplitude is controlled to be regular by detecting the phase errors of a color burst signal and a sampling clock from the process of detecting the amplitude of the color burst signal, and synchronizing their phases. CONSTITUTION:A shift register 10 fetches only a sample value string during a burst period from the digital sample value string of an inputted chrominance signal 1. The outputs of a latch circuit 12 and a latch circuit 14 are supplied to a subtractor 16 which executes the subtraction whose output is inputted to the one input terminal of an absolute value circuit 18 and an adder 21. Thus the phase control is executed, and as a result, the phases of a fsc clock and a color burst signal coincide with each other. In such a way, i.e., by extracting the sampling phase information from an amplitude detection circuit 3 constituting a part of an ACC loop, the phase detection is executed in a state that the amplitude of color burst signals is kept constant.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital ACrC (Automatic Co1or C) in a digital television receiver.
Control) circuit.

In general, digital television receivers use an analog-to-digital converter (
Hereinafter, it will be abbreviated as an A/D converter. It is necessary to synchronize the phase of the sampling clock that drives the sampling clock (
LL: phase -1ocked 1oop
) is provided.

If this sampling clock is not stable, the A/D converter will not be able to sample the input analog television signal at the desired phase, which will have a significant impact on the performance of the A/D converter and subsequent parts. become.

That is, since the performance after the A/D converter is determined here, it is necessary to stabilize the sampling clock.

However, in a phase-locked loop, if an amplitude change occurs in the reference color burst signal, that is, the color burst signal input into the loop, the amplitude change will change the phase detection sensitivity, and the sampling clock will change. This will have an adverse effect on stability and cause inconvenience.

A digital ACC circuit is provided that uses digital signal processing to control the gain of the color signal so that the color burst signal always has a constant amplitude in response to changes in the amplitude of the color signal. The amplitude of the burst signal can always be kept constant, and amplitude changes can be eliminated. An example of such a circuit is the one described in Japanese Patent Publication No. 59-25996.Although the amplitude of the burst signal is made constant, it cannot be used with respect to the color burst signal input to the phase-locked loop as described above. Therefore, the phase-locked loop is directly inputted with a single color burst signal with amplitude changes. Solve the problems of the conventional technology,
A digital ACC circuit that can be realized with a relatively simple configuration, which can not only keep the amplitude change of the color signal constant due to the characteristics of the transmission path, but also keep the phase detection sensitivity in the phase-locked loop constant. Our goal is to provide the following.

In order to achieve the above object, the present invention digitally multiplies a digitized color signal by a control signal using a multiplier, and then multiplies the digitized color signal by a control signal. A control signal corresponding to the ratio or difference between the detected amplitude value and the reference amplitude value is fed back as a control signal to the multiplier, and the color burst signal (by feedback control) is detected. In addition to controlling the amplitude of the color signal so that the amplitude is one step, the phase error information between the color burst signal and the sampling clock is detected from the process of detecting the amplitude of the color burst signal, and the phase error information is used to perform sampling. The color burst signal is forced to phase synchronize with the color burst signal. That is, as a result, a color burst signal whose amplitude is controlled to be constant is clarified by phase detection.

4. For example, in a digital television receiver, a clock synchronized with the color burst signal is generally used as a clock for sampling and quantizing the baseband analog television signal and A/D converter. used. Frequency 3feC, which is three times the color subcarrier frequency fsc, or frequency 4fsc, which is four times the color subcarrier frequency fsc, is often used. In the digital television receiver to which the present invention is applied, 4nf
ec (n is a natural number) is used. For example, if n = 1, in the N'I'SC method, fsQ = approximately A58 MHz, so the sampling frequency is 4 fsc = approximately 1432 MHz.
It becomes z.

FIG. 5 shows a color burst signal portion of an input television signal. Set the sampling clock frequency to 4 fsc
Then, four sample points are obtained in one period of the color burst, and each sample point is defined as "4n-5+P4n-2+P4,1.
Let it be P4n. That is, from this "4n-5 to P4n
is a θ shift of 90° from the next point with respect to the phase of the color burst.
This is the value sampled for each time. Here, if the amplitude of the color burst signal is A, then P4n-5=A einθ P4n-2=A sin (θ+9[1a)==Aco
sθP4n-+ = A sin (θ+180') =
-A, sin θP4n = A sin
(θ +2700 = -Ac0 day θ. This is a function of the phase θ for sampling the color burst signal, and the amplitude value is given by P4n-2-P4゜-2ACOfIIθ. Therefore, when θ=C10 The amplitude value of the color burst signal can be detected correctly even if there are two people. However, if the value of 6 is not 0, the detected amplitude value will not be 2 A but 2 A (1-cos θ).

Therefore, by performing the calculation = 2A using the sample values of the four points from %P4n-3 to P4n, the amplitude value of the color burst signal can be found regardless of the phase θ. That is, in the present invention, the difference in sample values (
P4n-s -P4n-1) and ("4n-2-"4n
) is used to detect the amplitude of the color burst signal.

Moreover, on the other hand, Pan-5-P4. −1 = 2 A By calculating sinθ, when θ is small, 2A sinθ and 2
The sampling phase θ can be detected and the sampling phase can be controlled. The convergence point of the phase-locked loop at this time is θ
= 0°, and the color reference vectors −(B−Y) and (R
−Y) corresponds to the phase angle of the color burst signal.

[Example of partition stage]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing a digital ACC circuit as an embodiment of the present invention.

In FIG. 1, 1 is the chrominance signal C, which is obtained by separating the analog-to-digital converted television signal. 2 is a multiplier, 6 is an amplitude detection circuit, 4 is a color killer gate circuit, 5 is an output of gate circuit 4, 6 is a color killer circuit, 7 is an output of a latch circuit 27 (described later), 8.9 is a subtraction circuit (described later) 10 is a shift register, 11, 12. 15. 14. 22.
23. 24. 25°, 7, 26.27 are latch circuits, 15.16 are subtracters, 17.18 are absolute value circuits, 19, 20° 21.3
0 is an adder, 28.29 is a squarer, 61 is a coefficient generator, 32.47 is a loop filter, 55.34
are AND circuits, and 49 is a voltage controlled oscillator (hereinafter referred to as VC).
It is abbreviated as O. ), 60 is the output of the color killer circuit 6,
69 is the output of the coefficient generator 31.

The first AND circuit 63 outputs a burst pulse B for extracting a color burst signal from a television signal.
F and a clock with a frequency of 4 fsc (hereinafter abbreviated as 4feC clock) are input, and the 4fe clock is transferred to shift register 1 only during the period when the color burst signal exists.
Supply to 0. Similarly, the second AND circuit 64 is connected to the burst gate pulse BF and a clock having a frequency fsc (hereinafter referred to as
It is abbreviated as fsc clock. ), and during the period of the color burst signal, the fsc clock is input to the latch circuits 11, 12, 15, 14, 22, . 25. 24 respectively.

As a result, shift register 10 and subsequent ones are colored and 8
・The continuity of processing is maintained by operating only during the period when the burst signal exists, and retaining the processing results of the burst period during other periods. , are input to the gate circuit 4 and shift register 10 via the multiplier 2.

The color signal input to the gate circuit 1I64 is output as the output 5, and is input to the subsequent color demodulation circuit (not shown).This gate circuit 4 outputs the output 5' when the color killer is executed.
The purpose is to make t'' zero and eliminate the interference.It is good if this purpose can be achieved, and there is no need to insert it after the multiplier 2.Also, if there is a circuit with functions such as signal processing, etc. It is also clear that there is no need to provide the gate circuit 4.

On the other hand, the shift register 10 takes in only the sample value sequence of the burst period from the digital sample value sequence of the input color signal 1, and delays it up to 4 clocks in units of 4 fsc clocks. Therefore, for example, the first output S1 is delayed by one clock, the second output S2 is delayed by two clocks, the sixth output S6 is delayed by three clocks, and the fourth output S4 is delayed by three clocks. A delay of 4 clocks is obtained.

These first to fourth outputs S1, 32 . S3.34 is held in each of the first to fourth latch circuits 11, 12, 13, 14 at the timing of the fsc clock.

These latch circuits 11, 12 . i3,14 are the sample values of one cycle of the color burst signal P4n-5+ Pan-2r Pan-1+ Pan as shown in FIG.
The value of is sequentially held and outputted in each latch circuit for each color burst cycle at the same timing.

Then, the first latch circuit 11 and the sixth latch circuit 15
The output of the second latch circuit 12 and the fourth latch circuit 14 are input to the second subtracter 16.
subtraction is performed between each. This second
The output 9 of the subtracter 16 becomes one input of the first absolute value circuit 18 and the first adder 21.

The output of the second subtracter 16 is integrated during the period of the burst gate pulse BP by the integrating circuit composed of the first adder 21 and the fifth latch circuit 24, and the result of the seventh result X (P44-s -Pan-1) to the sixth latch circuit 27 to determine the timing of the burst pulse Bl' (for example, if the burst pulse BF indicates the burst period from the rising edge of the pulse to the falling edge of the pulse, The second subtracter 16 always subtracts the output of the second latch circuit 12 from the output of the fourth latch circuit 14. If the output cuff'(i'' of the sixth latch circuit 27 is used and a phase-locked loop is constructed via the loop filter 47.VCO 41r, the fourth latch circuit 14
In the sample @P4n-s, the second latch circuit (Pan-
Phase control is performed so that 5-Pan-1) = 0, and as a result, the phases of the fsc clock and the color burst signal match.

At this time, the first latch circuit 11 always holds the value of the sample value P4o, the third latching circuit 13 always holds the value of the sample value P4n -2, and the first subtracter 15 Pa
The operation of n-2-Pan is performed.
- The result is led to the second absolute value circuit 17 and the absolute value I P
an-2-Pan I is determined and then integrated during the burst gate pulse BFO period by an integrator consisting of the second adder 19 and the seventh latch circuit 22, resulting in ΣlP4゜-2- P4nl is held in the 8th j=1 latch circuit 25 for 1H period. Further, the output I Pan-5Pan-j l of the absolute value circuit 18 of Kun1 is output from the sixth adder 20 and the ninth latch circuit 23.

8th. The outputs of the tenth latch circuits 25 and 26 are respectively the first
．． They are squared by the second square capacity 28.29 and added by the fourth adder 30. This first. Second square capacity 28.2
9 is a read-only memo! j (ROM). As a result of the above initial addition, the output of the adder 60 is (Σl ``4n-5-''4n-1l)
'+(Σl ``4n-2-P4.1)2 is obtained j-13-
1, and the amplitude value of the color burst signal is correctly detected regardless of the sampling phase. The output of this fourth adder 1230 is led to a coefficient generator 51, where the control value necessary to bring the entire amplitude of the color signal to the set reference value is determined. This coefficient generator 61 is, for example, a control target value ff
1Ao, and all the detected amplitude values AB, it can be easily configured to 0 with a ROM that stores the calculation result of =b. The output 69 of this coefficient generator 61 is fed back to the multiplier 2 through a loop filter 62'fI- having low-pass characteristics, and is multiplied by the color signal 1 input to the multiplier 2, so that the amplitude of the color burst signal is Control is performed so that the magnitude of the control target value is achieved.

According to this embodiment, the sampled phase information 'fc4 is output from the amplitude detection circuit 6, which is a part of the ACC loop (consisting of the multiplier 2°, the amplitude detection circuit 6, and the loop filter 52). That is, since the phase detection is performed while the amplitude of the color burst signal is kept constant, the phase detection sensitivity can be kept very constant. Moreover, since amplitude detection can be performed stably regardless of the sampling phase, the Ace loop is used.

A J# that operates stably with both phase-locked loops is created.

In addition, by making the ACCCC time constant t longer than the time constant of the phase-locked loop, the influence on the phase-locked loop due to the transient response of the ACC loop can be made negligible. If the time constant of 1. The second square capacity 28.29 can be made unnecessary, and the circuit scale can be reduced.

Furthermore, according to this embodiment, the first. Second subtractor 15.1
Using the output 8.9 of 6, the color killer circuit 6 can be easily realized as described below.

Figure 2 shows a specific example of the color killer circuit 6 shown in Figure 1?
ll is shown. 52 and 55 are comparators, 54.degree. and 61.mu. are OR circuits, 56 is a bidirectional counter, and 59 is an RS type fill frog (hereinafter abbreviated as R8-FF).

) 65 is a sign discrimination circuit, which is a 0th 1.2 subtracter 15.
The outputs 8.9 of i6 are the first . Second comparator 52.5
5 and the reference value REF1. A comparison with REF2 is made. When the sampling clock is phase-locked to the color output signal by the means described above, the output B is Σl
P4n-2-P4n l = 2 kAI錡1, and the output 9 is Σl Pan-5-P4n-j l = OI1. Also, the reference value REF1. 0 to 2k to REF2
Any value within the range of A. At this time, the first ratio *9.
When Σl"4n-2-P4n l < RBF 1 in the comparator 52, or Σl P4n4 in the second comparator 55
-"4n-j l > REF 2I Stomach 1 If the amplitude of the input color signal is extremely small and exceeds the control range of 800, or the S/N is extremely deteriorated, or the color It can be determined that there is no burst signal or the phase-locked loop is not locked and the color cannot be demodulated correctly.Furthermore, 15. The code discrimination circuit 66 uses the code bit of the output 8.9.
Determine the sign. At that time, the sign bit of output 8, 9
If either of these two values is negative, it can be determined that the phase-locked loop is not locked. In the above cases, it is necessary to operate the color killer, and therefore, it can be used as a condition for operating the color killer.

Therefore, the above-mentioned 1. When the second comparators 52 and 53 and the sign discrimination circuit 66 satisfy the above-mentioned conditions, the outputs are given to the first OR circuit 54. If there is an output from either the first and second comparators 52, 53 or the sign discrimination circuit 63, the first OR circuit 54 uses the output 55 to cause a bidirectional counter 56 to count up. It is given as a mode switching signal for either countdown or countdown. This counter 56 is equal to fSc
It operates using a clock as a clock and counts values from +N to -M. Now, it is assumed that when there is the above-mentioned output from the OR circuit 54, the counters 56 perform a count-up operation, and when there is no output, they perform a run-down operation. Then, the bidirectional counter 56 counts up and counts down according to the probability of occurrence of the output of the first OR circuit 54, and when the count exceeds +N, the overflow signal 57 is output as -.
When the count is N or less, an underflow signal 58 is output.

When this overflow signal 57 or underflow signal 58 is output, the second OR circuit 61
A reset signal 62 is output to reset the bidirectional counter 56 to zero. Further, when this overflow signal 57 is generated, a color killer signal 60 is generated by the R8-FF 59, and this color killer signal 60 is outputted until an underflow signal 58 is outputted. This color killer signal 60μ is applied to the gate circuit 4 shown in FIG. It can be realized.

Incidentally, the coefficient generator 61 described in this embodiment calculates 11 by using the difference AB - AO between the detected amplitude value AB and the reference value A.
It is possible. In other words, since the gain correction amount for the amplitude error AB -A can be predicted in advance, for example, the multiplier 2 is configured with a ROM, and the coefficient generator 61 performs the calculation AB -A. It can also be replaced with a subtracter.

Next, another embodiment of the present invention is shown in FIG. In FIG. 3, 67 is a switch circuit, 68 is an absolute value circuit, 70 is a squarer, 71 is an adder, 72 and 73 are latch circuits, respectively.
74 is an AND circuit. In this embodiment, the circuit scale of the amplitude detection circuit B can be reduced compared to the embodiment shown in FIG.

The configuration of the phase difference detection process in this embodiment is the same as in the previous embodiment, and from the first subtractor 15 (Plb+-2-
"4n), but from the second subtractor 16, (P4n-5'
-P4n-1) are obtained and supplied to the switch circuit 67, respectively. The switch circuit 67 operates according to the logic of *1# and 0# of the fsc clock, ("4n-5-
P4n-+) and ("4n-2-"4n) are alternately selected and output, and the outputs of the first and second subtracters 15 and 16 are time-division multiplexed.

The absolute value of the output of this switch circuit 67 is determined by a third absolute value circuit 68, and the output is divided into two by a third square capacitor 70.
be multiplied. The output of the sixth square capacitor 70 is integrated during the period of the burst gate pulse BF by an integrator consisting of a fifth adder 71 and an eleventh latch circuit 72, and the result is integrated every 1H. It is held in twelve latch circuits 73. Therefore, the output of the twelfth latch circuit 73 is obtained. Therefore, in this embodiment as well, the amplitude of the color burst signal can be detected correctly regardless of the sampling phase. The gain control amount of the output of the twelfth latch circuit 76 is determined by the coefficient generator 61 as in the previous embodiment, and is fed back to the multiplier 2 via the loop filter 62 having low-pass characteristics. , is multiplied by the color signal 1, and the color burst signal amplitude is controlled so as to have the magnitude of the total control target value.

Here, as in the previous embodiment, the coefficient generator 61 may be a ROM that stores a negative value or a subtractor that performs subtraction AB-AO, depending on the configuration means of the AB multiplier 2. It's okay. (Here, AB is the detected amplitude value b
AO is a control target value. ) In this embodiment, the same effect as the previous embodiment can be obtained, and compared to the previous embodiment, the absolute value circuit, squarer, adder, and latch circuit can be reduced, making it possible to significantly reduce the circuit scale. be. Furthermore, in this embodiment, due to the issue of making the time constant of the ACC loop longer than that of the phase-locked loop, the amplitude detection is performed by excluding the square capacity 70.
+I P4. -2-P4. The desired circuit operation can be expected even if it is approximated as 1M+1.

Further, in this embodiment as well as in the previous embodiments, a color killer circuit as shown in FIG. 2 can be easily realized.

Next, FIG. 4 shows a block diagram showing the configuration of a digital television receiver using the digital ACC circuit according to the present invention. In FIG. 4, 65 is an input terminal, 66 is an A/D converter, 67 is a Y/C separation circuit, 68 is a luminance signal processing circuit, 69 is a color demodulation circuit, 40 is a matrix circuit,
41, 42, and 43 are analog converters (
Hereinafter, it will be abbreviated as a D/A converter. ) 44 is a cathode ray tube, 50 is a synchronization separation circuit, and 51 is a timing generation circuit.

Also includes multiplier 2, amplitude detection circuit 6, gate circuit 4, color killer circuit 6% loop filter! +2.47, VCO
49 is the circuit shown in FIG. 1 or FIG. 6, respectively.

Baseband analog television signal is input terminal 6
5, is converted into a digital television signal by an A/Di converter 66, and then sent to a Y/C separation circuit 67 and a sync separation circuit 5.
Input to 0. '! The '/C separation circuit 67 separates the manually generated digital television signal into a luminance signal (Y) and a color signal (C). The separated color signal 1 is
The signal is input to an amplitude detection circuit 3 and a gate circuit 4 via a multiplier 2 .

This amplitude detection circuit 6 performs the processing described above and outputs a phase detection signal 7, an amplitude control signal 69, and a color killer detection signal 8.9, respectively.

The phase detection signal 7 is applied as a control signal for controlling the VCO 49 via a loop filter 47 that has a low-pass characteristic, and controls the phase of the 4feC clock output from the VCO 49. Therefore, the phase-locked loop
It is composed of the converter 56 - Y/C separation circuit 67 - multiplier 2 - amplitude detection circuit 3 - loop filter 47 → VCO 49 → A/D converter 36, and the sampling phase is the color reference vector - (
B-Y).

Phase control is performed so that the signals are aligned with (RY).

Further, as mentioned above, the ACC loop is composed of the multiplier 2 -> amplitude detection circuit 3 - loop filter 32 - multiplier 2,
Amplitude control of the color signal is performed so that the color burst signal has a reference amplitude value. This amplitude-controlled color signal is
The signal is supplied to the color demodulation circuit 59 via the gate circuit 4 operated by the color killer circuit B, and after demodulation processing is performed on the R2Y signal and the BY signal, hue adjustment is performed, for example, by manual adjustment.

Color saturation adjustment is performed and the signal is input to the matrix circuit 40. On the other hand, the luminance signal is subjected to processing such as contrast, brightness, and contour correction in the luminance signal processing circuit 6, and then input to the matrix circuit 40.

The matrix circuit 40 converts the input luminance signal, RY signal, and BY signal into six primary color signals of red (R), green (G), and blue (B). This R,G.

The B signals are converted into analog signals by D/A converters 41, 42, and 43, respectively, and applied to a cathode ray tube 44, so that an image is reproduced.

The synchronization separation circuit 50 separates the negative synchronization signal from the digital television signal and generates a signal H that serves as a horizontal and vertical reference.
D and VD are applied to the timing generation circuit 51. The timing generation circuit 51 generates 4 fsc, which is the output of the VCO 49.
Clock and the horizontal and vertical reference signals HD, VD'i
This is used to output burst gate pulses BF, clamp pulses, etc.

〔Effect of the invention〕

According to the present invention, the amplitude change of the color signal due to the characteristics of the transmission path is not only made constant (but also the phase detection is performed using the color burst signal whose amplitude is controlled to be constant by the ACC loop. Phase detection sensitivity can also be kept constant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital ACC circuit as an embodiment of the present invention, and FIG. 2 is a block diagram showing a specific example of the color killer circuit in FIG. 1.
FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of a digital television receiver using a digital ACC circuit according to the present invention, and FIG. 5 is a sample of a color burst signal. It is an explanatory diagram showing points. 2... Multiplier, 6... Amplitude detection circuit, 4... Gate circuit, 6゛°° power killer circuit, 1... Shift register, 11. 12. 13. 14. 22. 2
3. 24. 25°26, 27.72. 73...
・Latch circuit, 15. M...subtractor, 17. 18.
68...Absolute value circuit, 19,20°21.50.7
1...Adder, 2B, 29. 70... Squarer, 31... Coefficient generator, 32.47... Loop filter, 33, 34.74... AND circuit, 52.53
... Comparator, 54.61 ... OR circuit, 56...
・Both sides same counter, 59...RS Philip flop, 66...Sign discrimination circuit, 49...VCO156・
・・A/D converter, 37 ・Y/C separation circuit, 50・
...Synchronization separation circuit, 51...Timing generation circuit.

Claims (1)

[Claims] 1. Digital ACC that separates the carrier color signal from the input television signal and controls its level to a constant level.
In the circuit, the television signal is sampled by a voltage controlled oscillator that oscillates at a frequency 4n times (where n is a natural number) the color subcarrier frequency of the television signal, and a clock synchronized with the output of the voltage controlled oscillator. A/
A multiplier that digitally multiplies a carrier color signal separated from a digital signal obtained by D conversion by a control signal, means for serial-to-parallel conversion of the digital output signal from the multiplier, and a means for converting the digital output signal from the serial-to-parallel conversion means. 4 whose sampling phase differs by 90° with respect to the color subcarrier as an output signal.
means for simultaneously latching signals separated into two signals;
The latch means includes first and second subtracters that perform subtraction between signals whose sampling phases differ by 180 degrees with respect to the color subcarrier; means for detecting the level of the burst signal section; means for feeding back a control signal corresponding to the output level of the detection means as a control signal for the multiplier; and an output of one of the first and second subtracters. means for applying as a signal to control the voltage controlled oscillator, the gain control of the color signal is performed in the multiplier so that the level of the color burst signal is constant; A digital ACC circuit characterized in that the output of an oscillator is phase-synchronized with the color burst signal.