JP3473076B2 - Color signal demodulator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for demodulating a color signal in an NTSC television signal. 2. Description of the Related Art Hitherto, color signal demodulation has been mainly constituted by analog circuits. However, A of the demodulated color difference signal
When it is necessary to perform digital signal processing by performing / D conversion, the color signal can be directly demodulated by A / D conversion at the sampling timing of a clock synchronized with the burst signal. In such a case, conventionally, a phase shifter that changes the sampling timing by manually adjusting a variable resistor has been used. This will be described below with reference to the drawings. FIG. 9 is a block diagram showing a conventional chrominance signal demodulation apparatus. In the figure, 1 is a chrominance signal input terminal, 2 is a luminance signal input terminal, 3 is a synchronization separation circuit, 4 is a monostable multivibrator, and 5 is a PLL. Oscillator, 100 is a phase shifter, 101 is a variable resistor, 7 is a multiplier, 8 is a buffer amplifier, 9 is an A / D converter, 10 is an arithmetic unit, 11 is a 4 frequency divider, 12 is a switch,
13 is a frequency divider, 14 is a color difference signal CR (RY signal) output terminal, and 15 is a color difference signal CB (BY signal) output terminal. [0004] Of the television signals, a chrominance signal is applied to a chrominance signal input terminal 1 and a luminance signal is applied to a luminance signal input terminal 2. From the luminance signal, only the synchronization signal is extracted by the synchronization separation circuit 3. Using the extracted synchronization signal as a trigger, the monostable multivibrator 4 is driven, and the monostable multivibrator 4 generates a timing signal indicating a burst portion of a color signal (this timing signal is hereinafter referred to as a burst gate signal). . On the other hand, the color signal from the color signal input terminal 1 is
In the PLL oscillator 5, after only the burst signal is extracted at the timing of the burst gate signal, a reference subcarrier synchronized with the burst signal (hereinafter referred to as an fsc signal)
Is generated. This fsc signal is input to the phase shifter 100 and the phase is changed. The fsc signal whose phase has changed is input to the multiplier 7 and multiplied by 4, and then shaped by the buffer amplifier 8 (this signal is hereinafter referred to as a 4fsc signal). The color signal is input to the A / D converter 9 and is sampled at the timing of the 4 fsc signal to be a digital signal. The color signal that has become a digital signal is
In the arithmetic unit 10, the sign inversion operation is performed every two samples by a timing signal generated by the 4 frequency divider 11 of the 4fsc signal and changing every two samples.
Further, the data sequence on which this operation is performed is converted into one by a timing signal which is generated by the frequency divider 13 of the 4 fsc signal and changes every one sample in the switch 12.
Taken alternately for each sample. One output of the switch 12 thus extracted is a color difference signal CR, and the other output is a color difference signal CB. Both are output from a CR signal output terminal 14 and a CB signal output terminal 15, respectively. However, the CR output in this way is
The signal and the CB signal are not always correct signals. This is because the timing of sampling is indefinite and the phase may turn. Therefore, conventionally, the variable resistor 10 for adjustment is used so that the CR signal and the CB signal are correct.
1 changes the phase characteristics of the phase shifter 100 to adjust the sampling timing. FIG. 10 shows an example of the phase shifter 100 in FIG. FIG. 11 shows an example of the frequency dividers 11 and 13. Also,
FIGS. 12A and 12B are simple operation explanatory diagrams. FIG. 12A shows an NTSC color signal, FIG. 12B shows a luminance signal, and FIG. 12C shows a color signal vector display. Since the conventional color signal demodulation device is configured as described above, the variable resistor 101
Therefore, manual adjustment of the phase shifter 100 with extremely high accuracy is required, and the adjustment is difficult. In addition, there is a problem that the sampling phase changes due to a power supply voltage fluctuation, a temperature change, or a temporal change, and the hue changes. SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and has as its object to obtain a color signal demodulation device which can reduce the number of manually adjusted portions and always can demodulate a color signal with high accuracy. And A chrominance signal demodulator according to the present invention includes a synchronization separation circuit for extracting a synchronization signal from a luminance signal, and a timing signal (hereinafter referred to as a burst signal) indicating a burst signal portion of a chrominance signal from the synchronization signal. Gate signal), an oscillator controlled by a burst gate signal from the timing signal generating circuit and generating a reference subcarrier synchronized with a burst signal of a color signal, and an output signal of the oscillator. Based on the reference subcarrier clock signal
Color signal sampled by the A / D converter
The R-Y and B-Y color difference signals (hereinafter, respectively color difference signals C
R and CB) and a color signal bus.
Flip-flop that holds the color difference signals CR and CB of the
And the sign of each of the color difference signals CR and CB.
Comparator calculates the direction of phase change from the output of this comparator
Gate circuit that controls the phase of the previous burst
Signal and the output signal of the above gate circuit
Adder for generating a signal for controlling the
Holds the signal that controls the phase during the current burst
A phase detector constructed by flip-flops, clock of the reference subcarrier by an output signal of the phase detector
And a phase shifter for controlling the phase of the color difference signal to a normal phase by changing the phase of the color signal . A synchronizing separation circuit for extracting a synchronizing signal from a luminance signal, a timing signal generating circuit for generating a timing signal indicating a burst signal portion of a chrominance signal from the synchronizing signal, and a burst gate signal from the timing signal generating circuit. An oscillator that is controlled and generates a reference subcarrier synchronized with a burst signal of a color signal, and a clock signal of a reference subcarrier that is an output signal of the oscillator ,
The color signal sampled by the A / D converter is converted into RY
And BY color difference signals (hereinafter color difference signals CR and C, respectively)
B) and a burst portion of the color signal
Average value circuit for outputting the average value of the color difference signals CR and CB for one minute
And the averaged color difference signal output from this average circuit.
A phase detector for detecting the transfer error from No. alters by an error phase of the color difference signals by the output of the phase detector
It has a matrix calculator. The color signal demodulation device according to the present invention detects the phase of the digital color difference signals CR and CB after A / D conversion by a phase detector, and after D / A conversion of this phase detection signal, performs phase shift. in addition to the vessel, changing the reference sub-carrier wave phase, or the phase of the color difference signal is controlled to be correct, or in addition to it the matrix phase detection signal of the digital data <br/> data, color difference signals by calculation both varying the phase, both color difference signals CR and CB to be input to the phase detector is an average value processed through an averaging circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment of the present invention. The same parts as those of the conventional device shown in FIG. 6 is a variable voltage phase shifter, 16 is a phase detector, 17
Is a D / A converter. The operation up to the point where the color difference signals CR and CB are output as the output of the switch 12 from the color signal and the luminance signal is the same as that of the conventional example.
Is output not only to the output terminals 14 and 15 but also to the phase detector 16. The phase detector 16 uses the burst gate signal from the monostable multivibrator 4 to output the CR signal and C
A comparison is made between the B signal and the value "0". In the case of a correct CR signal and CB signal, the CR signal in the burst section is 0,
Since the CB signal in the burst section is negative, the comparison result indicates that the phase is in the negative direction when CB <0 and CR> 0, and
It can be seen that when CB <0 and CR <0, the phases are respectively turned in the positive direction. Also, if the CB signal is greater than 0 even if the CR signal is 0, it is considered that the phase is rotated by 180 degrees. The result of such comparison is output from the phase shift detector 16 as a digital signal (hereinafter, referred to as a phase signal). This phase signal is input to the D / A converter 17,
It is converted to a voltage value of an analog signal. D / A converter 17
Is input to the variable voltage phase shifter 6 to control the phase of the fsc signal. As a result, the sampling timing of the A / D converter 9 changes, and correct demodulation is performed. FIG. 2 shows an example of the phase detector 16 used in the color signal demodulator shown in FIG. The CR signal and the CB signal are input to a DFF (D-type flip-flop, a truth table of the DFF is shown in FIG. 8) 21. Since the burst gate signal is input to the clock of the DFF 21 from the terminal 20, the CR signal and the CB signal are output at the timing of the burst gate signal.
The signal is retained. The output of the DFF 21 is next input to the phase detection circuit 22 and compared with the value “0”. Considering now that the CR signal is negative and the CB signal is negative, that is, the phase is shifted in the positive direction, the value "-1" is supplied to the switch 26 from the combinational logic circuits 23 to 25. A signal to be selected is sent. The selected value “−1” is input to the adder 27. The addition result of the adder in the previous burst is input to the other input of the adder 27 through the DFF 21. Therefore, the phase signal output from the adder 27 has a value obtained by subtracting 1 from the previous value. This phase signal is D / A converted by the D / A converter 17 of FIG. 1 and then input to the variable voltage phase shifter 6.
The phase of fsc is changed in the negative direction. Evaluation of the changed phase is performed at the time of the next burst signal. If the phase is still deviated in the positive direction, the above procedure is repeated.
"1" is selected, so that the phase is changed in the positive direction. If the phase is not shifted, that is, if the CB signal is negative and the CR signal is 0, the switch 26 sets “0”.
Is selected, the phase signal retains its previous value, and the phase does not change. When the CB signal is positive or 0, the switch 26
Then, since "+1" is always selected and the phase is changed in the positive direction, the evaluation of the CR signal is not performed unless the CB signal becomes negative. FIG. 3 shows an example of the variable voltage phase shifter 6 used in the color signal demodulator of FIG. In the figure, 30 is an fsc input terminal from the PLL oscillator 5, 31 is a phase signal input terminal from the D / A converter 17, 32 is a voltage-controlled current variable amplifier, 33 is an inverting amplifier, 34 is a capacitor,
35 is an fsc output terminal. Here, an example is shown in which the phase control characteristic of the all-pass filter is changed without changing the signal amplitude by using an amplifier capable of changing gm by the voltage-controlled current variable amplifier 32. The variable resistor of the phase shifter may be constituted by an FET, and the phase may be changed by changing the gate voltage. The D / A converter may be a general R-2R type ladder resistor or the like, but may also be configured by PWM (pulse width modulation) and LPF (low pass filter). Embodiment 2 FIG. FIG. 4 shows another embodiment of the present invention. The difference from FIG. 1 is that a matrix operation unit 41 is provided instead of the voltage variable type phase shifter 6, and FIG. Means that the second phase detector 40 having a slightly different configuration is provided. In the first embodiment, the output of the phase detector 16 is D
The signal is converted into an analog signal by the / A converter 17, and the phase of the fsc signal is changed by this signal, thereby controlling the sampling timing of the A / D converter. On the other hand, in this embodiment, the CR signal, C
The B signal is input to the phase detector 40. Phase detector 40
Then, the phase difference which is an error is strictly calculated, and the phase difference signal θ is output. FIG. 5 shows an example of the phase detector 40. The phase difference θ of the burst portion is calculated by the following equation. θ = π−arctan (CR / CB) The phase detector 40 shown in FIG. 5 includes a ROM 50 programmed with the above calculation, a DFF 21, and an output terminal 51. The output .theta. Of the output terminal 51 is input to the matrix calculator 41, and a matrix operation is performed on each of the CR signal and the CB signal so as to correct the error, and the hue is corrected by digital data. FIG. 6 shows an example of the matrix calculator 41. Since the matrix operation is an operation to rotate the phase,
Assuming that the desired phase difference is θ, the calculation to be performed is as follows. CB ′ = COSθ · CB−SINθ · CR CR ′ = SINθ · CB + COSθ · CR At the time of performing the above arithmetic processing, in FIG. It comprises an adder 28 and a subtractor 64. Embodiment 3 FIG. In the present embodiment, an averaging circuit is inserted on the input side of the phase detectors of the first and second embodiments to obtain a color signal demodulation device that is more resistant to noise. FIG. 7 shows an example. In the figure, the color difference signals CR and CB applied to the color difference signal input terminals 18 and 19 are input to an adder 27. The output of the adder 27 is the DFF 21
The signal is input to the other input terminal of the adder 27 through “a”. The clock terminal of the DFF 21a is connected to the terminals 70 to 4
fsc is input, and a burst gate signal is input from the terminal 20 to the clear terminal. If the burst gate signal is a signal of "H" with a length corresponding to the α wavelength of 4 fsc, the color difference signal is added α times in the adder, and the sum is added to the DFF of the next stage.
21b is held at the falling edge of the burst gate signal. Further, the held signal is input to a divider 71 and divided by α. The result is output to the color difference signal output terminals 14 and 15. In the digital signal processing, if the value α is a multiplier of 2, the divider 71 becomes simpler and can be realized by a bit shift. Therefore, for example, values such as 16 and 32 may be selected. The CR signal and the CB signal thus obtained are input to the phase detectors 16 and 40 described in the first and second embodiments. As described above, according to the present invention, manual adjustment is not required at the time of color signal demodulation, and stable color demodulation can be performed even when the power supply voltage fluctuates, changes in temperature, or changes over time. Become. Further, in the case where the phase is adjusted using a matrix calculator, in addition to the above-described effects, digital processing is mainly performed, so that the circuit scale can be reduced, for example, when an IC is used. Further, in the case where the average value circuit is provided on the input side of the phase detector, it is possible to perform demodulation resistant to noise.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing a color signal demodulation device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a phase detector used in the device of FIG. FIG. 3 is a circuit diagram showing an example of a variable voltage phase shifter used in the device of FIG. FIG. 4 is a block circuit diagram illustrating a color signal demodulation device according to a second embodiment of the present invention. FIG. 5 is a circuit diagram showing a phase detector used in the apparatus of FIG. FIG. 6 is a circuit diagram showing a matrix calculator used in the device of FIG. 4; FIG. 7 is a circuit diagram showing an average value circuit of a phase detector used in Embodiment 3 of the present invention. FIG. 8 is a diagram illustrating a truth table of a D-type flip-flop. FIG. 9 is a block circuit diagram showing a conventional color signal demodulation device. FIG. 10 is a circuit diagram showing a phase shifter used in the device of FIG. FIG. 11 is a circuit diagram showing a frequency divider used in the device of FIG. 9; FIG. 12 is an explanatory diagram of a color signal demodulation operation. [Description of Signs] 1 Color signal input terminal 2 Luminance signal input terminal 3 Synchronous separation circuit 4 Monostable multivibrator 5 PLL oscillator 6 Variable voltage phase shifter 7 Multiplier 8 Buffer amplifier 9 A / D converter 10 Operation unit 11 4 frequency divider 12 switch 13 2 frequency divider 14 color difference signal CR (RY) output terminal 15 color difference signal CB (BY) output terminal 16 phase detector 17 D / A converter 18 color difference signal CR (R- Y) Input terminal 19 Color difference signal CB (BY) input terminal 20 Burst gate signal input terminal 21 DFF (D-type flip-flop) 22 Phase detection circuit 23 Inverter 24 OR gate 25 AND gate 26 Switch (3 inputs and 1 output) 27 Adder 28 Phase signal output terminal 30 fsc input terminal 31 Phase signal input terminal 32 Voltage controlled current variable amplifier 33 Inverting amplifier 34 Conden 35 fsc output terminal 40 the second phase detector 41 RO programming the operation of detecting a matrix calculator 50 phase difference signal
M 51 Phase difference signal output terminal 60 Phase difference signal input terminal 61 ROM with programmed sine function 62 ROM with programmed cosine function 63 Multiplier 64 Subtractor 704 4 fsc input terminal 71 Divider

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/44-9/78

Claims (1)

(1) A synchronizing separation circuit for extracting a synchronizing signal from a luminance signal, and a timing signal (hereinafter, referred to as a burst gate signal) indicating a burst signal portion of a chrominance signal from the synchronizing signal. Controlled by a timing signal generation circuit and a burst gate signal from the timing signal generation circuit;
An oscillator for generating a reference subcarrier synchronized with a burst signal of a chrominance signal, and a chrominance signal sampled by an A / D converter based on a clock signal of the reference subcarrier, which is an output signal of the oscillator, is denoted by RY. A switch for distributing the color difference signals of BY (hereinafter referred to as color difference signals CR and CB), and color difference signals CR and CB of a burst portion of the color signal;
, The color difference signals CR, CB
A comparator that determines the sign of each of the above, a gate circuit that calculates the direction of phase change from the output of the comparator, a signal that controls the phase at the time of the previous burst, and a phase that is operated on the output signal of the gate circuit. Adder for generating a signal for controlling the phase shifter, and a phase detector comprising a flip-flop for holding a signal for controlling the phase at the time of the current burst, which is the output of the adder, and an output signal of the phase detector. A color signal demodulator comprising: a phase shifter that varies a phase of a clock signal of the reference subcarrier and controls a phase of the color difference signal to a normal phase.