JPS61267480A - Clock generating circuit for digital television receiver - Google Patents

Abstract

PURPOSE:To generate a system reference clock which has a wide leading-in range with an integer-fold frequency of a color burst signal as the center and has stable frequency and phase, by using output signals from a frequency error detecting circuit and a phase deviation detecting circuit as control signals to control the frequency and the phase of the system reference clock. CONSTITUTION:In a system reference clock generating circuit 7, a sampling point as the reference of weighting is detected by a peak detecting circuit 8. A frequency error detecting circuit 9 and a phase deviation detecting circuit 10 operate several sampling points on a basis of the reference sampling point and detect an extent of frequency error and that of phase deviation respectively and output them. Signals outputted from these circuits 9 and 10 are added by an adder 11 and are converted to an analog value by a D/A converter 13, and this value is inputted as a frequency and phase control signal to a voltage control oscillator 15 by a low pass filter and amplifying circuit 14. Thus, a system reference clock 16 whose frequency is controlled to an integer-fold value of the color burst signal is generated from the voltage control oscillator 15.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a clock generation circuit, and more particularly.

The present invention relates to a clock generation circuit used in a digital television receiver that performs analog-to-digital conversion of an analog composite video signal including a color burst signal and performs digital signal processing.

[Background of the invention]

In digital television receivers that perform analog-to-digital conversion and digital signal processing of analog composite video signals including color burst signals, the system reference clock is used for sampling the analog composite video signal and subsequent signal processing. , its stability is very important. In other words, small fluctuations in the system reference clock have a large effect on one image, and especially during color demodulation, the difference in phase of the subcarrier for one color with respect to the color burst signal results in a change in hue, resulting in unevenness in one color. It appears in the image as. Therefore, in order to stabilize the signal, a method has been devised in the past in which the color burst signal is extracted from the analog composite video signal and added to a crystal oscillator to generate a chlorine, but this method has the disadvantage that it is difficult to obtain the desired phase. Also.

A device using a method of controlling the phase by increasing the weight by 1 using a sampled color burst signal is described in Japanese Patent Publication No. 58-60889. Since it is configured on the assumption that the frequency is very close to an integral multiple of the burst signal, the clock frequency (initial clock frequency) before being controlled, such as when switching channels or turning on the power, etc. Another problem is that when the frequency of the system reference clock is significantly different from the frequency of an integral multiple of the color burst signal, not only one phase but also the frequency cannot be controlled.

[Object of the invention].

The purpose of the present invention is to solve the problems of the prior art described above,
A clock generation circuit that has a wide pull-in range around a frequency that is an integer multiple of the color burst signal and is capable of generating a stable system reference clock that has a frequency that is an integer multiple of the color burst signal and has a phase of a set value. Our goal is to provide the following.

[Summary of the invention]

In order to achieve the above object, the present invention provides a frequency/error detection circuit that obtains a frequency error of a system reference clock by calculating using some sampling points of a digitized color burst signal. A phase deviation detection circuit for obtaining a phase deviation at a point is provided, and output signals from each circuit are used as control signals to control the frequency and phase of the system reference clock.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG. 1 below.

In Figure 1, l is an analog composite video signal, 2 is an amplifier/clamp circuit, and 3 is an analog-to-digital converter (
Hereinafter, it will be abbreviated as an A/D converter. ), 4 is a digital composite video signal, 5 is a synchronization separation circuit, and 6 is a rear-stage video signal processing circuit.

Also, 7 is the system reference clock generation circuit.

Peak detection circuit 82 Frequency error detection circuit 92 Phase deviation detection circuit 10. Adder 11. Gate hold circuit 12.
Digital-to-analog converter (hereinafter referred to as

Abbreviated as D/A converter. )13. Low pass filter
It is composed of an amplifier circuit 14 and a voltage controlled oscillator 15, and generates a system reference clock 16.

Next, the operation will be explained.

First, an analog composite video signal 1 is input to an amplifier/clamp circuit 2, amplified to the input level of an A/D converter 3 at the next stage, and then input to the A/D converter 3 after its DC level is adjusted. The A/D converter 3 samples the video signal using the system reference clock 16 and outputs it as a digital composite video signal 4. This digitized video signal 4 is sent to a synchronization separation circuit 5. Post-stage video signal processing circuit 6
and are input to the system reference clock generation circuit 7, respectively. In the system reference clock generation circuit 7, the peak detection circuit 8 first detects a sampling point which becomes a reference for weighting by 1. The frequency error detection circuit 9 and the phase deviation detection circuit 10 calculate the frequency error amount and the phase deviation amount by calculating several sampling points based on the reference sampling point.

Output the detection results. The signals output from each are added by an adder 11, converted to an analog value by a D/A converter 13, and then converted into one frequency/phase control signal by a low-pass filter/amplifier circuit 14 to a voltage controlled oscillator 15. is input. As a result, the voltage controlled oscillator 15
From this, a system reference clock 16 is generated whose frequency is an integral multiple of the color burst signal, particularly four times that of the color burst signal, and whose phase is controlled to a constant value. In addition, as mentioned above, A/
The D converter 3 samples and quantizes the input video signal based on this clock 16.

Next, the configuration and operation of the main circuits in FIG. 1 will be explained in more detail using FIGS. 2 to 5.

FIG. 2 is a block diagram showing the peak detection circuit 8 in the ta1 diagram.

In FIG. 2, 17 is an l clock delay circuit.

18 is an inversion circuit, 19 is an adder and encoder, and 20 is an output signal of the peak detection circuit 8.

Moreover, FIG. 3 shows the color burst signal, its sampling point, and the output signal Pn (n=0, 1) of the peak detection circuit.
, 2...) 20.

The peak detection circuit 8 outputs the sign of the difference between the input sample point Sn and the sample point 5n-1 one sample past, as shown in FIG. In other words, it performs the operation expressed by the linear equation (1). Here, sign is a function that outputs O when the argument is positive or zero, and outputs 1 when the argument is negative.

Next, FIG. 4 is a block diagram mainly showing the configurations of the frequency error detection circuit and phase deviation detection circuit of FIG. 1.

In FIG. 4, 21 is an inverter, 22 is a shift register, and 23, 24, and 25 are adders.

Further, as mentioned above, 8 is a peak detection circuit, 11 is an adder, and 1
2 is a gate hold circuit.

The operation of the mixed 5 frequency error detection circuit 9 will be explained in principle.

FIG. 5 is a waveform diagram for explaining the operation of the frequency error detection circuit, and shows the color burst signal waveform and its sampling points. If (a) is equal to 4 times the frequency of the signal 4fsc, (b)
(C) The case where it is large and (C) the case where it is small.

Now, the rising point of the signal Pn output by the peak detection circuit 8 is set as the reference sampling point s4m (m=1.2.
), then the sampling point 84 of 4 samples past
(m-1) means that the frequency f of the system reference clock 16 is exactly four times that of the color burst signal, 4fsc I
If c is equal, then the phase at 84m and the phase at 84(m-1) are equal, as shown in FIG. 5(a).

The digital values at each sampling point are also the same. However, if the frequency f of the system reference clock is greater than four times the frequency 4fsc of the color burst signal.

As shown in FIG. 5(b), the phase at sampling point 34m leads the phase at S4(m-1), so the digital value is larger at 84m than at 84(m-1).

Conversely, if the frequency f (D) of the system reference clock is smaller, the result will be as shown in FIG. 5(c).

Since the phase at 84m lags behind the phase at 84(m-1), the digital value at 84(m-1) is sharper than at 54rn. In other words, the error F between the frequency f of the system reference clock and the frequency 4fsc, which is four times the frequency of the color burst signal, is F = 84rn -84(m -1) ・
--(2), and when F=O, the frequency f of the system reference clock becomes equal to the frequency 4fsc, which is four times the frequency of the color burst signal.

In FIG. 4, this frequency error detection circuit 9 is composed of an inverter 21 for inverting the digital composite video signal 4, a shift register 22 for delaying the digital composite video signal 4 by 4 samples, and an adder 24.

Next, the operation of the one phase deviation detection circuit 10 will be explained in principle.

The first output is a waveform diagram for explaining the operation of the phase deviation detection circuit, and shows a color burst signal and sampling points.

The phase deviation ejection circuit 10 is a circuit that detects the deviation between the reference phase o' (tsOo) of the color burst signal and the phase of the sampling point 84m. The frequency f of the system reference clock is already the color burst signal (41!17)
Frequency 4fsc IIC etc. L * (WE 51fi
O(d)1), K at which the phase at the sampling point 84m becomes the reference phase 00 (180°) is the average value of the digital values at the sampling point 34m-1 (i=o, 1, 2.3). It is only necessary that the digital value of the sampling point 84m be equal to that of the sampling point 84m. That is, the reference phase deviation H = 84m-+ΣS4m-i -・-(3
), and if we control so that this H becomes zero.

As shown by the arrow in FIG. 6, the phase at one sampling point S4m is o' (xsOo).

In FIG. 4, this phase deviation detection circuit 1O includes an inverter 21 for inverting the digital composite video signal 4, a shift register 22, and a sampling point 84m-1 (i=o
, 1 , 2 , 3 ), an adder 23 for calculating the average value of the digital values, and the average value and the sampling point 84
and an adder 25 for calculating the difference from the digital value of m.

Next, a detection output F outputted from one or more frequency error detection circuits 9 and phase error detection circuits 10.

As shown in FIG. 4, H is added by an adder 11 and input to the gate hold circuit 12 at the primary stage. This gate hold circuit 12 holds the value when m = 4 in the equations (2) and (3) during the burst period in which the color burst signal is present until the next change.

Here &m=4 means that the color burst signal is 8~
Since there are 12 periods, the sampling point near the center has a large amplitude, and this rainbow can be obtained by counting the output Pn of the peak detection circuit 8 and calculating P4. The output of the gate hold circuit 12 is converted into an analog signal by the KD/A converter 13 as shown in FIG.
14, the voltage controlled oscillator 150 control voltage becomes the output of the upper voltage controlled oscillator 15, that is, the system reference clock 16.
control the frequency and phase of

According to this embodiment, a stable system reference clock 1 with a frequency four times that of the color burst signal and a constant phase is used.
You can get 6.

〔Effect of the invention〕

According to the present invention, it is possible to generate a system reference clock that has a wide pull-in range centering on a frequency that is an integral multiple of the color burst signal, and is stable in both one station wave number and one phase. This has the effect of providing a stable image with no unevenness in one color.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. Fig. 2 is a block diagram showing the peak detection circuit of Fig. 1, Fig. 3 is a waveform diagram showing the color burst signal, its sampling point, and the output signal of the peak detection circuit, and Fig. 4 is a block diagram showing the peak detection circuit of Fig. 1.
A block diagram mainly showing the configuration of the frequency error detection circuit and phase deviation detection circuit shown in FIG. 5, a waveform diagram for explaining the operation of the frequency error detection circuit, and FIG. 6 for explaining the operation of the phase deviation detection circuit. FIG. 1...Analog composite video signal. 2...Amplifier clamp circuit, 3...A/D converter. 4...Digital composite video signal. 7...System reference clock generation circuit. 8...Peak detection circuit. 9...Frequency error detection circuit. 10... Phase deviation detection circuit. 11... Adder. 12...Gate hold circuit. 13...D/A converter. 14...Low pass filter/amplifier circuit. 15...Voltage controlled oscillator. 16...System reference clock. 17, 22...shift register. 20...Output signal of the peak detection circuit. 23, 24, 25...Adder.

Claims (1)

[Claims] 1. A voltage-controlled oscillator; an analog-to-digital converter that samples a composite video signal including a color burst signal and converts it into a digital value using a clock signal output from the oscillator; and a voltage-controlled oscillator. A first means for detecting a frequency error between the frequency of the clock which is the output of the color burst signal and a frequency that is an integral multiple of the color burst signal, and a second means for detecting a phase deviation, and the outputs of the first and second means. It consists of an adder for synthesizing, and a digital-to-analog converter for converting the output of the adder into an analog voltage.
A clock generation circuit for a digital television receiver, characterized in that the output of an analog converter is applied to the voltage controlled oscillator to keep the oscillation frequency and phase constant. 2. In the clock generation circuit according to claim 1, the first and second means each detect a frequency error or phase deviation using four samples before and after a certain peak point of the color burst signal. A clock generation circuit for a digital television receiver, characterized by: 3. In the clock generation circuit according to claim 1, the first means includes a shift register for delaying the digitized color burst signal, and a shift register for delaying the digitized color burst signal and the shift register for delaying the digitized color burst signal. 1. A clock generation circuit for a digital television receiver, comprising an inverter and an adder for determining the difference between the signal and the output signal from the register. 4. In the clock generation circuit according to claim 1, the second means includes a shift register for delaying the digitized color burst signal, and a shift register for delaying the digitized color burst signal, and using the delayed output to generate a signal between four samples. A clock for a digital television receiver, comprising an adder for determining an average value, and an inverter and adder for determining a difference between the average value and a sampled value of a current color burst signal. generation circuit.