JPH0262961B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM demodulation circuit, and more particularly to an FM demodulation circuit that performs demodulation using digital arithmetic processing.

[Conventional technology]

When demodulating an FM (frequency modulation) signal, the input modulation signal is superimposed on the demodulation output, so conventionally a filter was placed after the demodulation circuit to separate and remove the modulation signal component. However, for example
The carrier wave band is wide and the carrier wave frequency is low, such as that used in the image recording method of VTR.
In the case of the so-called low carrier FM method, as shown in Figure 1, the lower sideband of the FM signal 11 and the demodulated output 1
If the high frequency components of 2 (video signals) overlap as shown by diagonal lines, the FM signal components may pass through the demodulation circuit and filter and cause beat disturbances. This phenomenon is generally referred to as feedthrough in the demodulation circuit.

To prevent such feedthrough,
It becomes impossible to lower the frequency of the FM signal too much. In other words, even though the original bandwidth of the transmission system is wide,
The frequency of the FM signal must be increased by the bandwidth of the demodulated output, and as a result, there is a problem in that only about 2/3 of the originally usable transmission band can be used.

On the other hand, the above-mentioned problem can be solved if FM demodulation is performed by digital calculation as described in Japanese Patent Laid-Open No. 140706/1983. However, in this known example, the FM demodulation output is obtained by measuring the number of zero crosses in the sampled FM signal and calculating the reciprocal of the time interval until it reaches a certain number. The carrier frequency must be sufficiently high relative to the frequency of the modulating input signal, and the carrier frequency must be low enough to be close to the frequency of the modulating input signal.
It is difficult to apply this method to demodulating FM signals using the FM method. In other words, in the low-carrier FM method, the time interval between zero-crossing points of the FM signal changes greatly depending on the modulation input signal, but in the known method, this time interval cannot be measured, and the correct demodulated output cannot be measured. is not obtained.

[Problem to be solved by the invention]

As mentioned above, in conventional FM demodulation circuits using digital arithmetic processing, the FM demodulation output is obtained by calculating the reciprocal of the time interval until the number of zero crosses in the FM signal reaches a certain number. For,
There was a problem in that it was difficult to apply to demodulating FM signals using low carrier FM methods.

The present invention can perform demodulation of FM signals using a low carrier FM method using digital arithmetic processing.
The purpose is to provide an FM demodulation circuit.

[Means to solve the problem]

The FM demodulation circuit of the present invention converts a frequency modulation signal into a digital signal, and in the FM demodulation circuit that performs demodulation by digital arithmetic processing, the FM demodulation circuit converts a frequency modulation signal into a digital signal. means for measuring a first time interval to a second sample point immediately before the second zero cross point by clock counting; the second zero cross point is estimated by interpolation from the sample point immediately before the second zero cross point, and the second zero cross point is estimated by interpolation from the second sample point and the sample point immediately after the second zero cross point, and means for measuring a second time interval between the cross point and the first sample point and a third time interval between the second zero cross point and the second sample point; and means for calculating a time interval between zero cross points by adding the second and third time intervals, and outputting a digital value representing the time interval as a digital signal corresponding to the demodulated output of the frequency modulated signal. It is characterized by

[Effect]

Since the FM demodulation circuit of the present invention basically measures the time interval between zero cross points, a good demodulation output can be obtained even when the carrier frequency is low.

In the present invention, the first, second and third
By adding the time intervals of , the time interval between zero cross points can be determined with high accuracy.

That is, since the first time interval is determined by the precision of the clock, it can be measured with extremely high precision if it is generated by a clock and a crystal oscillator. On the other hand, since the zero crossing points for the second and third time intervals are determined by interpolation, they can be measured with an accuracy equivalent to the quantization accuracy of the digital signal.

〔Example〕

FIG. 2 shows the configuration of an FM demodulation circuit according to an embodiment of the present invention, in which an input terminal 21 receives a modulation signal, for example, an FM demodulation circuit using the aforementioned low carrier FM method.
A signal is input. This modulated signal is input to the A/D converter 22. The A/D converter 22 samples the input modulation signal using a sampling clock supplied from the clock generating circuit 23, and outputs a digital signal having an appropriate number of bits. Although the clock generating circuit 23 may generate a clock with a constant period regardless of the input, it is more preferable to generate a clock synchronized with the input modulation signal.

FIG. 3 shows an example of the configuration of a clock generation circuit 23 that uses a PLL (phase lock loop) to generate a clock synchronized with an input modulation signal.
The input modulation signal 31 and the output signal from the 1/N frequency divider 35 are multiplied by a multiplier 32 for phase comparison, and the output is passed through a low-pass filter 33 to a voltage controlled oscillator (VCO) 34 as a control voltage. The output of this VCO 34 is supplied to the 1/N frequency divider 35.
By feeding multiplier 32 through
It is configured to obtain a clock 36 that is synchronized with the input modulation signal 31 from the VCO 34 and has a frequency N times the carrier frequency of the modulation signal 31.

On the other hand, the digital signal output from the A/D converter 22 is supplied to the digital arithmetic circuit 24,
Here, a digital signal corresponding to the demodulated output of the input modulated signal is generated. The digital signal outputted from the digital arithmetic circuit 24 is converted into an analog signal by a D/A converter 25, and taken out as a demodulated signal via an output terminal 26.

For example, when the input modulation signal is an FM signal, the digital arithmetic circuit 24 converts A/A as shown in FIG. 4a.
The time interval between zero cross points of the digital signal from the D converter 22, that is, between P ₁ and P ₂ , between P ₂ and P ₃ ...
It is configured to sequentially measure the time intervals T _x of , and output count values representing these time intervals as a digital signal corresponding to the demodulated output. FM
Since the signal has information in the form of frequency deviation, that is, periodic change, the time interval between zero crossing points is measured as described above, and the digital signal representing the time interval is sent to the D/A converter 25. The operation of converting to an analog signal is nothing but demodulation operation. here,
Since the target digital signal is a temporally discrete sampling sequence, zero-crossing point detection requires
This cannot be done directly from the digital signal output from the A/D converter 22. Therefore, in this embodiment, the zero-crossing point is estimated by interpolation, and the above-mentioned time interval is measured based on it.

That is, as shown in Fig. 4b, when determining the time interval between zero cross points P ₁ and P ₂ , first, the sample point (zero cross point P) immediately after the polarity of the digital signal changes from negative to positive. Measure the time interval T ₀ from the next sample point B ₁ (the next sample point _after 1) to the sample point A ₂ immediately before the polarity changes (the sample point before the zero cross point P ₂ ). And the zero cross point
Estimated by interpolation from the digital signal values of P ₁ , P ₂ and the two positive and negative sample points that sandwich them, and the time interval between sample point B ₁ and the immediately preceding zero cross point P ₁
T ₁ and the time interval T ₂ between the sample point A ₂ and the immediately following zero cross point P ₂ are measured. These time intervals T ₁ and T ₂ can be determined by T ₁ =B ₁ /(A ₁ +B ₁ ) and T ₂ =A ₂ /(A ₂ +B ₂ ), respectively. The three time intervals obtained in this way
By adding T ₀ , T ₁ , and T ₂ , the time interval T _x between zero cross points P ₁ and P ₂ can be found.

FIG. 5 shows a specific example of the configuration of the digital arithmetic circuit 24 based on this principle. In FIG. 5, a digital signal 41 output from the A/D converter 22 in FIG. The timing of the polarity change is detected. The detection pulse of the polarity change detection circuit 42 is applied to a counter 43 as a reset pulse and to a latch circuit 44 as a latch pulse. However, it is desirable that the reset pulse to the counter 43 be slightly delayed from the timing of the latch pulse to the latch circuit 44. The counter 43 measures the time interval T ₀ in FIG. 4b by counting clocks having a constant period, in this example the same period as the sample point interval of the digital signal 41.

Note that the polarity change detection circuit 42 is configured as shown in FIG. 4b, for example.
Detection pulses are generated at the sample point next to the zero cross point _P1 and the sample point next to the zero cross point _P2 of the digital signal 41 in the counter 43.
counts the clocks over the time T ₀ +τ (τ is the sample interval of digital signal 41) between these sample points. In this case, assuming that the clock to the counter 43 has the same period as the sample point interval of the digital signal 41, the counter 43 will output (T ₀ /τ)
Since +1 clocks are counted, if the counted value is taken as _T0 , an error of τ corresponding to a counted value of "+1" will occur. However, when the counter 43 is reset, the content is not "0" but "-".
1'' (this is a problem of how to set the initial value of the counter, so it can be easily realized), such an error will not occur and T ₀ can be measured correctly.

The measured value of T ₀ obtained by the counter 43 in this way is latched in the latch 44 at a timing immediately before the counter 43 is reset next time, and the upper bit output 45 regarding the time interval T _x between the zero cross points P ₁ and P ₂ is output. becomes.

On the other hand, the digital signal 41 from the A/D converter 22 is further input to latches 47 and 48 via a one-sample delay circuit 46. The latch 47 uses the detection pulse of the polarity change detection circuit 42 as a latch pulse, and the latch 48 uses a pulse obtained by delaying this detection pulse by one sample delay circuit 49 as a latch pulse, and performs a latching operation. As a result, the values A ₁ and A ₂ are sequentially latched in the latch 47, and the values B ₁ and B ₂ are sequentially latched in the latch 48. The outputs of these latches 47, 48 are:
It is commonly applied to arithmetic circuits 50 and 51 for calculating time intervals T ₂ and T ₁ in FIG. 4b, respectively. Then, the output of the arithmetic circuit 51 is latched by a latch 53 to which the output pulse of the 1-sample delay circuit 52, which further delays the output pulse of the 1-sample delay circuit 49, is applied as a latch pulse. The output of this latch 53 and the output of the arithmetic circuit 50 are added by an adder 54. This causes the time interval in FIG. 4b from adder 54 to
The lower bit output 55 regarding T _x is the zero cross point.
Obtained immediately after the next sample point of P ₂ .

In other words, the polarity change detection circuit 42 detects the zero cross point.
When the next sample point of P ₁ is detected, at this point the detection pulse of the polarity change detection circuit 42 is set to latch 4.
7 is applied as a latch pulse, and this detection pulse is further delayed by a one sample delay circuit 49, and a pulse is applied as a latch pulse to latch 48.The inputs of latches 47 and 48 are one sample delay circuit 46 which converts the digital signal 41 into one sample. Since the signals are delayed by the same amount, the values of A ₁ and B ₁ are latched in latches 47 and 48, respectively. At this time,
The arithmetic circuit 50 outputs A ₁ /(A ₁ +B ₁ ), and the arithmetic circuit 51 outputs B ₁ /(A ₁ +B ₁ ). Next, a latch pulse is applied from the one sample delay circuit 52 to the latch 53 with a further delay of one sample, so the latch 53 latches B ₁ /(A ₁ +B ₁ ), which is the output of the arithmetic circuit 51, and the next It is held until the arrival of the latch pulse.

Next, the polarity change detection circuit 42 detects the zero cross point P ₂
When the next sample point is detected, at this point, the detection pulse of the polarity change detection circuit 42 is applied to the latch 47 as a latch pulse, and this detection pulse is further delayed by the one sample delay circuit 49, and the pulse is applied to the latch 48 as a latch pulse. Therefore, the values of A ₂ and B ₂ are latched in latches 47 and 48, respectively. At this time, the arithmetic circuit 50 outputs
A ₂ /(A ₂ +B ₂ ), and from the arithmetic circuit 51, B ₂ /(A ₂
+B ₂ ) are output respectively. The latch from the adder 54 is held in the latch 53 first.
B ₁ /(A ₁ +B ₁ ) is the output of the arithmetic circuit 50.
The sum of A ₂ /(A ₂ +B ₂ ), ie, the value of T ₁ +T ₂ , is output as the lower bit output 55 for the time interval T _x .

The upper and lower bit outputs obtained in this way 4
5 and 55 are combined, and a count value representing the time interval T _x is taken out as an output 56 of the digital arithmetic circuit 24. In this case, the time interval is the A/D converter 2
Since it can be determined with the same accuracy as the conversion accuracy of 2, A/D
The frequency of the sampling clock supplied to the converter 22 may be a value defined by the sampling theorem, that is, twice or more the highest frequency of the input modulation signal.

In this way, after converting the input modulation signal to a digital signal, a digital signal corresponding to the demodulated output is generated by digital calculation, and this is converted to an analog signal to obtain the demodulated output. , there is no feed-through as seen in demodulation circuits using conventional analog processing, so for example, as shown in Figure 1, the modulation signal (FM
Even if the frequency spectra of signal) 11 and demodulated output 12 partially overlap, stable demodulation without beat disturbance etc. is possible. Furthermore, when the lower sideband of the modulated signal 11 and the demodulated output 12 completely overlap as shown in FIG. 6a, and furthermore, as shown in FIG. Stable and good demodulation is possible even in a case where the demodulated output 12 almost overlaps with the one in which the demodulated output 12 is limited to a shape close to a single sideband. In this way, the utilization efficiency of the transmission band is significantly improved.

FIG. 7 shows another embodiment of this invention,
The digital signal input to the input terminal 21 is made into a square wave by the limiter 71, and further integrated by the integrator 72 to make it into a triangular wave as shown in FIG.
The signal is input to the A/D converter 22. In this way, it is possible to more accurately estimate the zero cross points by interpolation as explained with reference to FIG. 4B, and even better demodulation is possible.

Furthermore, in the above explanation, in order to estimate the zero-crossing point of the output signal of the A/D converter 22, interpolation was performed by regarding the waveform near the zero-crossing point as a straight line.
It is also possible to shorten the sampling interval of the D converter 22, assume that the input modulation signal waveform is a sine wave, and calculate the zero-crossing point as the zero-crossing point of the sine wave.

Note that the input FM modulation signal waveform is directly converted to A/
It is conceivable to measure the period of the FM modulation signal and convert it into a digital signal instead of converting it into a digital signal using a D converter. However, in that case, A/D
When the number of quantization bits required for conversion is n, it is necessary to measure the period of the input modulation signal with a precision of 1/2 ⁿ . In other words, a clock with a frequency 2 ⁿ times the frequency deviation of the FM signal is required. As an example, in the currently commonly used VTR,
FM carrier frequency is about 8MHz, frequency deviation is ±
Since it is about 1MHz, the frequency change range is 7~
Corresponding to 9MHz, the period change range is approximately 159 to 111ns
Therefore, the change width is 48 ns. If we were to convert this to an 8-bit digital signal, it would be 48ns/ ²⁸
= 0.187ns, requiring a clock frequency of 5.3GHz. On the other hand, according to the previous embodiment, A/
As mentioned above, the frequency of the clock for D conversion should be at least twice the highest frequency of the modulation signal.
Taking the case of the VTR mentioned above as an example, 18MHz is sufficient.

〔Effect of the invention〕

As described above, according to the present invention, the low carrier waves used in VTRs are
Even FM signals with low carrier frequencies, such as those in the FM system, can be successfully demodulated by digital calculation processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the frequency spectrum of the modulation signal and demodulation output in the low carrier FM method, FIG. 2 is a diagram showing the configuration of a demodulation circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing the clock frequency spectrum in the same embodiment. FIG. 4a and b are diagrams for explaining the operating principle of the digital arithmetic circuit in the same embodiment. FIG. 5 is a diagram showing a specific example of the configuration of the digital arithmetic circuit. , FIGS. 6a and 6b are diagrams showing frequency spectra of a modulated signal and demodulated output suitable for the demodulation circuit of the present invention, and FIG. 7 is a diagram showing the configuration of a demodulation circuit according to another embodiment of the invention.
FIG. 8 is a diagram showing the waveform of a modulation signal input to the A/D converter in the same embodiment. DESCRIPTION OF SYMBOLS 11... Modulation signal, 12... Demodulation output, 21... Modulation signal input terminal, 22... A/D converter, 23... Clock generation circuit, 24... Digital calculation circuit, 25
...D/A converter, 26...output terminal, 71...limiter, 72...integrator.

Claims (1)

[Claims] 1. In an FM demodulation circuit that converts an input frequency modulation signal into a digital signal and demodulates it by digital arithmetic processing, a first sample point immediately after the first zero cross point of the digital signal means for measuring a first time interval from the time to the second sample point immediately before the second zero cross point by clock counting; the second zero cross point is estimated by interpolation from the sample point immediately before the zero cross point, the second zero cross point is estimated by interpolation from the second sample point and the sample point immediately after the second zero cross point, and The second sample point between the zero crossing point of
and a third time interval between the second zero crossing point and the second sample point; and adding the first, second and third time intervals to determine the zero crossing point. and means for calculating a time interval between and outputting a digital value representing the time interval as a digital signal corresponding to a demodulated output of the frequency modulated signal.
FM demodulation circuit. 2. The method according to claim 1, wherein the frequency modulation signal is converted into a triangular wave.
FM demodulation circuit. 3. The FM demodulation circuit according to claim 1 or 2, wherein the frequency modulation signal is modulated by a low carrier frequency modulation method.