JPH0530521A - Sampling clock generating circuit - Google Patents

Abstract

PURPOSE:To digitize a sampling clock generating circuit synchronized with an optional phase of a color burst signal in an NTSC signal. CONSTITUTION:A phase difference between a subcarrier and a sampling clock is computed by a subcarrier phase detecting circuit 5 based upon subcarrier data obtained by A/D converting a subcarrier signal obtained from an NTSC signal by a color burst control PLL circuit 3 and added to an optional phase value obtained by a phase shifting circuit and the added value is D/A converted to constitute a loop for controlling a VCO 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a sampling clock generation circuit used when sampling an image signal. Particularly, the first invention relates to a clock generation circuit for generating a sampling clock which is phase-synchronized with the color burst axis of an NTSC composite image signal, and the second invention is a sampling circuit which is phase-synchronized with an arbitrary phase of a color burst of an NTSC composite image signal. The present invention relates to a clock generation circuit that generates a clock.

[0002]

2. Description of the Related Art Conventionally, a clock generating circuit of this type has constituted a PLL circuit by an analog circuit.

[0003]

Since such a conventional clock generation circuit has an analog circuit configuration, it has poor stability and requires adjustment, and since it is composed of analog components, it has a drawback that it is difficult to form an LSI. .

The present invention eliminates such drawbacks, and an object of the present invention is to provide a sampling clock generating circuit partially digitized.

[0005]

The first invention is NTS.
In a sampling clock generation circuit having an input terminal for inputting a C composite image signal and an output terminal for outputting a sampling clock signal for sampling the NTSC composite image signal, a phase is applied to the color burst signal of the NTSC composite image signal. Means for generating a synchronized subcarrier signal, means for performing analog-digital conversion on the subcarrier signal with a sampling clock signal and outputting subcarrier data, and the position of the subcarrier signal and the sampling clock signal from the subcarrier data Means for calculating a phase difference and outputting it as phase difference data, means for digital-analog converting this phase difference data and outputting it as a frequency control signal, and a frequency control signal having a center frequency that is an integral multiple of the subcarrier signal. To Flip and characterized by comprising a means for outputting the center frequency as a variable and the sampling clock signal.

A second invention is a sampling clock generation circuit having an input terminal for inputting an NTSC composite image signal and an output terminal for outputting a sampling clock signal for sampling the NTSC composite image signal. Means for generating a subcarrier signal phase-synchronized with the color burst signal of the composite image signal, means for controlling the amplitude of the subcarrier signal to a predetermined amplitude and outputting as a new subcarrier signal, and the new subcarrier signal Means for analog-digital converting the sampling clock signal to output subcarrier data, and means for calculating the phase difference between the new subcarrier signal and the sampling clock signal from the subcarrier data and outputting it as phase difference data, This phase difference data Means for adding phase shift data corresponding to a predetermined phase difference to the new subcarrier signal and outputting it as new phase difference data, and digital-analog converting this new phase difference data and outputting it as a frequency control signal. And means for having a center frequency that is an integral multiple of the new subcarrier signal and varying the center frequency according to the frequency control signal and outputting the sampling clock signal.

[0007]

[Function] NTS is controlled by the color burst control PLL circuit 3.
Using the subcarrier data obtained by AD-converting the subcarrier signal obtained from the C signal, the subcarrier phase detection circuit 5 calculates the phase difference between the subcarrier and the sampling clock, and an arbitrary phase amount by the phase shift circuit is calculated. A loop for controlling the VCO 17 by adding and performing DA conversion on this is configured.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of the first invention. In this figure, 1 is an input terminal for inputting an NTSC composite image signal, 2 is an output terminal for outputting a sampling clock of nf _sc phase-synchronized with a color burst signal, and 3 is a phase for a color burst signal of an NTSC composite image signal 0103. Synchronized subcarrier signal 030
The color burst control PLL circuit 4 for generating 4 outputs the voltage controlled oscillator (hereinafter, referred to as a subcarrier signal 0304) having a center frequency that is an integral multiple (n times) of the subcarrier signal 0304 which is the output signal of the color burst control PLL circuit 3.
An AD conversion circuit for performing AD conversion with a sampling clock signal 0704 which is an output of VCO), a subcarrier phase detection circuit 5 for calculating a phase difference between the subcarrier signal 0304 and the sampling clock signal 0704 from the subcarrier data 0405, 6 Is the phase difference data 050
Reference numeral 6 is a DA conversion circuit for performing DA conversion, and reference numeral 7 is a VCO controlled by the output signal 0607 of the DA conversion circuit. The color burst control PLL circuit 3 extracts the color burst portion from the NTSC composite video signal and generates a continuous subcarrier signal 0304 which is phase-synchronized with this, and the AD conversion circuit 4 outputs the sampling clock 070.
AD conversion is performed at 4 (nf _sc ) to obtain subcarrier data. Further, from this subcarrier data, the subcarrier phase detection circuit 5 calculates the phase difference between the sampling clock and the subcarrier signal, the DA conversion circuit 6 performs DA conversion, and the VCO is controlled by this analog signal. With the above loop configuration, it is possible to obtain a sampling clock phase-synchronized with the color burst of the NTSC composite image signal.

FIG. 4 is a diagram for explaining the principle of the second invention. In this figure, reference numeral 1 is an input terminal for inputting an NTSC composite image signal, 2 is an output terminal for outputting a sampling clock that is n times as large as f _sc in phase with an arbitrary phase of the color burst signal, and 3 is an NTSC composite image signal. Color burst control PL for generating a subcarrier signal 0308 which is phase-synchronized with the color burst signal 0103
L circuit, 8 is an automatic gain control circuit (hereinafter, referred to as an automatic gain control circuit for controlling the subcarrier signal 0308 to a predetermined constant amplitude A).
4 is a subcarrier signal 080 which is an output signal of the AGC circuit 8.
An AD converter circuit that performs AD conversion with a sampling clock signal 0704 that is an output of a VCO having a center frequency that is an integral multiple (n times) of 4 is a phase difference between the subcarrier data 0405 and the subcarrier signal 0804 and the sampling clock signal 0704. And a subcarrier phase detection circuit for outputting as phase difference data, 9 is a phase shift circuit for outputting phase shift data 0903 corresponding to an arbitrary phase difference with respect to the color burst signal 0804 of amplitude A, 3
0 is an adder for adding the phase difference data 0530 which is the output of the subcarrier phase detection circuit 5 and the phase shift data 0930 which is the output of the phase shift circuit 9, and 6 is DA conversion of the phase difference data 3006, and analog frequency control Signal 06
DA conversion circuit for outputting 07, 7 for frequency control signal 06
VCO controlled by 07. The color burst control PLL circuit 3 extracts the color burst portion from the NTSC composite image signal and generates a continuous subcarrier signal 0308 which is phase-synchronized with the color burst portion.
The circuit 8 keeps the amplitude constant and obtains a subcarrier signal. Further, this signal is AD-converted by the AD conversion circuit 4 at the sampling clock 0704 (nf _sc ) to obtain subcarrier data 0405. Further, the subcarrier phase detection circuit 5 calculates the phase difference between the sampling clock and the subcarrier signal from the subcarrier data to obtain the phase difference data. Further, the phase shift circuit 9 adds phase shift data corresponding to a predetermined phase difference to the subcarrier signal, and DA conversion is performed by the DA conversion circuit 6 as phase data, whereby the phase is synchronized with an arbitrary phase of the color burst. The sampling clock can be obtained.

FIG. 2 is a block diagram showing this embodiment. In this embodiment, the sampling clock is 4f _sc with n = 4. The AD conversion circuit 4, the DA conversion circuit 6 and the VCO 17 in FIG. 1 have a one-to-one correspondence with that of FIG. The color burst control PLL circuit 3 is composed of the burst sampling circuit 10, the sync separation circuit 13, the phase comparison circuit 11 and the VCO 12 shown in FIG. Further, the subcarrier phase detection circuit 5 includes registers 14, 15, 1
8, an adder 16, a subtractor 17, an AND circuit 21 for performing a logical product, a frequency dividing circuit 22 for dividing a 4f _sc clock by 4, a counter 23 reset by a horizontal synchronizing signal 1323 and counted by a 4f _SC clock, AD conversion It is composed of a positive / negative determination circuit 20 and an integration circuit 19 for determining whether the inclination of the sample point position is positive or negative. That is, as shown in FIG. 1, this first embodiment comprises an input terminal 1 to which an NTSC composite image signal is input and an output terminal 2 which outputs a sampling clock signal for sampling the NTSC composite image signal. Further, as a feature of the present invention, a color burst control PLL circuit 3 which is a means for generating a subcarrier signal phase-synchronized with the color burst signal of the NTSC composite image signal, and a sampling clock signal for the subcarrier signal. AD conversion circuit 4 which is means for analog-to-digital conversion and outputs subcarrier data, and means for calculating the phase difference between the subcarrier signal and the sampling clock signal from the subcarrier data and outputting as phase difference data. Subcarrier phase detection circuit 5 and this A DA conversion circuit 6 which is means for digital-analog converting the difference data and outputting it as a frequency control signal, and a center frequency which is an integral multiple of the subcarrier signal and which is varied in accordance with the frequency control signal. And a VCO 7 which is means for outputting as a sampling clock signal.

Next, the operation of this embodiment will be described. Figure 2
Meanwhile, the sync separation circuit 13 separates the sync signal from the image signal 0110, and outputs a horizontal sync signal 1323 and a burst flag signal 1310 indicating the position of the color burst.
Further, the burst sampling circuit 10 extracts only the color burst signal portion from the image signal 0110 using the burst flag signal 1310. The phase comparison circuit 11 performs a phase comparison using the color burst signal 1011 and the color subcarrier (frequency is f _sc ) signal 1211 which is the output of the VCO 12, and controls the VCO 12 to phase the color burst signal. It is possible to obtain synchronized continuous subcarrier signals 1204. The subcarrier signal 1204 is AD-converted by the AD conversion circuit 4 at a frequency (4f _sc ) which is four times the subcarrier frequency f _sc .

Next, the operation of detecting the phase between the subcarrier signal and the sampling clock from the AD-converted subcarrier data 0414 will be described with reference to FIG. FIG. 3 shows how the color subcarrier signal is sampled at a sampling clock of 4 f _sc . The object of the present invention is to obtain a sampling clock that is phase-synchronized with the color burst, that is, it is achieved by performing control so that the sampling phase marked with a circle in FIG. Specifically, in FIG. 3, the subcarrier signal data 0414 is filtered, the output thereof is integrated, and the VCO 7 is controlled by the positive, negative, or zero of the value. For example, in the case of the sample phase indicated by x, the integrated output has a negative value, so that the oscillation frequency of the VCO 7 is controlled so that the sampling point is on the right side.

Further, in the case of the sample phase marked with □, the integrated output becomes positive, so that the oscillation frequency of the VCO 7 is raised and the control is performed so that the sampling point comes to the left side.

In FIG. 2, the registers 14 and 15 and the adder 16 and the subtractor 17 constitute a filter having the following coefficients.

(-1 2 -1) / 4 However, the filter coefficient calculation is performed by bit shift, and only the description such as x1 / 4 is shown in FIG. In addition, the positive / negative determination circuit 20 detects a rising sample point in order to integrate only the rising phase filter output, and the positive / negative control signal 20 that validates only this sampling point.
21 is output. Further, the counter 23 counts in synchronization with the horizontal synchronizing signal 1323 and outputs an effective sample control signal 2321 for obtaining an integrated value obtained by filtering only effective samples in one line. Therefore, the filter output 1718 is latched by the AND circuit 21 in the register 18 by using the signal 2118 obtained by ANDing the positive / negative control signal 2021, the effective sample control signal 2321 and the signal 2122 obtained by dividing 4f _sc by 4 to obtain 1 The integrator circuit 19 can integrate the filter outputs of several rising samples in the line. The DA conversion circuit 6 DA-converts the integrated value 1916 to convert it to the VCO 17
To control the sampling clock.

Next, an embodiment of the second invention will be described with reference to the drawings. FIG. 5 is a block diagram showing this embodiment. In this embodiment, the sampling clock is n
= 4 and 4f _sc . AD conversion circuit 4, D in FIG.
The A conversion circuit 6, VCO 17, AGC 8, phase shift circuit 9 and adder 30 have a one-to-one correspondence with that of FIG. The color burst control PLL circuit 3 is composed of the burst extraction circuit 10, the sync separation circuit 13, the phase comparison circuit 11 and the VCO 12 shown in FIG. 5, and the subcarrier phase detection circuit 5 includes the registers 14, 15, 18 and addition. 16, a subtractor 17, AND circuits 21 and 4 for performing a logical product
A frequency dividing circuit 22 that _{divides the} f _sc clock by 4, a counter 23 that is reset by the horizontal synchronizing signal 1323 and is counted by the 4 f _sc clock, a positive / negative determination circuit 20 and an integration circuit that determine the positive / negative of the slope of the AD-converted sample point position. 1
It is composed of 9. Further, the position of the adder 30 is slightly changed from that of FIG.

That is, in this embodiment, as shown in FIG. 1, an input terminal 1 for inputting an NTSC composite image signal and an output terminal 2 for outputting a sampling clock signal for sampling the NTSC composite image signal are provided. Further, as a feature of the present invention, the above N
A color burst control PLL circuit 3 that is a means for generating a subcarrier signal that is phase-synchronized with the color burst signal of the TSC composite image signal, and a new subcarrier signal by controlling the amplitude of this subcarrier signal to a predetermined constant amplitude. AGC8 which is a means for outputting as
An AD conversion circuit 4 which is means for analog-digital converting this new subcarrier signal with a sampling clock signal and outputting subcarrier data, and a phase difference between the new subcarrier signal and the sampling clock signal from this subcarrier data. And a subcarrier phase detection circuit 5 which is a means for outputting as phase difference data,
This phase difference data is added to the new subcarrier signal with phase shift data corresponding to a predetermined phase difference, and is output as new phase difference data. D / A conversion circuit 6 which is a means for digital-analog converting the phase difference data and outputting it as a frequency control signal, and a center frequency which is an integral multiple of the new subcarrier signal and which has a center frequency in accordance with the frequency control signal. And a VCO 7 which is a means for outputting the sampling clock signal as the sampling clock signal.

Next, the operation of this embodiment will be described. Figure 5
Meanwhile, the sync separation circuit 13 separates the sync signal from the image signal 0110, and outputs a horizontal sync signal 1323 and a burst flag signal 1310 indicating the position of the color burst.
Further, the burst sampling circuit 10 extracts only the color burst signal portion from the image signal 0110 using the burst flag signal 1310. The phase comparison circuit 11 performs a phase comparison using the color burst signal 1011 and the color subcarrier (frequency is f _sc ) signal 1211 which is the output of the VCO 12, and controls the VCO 12 to phase the color burst signal. A synchronized continuous subcarrier signal 1208 can be obtained. The sub-carrier signal 1208 is controlled to a constant amplitude A by the AGC circuit 8, four times the frequency of the subcarrier frequency f _sc in the AD converter 4 as the color burst signal 2 (4
f _sc ) is AD-converted to obtain subcarrier data 0414.

Next, the operation of detecting the phase between the subcarrier signal and the sampling clock from the subcarrier data 0414 will be described with reference to FIG. FIG. 6 shows how the color subcarrier signal is sampled at a sampling clock of 4 f _sc . Waveform 1 in the figure is the color burst signal 0804 itself,
The waveform 2 is obtained by subtracting the phase shift data for the phase shift (α in the example of this figure) by the phase shift circuit 9, and is controlled by this waveform in the control loop. The object of the present invention is to obtain a sampling clock that is phase-synchronized with the color burst, that is, it can be achieved by performing control so that the sampling phase indicated by a circle in FIG. Specifically, in FIG. 6, the subcarrier data 0414 is filtered, its output is integrated, and its value is positive, negative,
Control VCO 7 by zero. For example, in the case of the sample phase indicated by x, the integrated output has a negative value, so VCO7
The control is performed so that the oscillation frequency of is low and the sampling point is on the right side.

Further, in the case of the sample phase marked with □, the integrated output becomes positive, so that the oscillation frequency of the VCO 7 is increased and the control is performed so that the sampling point comes to the left side. This control for waveform 1 is accomplished by adding the phase shift data 0930 to the filter output 1830.

In FIG. 5, the registers 14 and 15, the adder 16 and the subtracter 17 constitute a filter having the following coefficients.

(-1 2 -1) / 4 However, the filter coefficient calculation is performed by bit shift, and only the description such as x1 / 4 is shown in FIG. In addition, the positive / negative determination circuit 20 detects a rising sample point in order to integrate only the rising phase filter output, and the positive / negative control signal 20 that validates only this sampling point.
21 is output. Further, the counter 23 counts in synchronization with the horizontal synchronizing signal 1323 and outputs an effective sample control signal 2321 for obtaining an integrated value obtained by filtering only effective samples in one line. Therefore, the filter output 1718 is latched by the AND circuit 21 in the register 18 by using the signal 2118 obtained by ANDing the positive / negative control signal 2021, the effective sample control signal 2321 and the signal 2122 obtained by dividing 4f _sc by 4 to obtain 1 The integrator circuit 19 can integrate the filter outputs of several rising samples in the line. further,
The phase shift circuit 9 adds the phase shift data corresponding to the phase difference α from the amplitude A to the filter amplitude 1830 in the adder 30.
, The sampling point can be controlled to have the phase difference α. The DA conversion circuit 6 DA-converts the integrated value 1906 and outputs it to the VCO 17.
Controls the frequency of the sampling clock.

[0024]

As described above, according to the present invention, since a part of the conventional color burst clock PLL circuit is digitized, the stability is excellent, no adjustment is required, and further the LSI can be realized, so that the size can be reduced. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of a first embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a first embodiment of the present invention.

FIG. 3 is a waveform chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram showing the principle of the second embodiment of the present invention.

FIG. 5 is a block configuration diagram showing a configuration of a second embodiment of the present invention.

FIG. 6 is a waveform chart showing the operation of the second embodiment of the present invention.

[Explanation of symbols]

1 input terminal 2 output terminals 3 color burst control PLL circuit 4 AD conversion circuit 5 Subcarrier phase detection circuit 6 DA conversion circuit 7 Voltage controlled oscillator (VCO) 8 Automatic gain control circuit (AGC) 9 Phase shift circuit 10 Burst sampling circuit 11 Phase comparison circuit (phase comparison) 12 Voltage controlled oscillator (VCO) 13 Sync separation circuit 14, 15, 18 Register (D) 16 adder 17 Subtractor 19 Integrator circuit 20 Positive / negative judgment circuit 21 AND circuit (AND) 22 frequency divider (1/4) 23 Counter (CTR) 30 adder

Claims (2)

[Claims] 1. A sampling clock generation circuit having an input terminal for inputting an NTSC composite image signal and an output terminal for outputting a sampling clock signal for sampling the NTSC composite image signal, Means for generating a subcarrier signal phase-synchronized with the color burst signal; means for analog-digital converting the subcarrier signal with a sampling clock signal to output subcarrier data; and the subcarrier signal and the sampling from the subcarrier data. A means for calculating the phase difference with the clock signal and outputting it as phase difference data, a means for digital-analog converting this phase difference data and outputting it as a frequency control signal, and a center frequency that is an integral multiple of the subcarrier signal. Sampling clock generating circuit, characterized in that a means for outputting the center frequency according to the frequency control signal as a variable and the sampling clock signal. 2. A sampling clock generating circuit having an input terminal for inputting an NTSC composite image signal and an output terminal for outputting a sampling clock signal for sampling the NTSC composite image signal, Means for generating a subcarrier signal phase-locked to the color burst signal, means for controlling the amplitude of the subcarrier signal to a predetermined amplitude and outputting as a new subcarrier signal, and the new subcarrier signal for the sampling clock signal Means for analog-to-digital conversion and output of subcarrier data, means for calculating the phase difference between the new subcarrier signal and the sampling clock signal from this subcarrier data and outputting as phase difference data, and this phase difference data The above new A means for adding phase shift data corresponding to a predetermined phase difference to the subcarrier signal and outputting it as new phase difference data; a means for digital-analog converting this new phase difference data and outputting it as a frequency control signal; A sampling clock generation circuit having a center frequency that is an integral multiple of the new subcarrier signal, and means for varying the center frequency according to the frequency control signal and outputting it as the sampling clock signal. .