JP2823291B2 - SECAM type line identification circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a SECAM type line identification circuit effective as a SECAM switch collation circuit in a SECAM type color television receiver.

(Prior Art) There are three color television signal systems currently used in the world: NTSC, PAL, and SECAM. SECAM
The method is mainly adopted in communist countries and France.

In the SECAM system, two different color signal information (B-Y) signal and (R-Y) signal are frequency-modulated by different carrier waves, and are transmitted alternately line-sequentially every horizontal period. . On the receiver side, one horizontal period delay line and SE
A switching circuit called a CAM switch synchronizes the above two signals, and the (BY) signal is supplied to the (BY) demodulator and the (RY) signal is supplied to the (RY) demodulator. The color signal is reproduced. The SECAM switch is driven by the output of a flip-flop circuit that inverts every horizontal cycle. To correctly supply color signal information to each demodulator,
It is necessary that the inverted and non-inverted phases of the flip-flop circuit are correctly synchronized with the color signal information sent in a line-sequential manner.

To this end, an identity signal (ID signal) is transmitted in the SECAM system as information for identifying color signal information.

That is, the (BY) signal is frequency-modulated on a 4.25 MHz carrier, and the (RY) signal is frequency-modulated on a 4.46 MHz carrier, and transmitted line-sequentially. At the beginning, unmodulated carriers 4.25 MHz and 4.406 MHz are inserted as ID signals, respectively. The ID signal is determined on the receiving side by an ID identification circuit. The ID identification circuit performs an operation of extracting the ID signal, determining the frequency of the ID signal, and resetting the flip-flop circuit to return to a correct phase state.

FIG. 8 shows a conventional SECAM type color demodulation circuit.
The television signal input from an antenna (not shown)
The video signal is demodulated into a composite video signal by the video detection circuit, and only the chroma signal is input from the input terminal 1. The chroma signal is input to a color difference amplifier 7 and an ID amplifier 10 via a band-pass filter 6 called a bell filter. The color difference amplifier 7 takes in and amplifies the color difference signal using the gate pulse from the terminal 3, and the color difference signal is supplied to the color difference demodulation circuit 8. The color difference demodulation circuit 8 obtains a baseband color difference signal, and the color difference signal is input to the baseband processing circuit 9. In the baseband processing circuit 9,
De-emphasis processing is performed, and a (G-Y) signal is also obtained by matrix processing. This allows the output terminal
9 _1, 9 from _{2, 9 3, (R-} Y) signal, (G-Y) signal,
A (BY) signal is derived.

On the other hand, the ID signal is transmitted to the ID amplifier 10 using a gate pulse.
And is amplified and input to the ID demodulation circuit 11. The ID demodulation circuit 11 performs FM demodulation of the ID signal and performs baseband
Get the ID signal. This demodulated ID signal is supplied to the line determination circuit 12. The line determination circuit 12 determines whether the polarity of the demodulation ID signal and the output line pulse of the flip-flop circuit 13 match. If the polarity is opposite, an error pulse for inverting the polarity of the flip-flop circuit 13 is output, and the operation phase of the flip-flop circuit 13 is controlled to reverse. The output line pulse of the flip-flop circuit 13 is used in the color difference demodulation circuit 8 for sorting the (BY) signal and the (RY) signal input line-sequentially.

FIG. 9 shows the inside of the ID demodulation circuit 11 in more detail.

The input ID signal from the ID amplifier 10 is input to a phase comparator 15 and compared in phase with a signal from a voltage controlled oscillator (VCO) 16. Then, the comparison result is output as a demodulation ID signal and also input to the voltage-current converter 17. The voltage-current converter 17 has a resistor 18
The control current is generated by adding the conversion current of the voltage given by the control signal and supplied to the control terminal of the voltage controlled oscillator 16.
The voltage controlled oscillator 16 is configured so that the oscillation frequency changes linearly with respect to the control current. This demodulation system, generally called a phase locked loop for demodulation (PLL), utilizes the fact that the oscillation frequency of the oscillator is locked equally to the input signal frequency, and demodulates the voltage change on the input side of the voltage-current converter 17. It is used as output.

FIG. 10 is a characteristic diagram and signal waveform diagram shown for explaining the operation of the circuits of FIGS. 8 and 9.

As the ID signal, two of fOB and fOR having different frequencies are transmitted alternately in one horizontal cycle. Now, for the sake of explanation, an intermediate frequency between the frequencies foB and foR is referred to as foID.

Assuming that the initial oscillation frequency (free-run frequency) of the voltage controlled oscillator 16 of the ID demodulation circuit 11 is adjusted to foID by the resistor 18, the detection characteristic of the demodulation circuit is as shown in FIG. Extracted from the chroma signal of FIG.
The ID signal is as shown in FIG. 7C, and a signal obtained by demodulating the ID signal (demodulated ID signal) is f oR as shown in FIG.
When the pulse is positive, the pulse is negative, and when foB, the pulse is negative. Therefore, by comparing the polarities of the line pulse and the demodulated ID signal as shown in FIG. 7E, it is possible to determine whether or not the polarities of the two coincide. The line pulse is created by dividing the horizontal synchronization signal by 1/2.

As shown in the figure, if the polarities match, the result of the synchronous integration becomes a high level and no error signal is output to the flip-flop circuit 13.However, if the phases have opposite polarities, the result of the synchronous integration becomes a low level and an error occurs. Output a signal.

When the input ID signal does not exist, it can be considered that a black-and-white video signal is being broadcast. In this case, the result of the synchronous integration is “0”, and a direct current (DC) determined by the bias voltage in the discrimination circuit is obtained. DC) value. At this time, the line determination circuit 12 determines that the image is in the black and white state, outputs a color killer signal, and supplies the color killer signal to the baseband processing circuit 9.
The color difference signal output is cut off to prevent unnecessary signals from being output to the screen.

(Problems to be Solved by the Invention) According to the SECAM type line identification circuit described above, in order to set the free-run frequency of the voltage-controlled oscillator, the resistance 18
It is necessary to adjust using. Such adjustment of the volume increases the number of work steps in the manufacturing process of the television receiver, which leads to an increase in the cost of the receiver. In addition, there is a possibility that the adjustment point may shift due to temperature or aging,
It has the weakness of lacking long-term reliability.

Therefore, an object of the present invention is to provide a SECAM type line identification circuit that can eliminate adjustment components in an ID demodulation circuit.

[Constitution of the Invention] (Means for Solving the Problems) The present invention relates to a SECAM receiver for generating a reference signal having an intermediate frequency between two ID signals, and a phase locked loop circuit for the reference signal. Means for controlling the ID demodulation circuit to be at the center of the demodulation axis.

(Operation) By the above means, in the ID demodulation circuit, mechanical adjustment means for adjusting the center of the demodulation axis becomes unnecessary, and automatic adjustment control can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The chroma signal is
The signal passes through a band-pass filter 22 called a bell filter via an input terminal 21, and is input to a color difference amplifier 23 and an ID amplifier 27. The color difference amplifier 23 takes in and amplifies the color difference signal using the gate pulse from the terminal 26, and the color difference signal is supplied to the color difference demodulation circuit 24. The color difference demodulation circuit 24
Performs demodulation processing using a phase locked loop circuit.
The switching of the demodulation axis is realized by switching the carrier wave of f oB and f oR every line cycle by the line pulse. As a result, a baseband color difference signal is obtained from the color difference demodulation circuit 24, and the color difference signal is input to the baseband processing circuit 25.

In the baseband processing circuit 25, a de-emphasis process is performed, and a demodulated color difference signal is added or subtracted with a direct signal which is delayed by 1H in some cases without delay, and a (G-Y) signal is also obtained by matrix processing. Thus, from the output terminal _{25 1, 25 2, 25 3} , (R-Y) signal, (G-Y)
A signal, (BY) signal is derived.

On the other hand, the ID signal is generated by an ID amplifier 27 using a gate pulse.
And is amplified and input to the ID demodulation circuit 28.

Here, the ID demodulation circuit 28 is supplied with a reference signal foID from the color difference demodulation circuit 24 for demodulation axis adjustment. The reference signal foID plays an important role in making the ID demodulation circuit 28 unadjusted, as described later.

The ID demodulation circuit 28 demodulates the ID signal by FM and performs baseband ID demodulation.
Get the signal. This demodulated ID signal is supplied to the line determination circuit 29. The line determination circuit 29 determines whether the polarity of the demodulated ID signal and the output line pulse of the flip-flop circuit 30 are matched. If the polarity is reverse, an error pulse for inverting the polarity of the flip-flop circuit 30 is output, and the operation phase of the flip-flop circuit 30 is controlled to reverse. The output line pulse of the flip-flop circuit 30 is used in the color difference demodulation circuit 24 for sorting the (BY) signal and the (RY) signal input in a line-sequential manner.

 FIG. 2 shows the ID demodulation circuit 28 specifically.

The input ID signal is input to the phase comparator 33 via the input terminal 31. The reference signal foID is input to the phase comparator 38 via the input terminal 32. An oscillation output from a common voltage controlled oscillator (VCO) 37 is supplied to the phase comparators 33 and 38. The comparison result of the phase comparator 33 is output to the output terminal 34 as a demodulation ID signal and is input to the voltage-current converter 35. The voltage-current converter 35 supplies the converted current of the input voltage to the adder 36. The adder 36 is also supplied with the converted current from the voltage-current converter 39. The adder 36 adds two input conversion currents to generate a control current and supplies the control current to the control terminal of the voltage controlled oscillator 37.

The comparison result of the phase comparator 38 is input to the voltage-current converter 39. The voltage / current converter 39 supplies the converted current to the adder 36. Here, a key signal is supplied from the terminal 41 to the voltage / current converter 39, and the voltage / current converter 39 is controlled to be conductive or non-conductive by the key signal. Then, it operates to hold the control information in the conductive state in the capacitor 40 in the non-conductive state.

The above-described phase comparator 33, voltage-current converter 35, adder 3
6.The loop formed by the voltage controlled oscillator 37 is a phase locked loop for ID demodulation, and the loop of the phase comparator 38, the voltage / current converter 39, the adder 36, and the voltage controlled oscillator 37 is used for adjusting the reference demodulation axis. It is a phase locked loop.

FIG. 3 is a diagram shown to explain the operation of the above system.

It is assumed that the detection axis indicated by the solid line in FIG. 3A has been obtained before the adjustment. Extracted from the chroma signal in FIG.
The demodulated ID signal obtained by demodulating the ID signal (FIG. 10C) is as shown in FIG. 10D, and the detection output of foB is almost eliminated.

Therefore, it is assumed that a reference signal foID as shown in FIGS. 7A and 7E is given from the color difference demodulation circuit 24. A key signal is also provided in synchronization with the reference signal f oID. Then, the voltage-current converter 39 is activated by the key signal, a phase lock loop for adjustment works, and the oscillation frequency of the voltage-controlled oscillator 37 is pulled down to the same frequency as the reference signal foID. At this time, a detection output as shown in FIG. 3G appears at the output of the voltage-current converter 39, and this detection voltage is held by the capacitor 40.

Once the demodulation axis is pulled in by the reference signal, the free-running frequency of the voltage-controlled oscillator 37 is maintained thereafter, so that the demodulation axis is f as shown by the dashed line in FIG. An ideal demodulation axis centered on the oID. When the ID signal is demodulated in this state (after the automatic adjustment is completed), a demodulated ID signal vertically symmetric with respect to the reference level can be obtained as shown in FIG. . .

Next, a system for obtaining the reference signal foID from the color difference demodulation circuit 24 will be described.

FIG. 4 specifically shows the configuration of the color difference demodulation circuit 24. The chroma signal from the color difference amplifier 23 is input to the phase comparator 52 via the input terminal 51, and is compared in phase with the output of the voltage controlled oscillator 56. This comparison result is output to the output terminal 53 as a color difference signal demodulation output, and the voltage-current converter
Entered in 54. The conversion current obtained here is added to the adder 55
Is input to The output current of the current source 57 is constantly supplied to the adder 55, and the current source 5 is supplied to the adder 55 via switches 61 and 62.
Current from 8,59 is selectively supplied. The output current of the adder 55 is supplied to the control terminal of the voltage controlled oscillator 56 as a control current.

A loop formed by the phase comparator 52, the voltage-current converter 54, the adder 55, and the voltage-controlled oscillator 56 forms a phase-locked loop, and demodulates a color difference FM signal (that is, a chroma signal).

Chroma signals have different center frequencies for each line (foB
= 272fH, foR = 282fH), it is necessary to switch the demodulation axis to keep the black level of the demodulated color difference signal constant for each line. Therefore, in this embodiment, this is realized by changing the direct current (DC) value of the control current supplied to the voltage controlled oscillator 56 for each line. That is, normally, the current I OB from the current source 57 is supplied to the adder 55, and is added to the output current of the voltage-current converter 54.In the ID signal period, the current from the current source 58 is further added. In the (RY) signal period (foR period), the output current from the current source 59 is further added.

FIG. 5 is a characteristic and waveform diagram for explaining the operation of the above-described color difference demodulation circuit 24.

Now, when the current IoB is supplied to the adder 55, it is assumed that the oscillation frequency of the voltage control oscillator 56 is adjusted to be fOB ((BY) signal demodulation carrier).
Then, the detection characteristic DB when the current IoB is supplied is as shown in FIG. 7A, and the demodulated output when the (BY) signal is demodulated is as shown in FIG. To black level
The waveform is vertically symmetric with respect to Vref. Next, (R-
Y) When the signal is input, both the switches 61 and 62 are turned on. As a result, the detection characteristic DR becomes as shown in FIG. 7A, and becomes a demodulated output centered on the black level Vref as shown in FIG. Each output current of the current sources 58 and 59 is set to a current amount capable of shifting the frequency of foB by +5 fH, and according to the total current, a shift of +10 fH can be obtained. This is exactly f oR
(= FoB + 10fH), and the oscillation output at this time is (R−
Y) It can be used as a carrier for signal demodulation. The oscillation frequency at this time is 272fH + 5fH + 5fH = 282fH,
The center of the demodulation axis shifts to f oR as shown in FIG.

Key signals for controlling the switches 61 and 62 have timings as shown in FIGS. That is, both switches are turned on only during the (RY) signal period, and (B
-Y) Both are off in the signal period, and only one switch, for example, 61 is turned on in the ID signal period (blanking period).

During this period, the oscillator 56 outputs 272fH + 5fH = 277fH (= fo
ID). Accordingly, a change in the oscillation frequency of the voltage controlled oscillator 56 over several horizontal periods is as shown in FIG. Therefore, the oscillation output during the ID signal period can be taken into the ID demodulation circuit 28 from the color difference demodulation circuit 24 as the reference signal foID. With such a configuration, a reference signal for adjustment of the ID demodulation circuit 28 can be obtained without any trouble in the demodulation operation of the color difference signal.

In the above embodiment, when automatically adjusting the free-run frequency of the voltage control oscillator 37 in the ID demodulation circuit 28, attention was paid to comparing the phase of the ID signal with the reference signal foID. However, it is also possible to compare the demodulated output (voltage) when there is no signal with the demodulated output (voltage) when the reference signal foID is input, and to control the free-run frequency of the voltage-controlled oscillator so that there is no error. .

FIG. 6 shows another embodiment of the ID demodulation circuit.
Is attached. Input terminal 71 has an input ID signal, input terminal 72
Is supplied with a reference signal foID, and is selectively introduced into a phase comparator 74 by a switch 73. The phase comparator 74 compares the phase of the input signal from the switch 73 with the output signal of the voltage controlled oscillator 78, and derives the phase comparison result to the output terminal 75 as a demodulation ID signal.

The output terminal of the phase comparator 74 is connected to the voltage / current converter 76, the sample / hold circuit 79, and the comparator 81. The converted current of the voltage / current converter 76 is input to the adder 77, and is added to the current from the voltage / current converter 83. The output of the adder 77 is supplied as a control current to the control terminal of the voltage controlled oscillator 78, and the output of the voltage controlled oscillator 78 is supplied to the phase comparator 74.

The sample and hold circuit 79 samples the demodulated output with the key signal in the non-signal period supplied to the terminal 85, and holds the sampled output in the capacitor 80. The comparator 84 operates in response to the key signal supplied to the terminal 84 when the reference signal foID is input, and outputs a demodulated output (a demodulated output of the reference signal foID) and a capacity 80
And the voltage of. The error output of the comparator 81 is input to the voltage-current converter 83. The output current of the voltage / current converter 83 is input to the adder 77.

The loop of the phase comparator 74, the voltage-current converter 76, the adder 77, and the voltage-controlled oscillator 78 is a phase locked loop for ID demodulation, and the phase comparator 74, the sample-hold circuit 79, and the comparator 8
1. A loop formed by the voltage-current converter 83, the adder 77, and the voltage-controlled oscillator 78 is a loop for adjustment.

FIG. 7 is a characteristic and signal waveform diagram shown for explaining the operation of the above circuit.

Now, it is assumed that the free-run frequency of the voltage-controlled oscillator 78 has deviated from the frequency of the reference signal foID as shown in FIG. Then, the detection axis becomes as shown by the solid line,
When demodulating the ID signal extracted from the chroma signal shown in FIG. 7B (FIG. 10C), as shown in FIG.
Almost no demodulated output is obtained, and the line discriminating circuit at the subsequent stage cannot perform synchronous integration. The switch 73 selectively introduces the ID signal and the reference signal foID, and these signals exist in a time division manner as shown in FIG. Separately, in the sample and hold circuit 79, the demodulated output during the no signal period is sampled and held in the capacitor 80. FIG. 11G shows a key signal supplied to the comparator 81, and FIG. 11H shows a key signal supplied to the sample-and-hold circuit 79.

Here, when the reference signal foID is input, the voltage controlled oscillator 78 is phase-locked to the reference signal foID. At the same time, the comparator 81 compares the voltage held in the capacitor 80 with the demodulated output (I) of the reference signal foID, integrates the error voltage with the capacitor 82, and The rapid change is suppressed. However, due to the influence of the error voltage, the output current of the voltage-current converter 83 is changed.

Thus, when the reference signal foID is input, the voltage controlled oscillator 78 is controlled to a frequency at which no error voltage occurs in the comparator 81. That is, the level of the demodulated output when there is no signal and the level of the demodulated output when the reference signal is input are controlled to be the same.

As a result, the reference frequency of the voltage controlled oscillator 78 is adjusted, and the detection characteristic becomes a characteristic as shown by a dashed line in FIG. FIG. 11 (J) shows the demodulation obtained with this characteristic.
The ID signal is shown.

In the above embodiment, the reference signal foID is introduced from the color difference demodulation circuit. However, the present invention is not limited to this. In addition, there are various methods for adjusting the frequency of the carrier in the color difference demodulation circuit, both automatic and manual, and are not limited to the embodiments.

[Effects of the Invention] As described above, the present invention can eliminate adjustment components in an ID demodulation circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the ID demodulation circuit of FIG. 1 in detail, and FIG. 3 is a diagram for explaining the operation of the circuits of FIG. 1 and FIG. FIG. 4 is a diagram showing in detail the color difference demodulation circuit of FIG. 1, FIG. 5 is a diagram showing the characteristics and signal waveforms for explaining the operation of the circuit of FIG. FIG. 6 is a diagram showing another example of the ID demodulation circuit of FIG. 1, FIG. 7 is a characteristic and signal waveform diagram for explaining the operation of the circuit of FIG. 6, and FIG. FIG. 9 is a diagram showing a demodulation circuit, FIG. 9 is a diagram showing the ID demodulation circuit of FIG. 8 in detail, and FIG. 10 is a characteristic and signal waveform diagram shown for explaining the operation of the circuit of FIG. 22 ... bell filter, 23 ... color difference amplifier, 24 ... color difference demodulation circuit, 25 ... baseband processing circuit, 27 ... ID amplifier, 28 ... ID demodulation circuit, 29 ... line discrimination circuit, 30 ...
Flip-flop circuits, 33, 38, 52, 74 ... phase comparators, 35, 39, 54, 76, 83 ... voltage-current converters, 36, 55,
77 …… Adder, 37, 56, 78 …… Voltage controlled oscillator, 79 ……
Sample hold circuit, 81 ... Comparator.

Claims (5)

(57) [Claims] 1. A means for generating a reference signal having an intermediate frequency between two ID signals in a SECAM receiver, and introducing the reference signal into an ID demodulation circuit using a phase locked loop circuit to demodulate this circuit. A SECAM type line identification circuit, comprising: means for controlling an axis center frequency to be the same as the reference signal frequency. 2. The ID demodulation circuit comprises a first phase locked loop circuit, and an initial oscillation (free-run) frequency of a first oscillator controlled by a voltage or a current in a loop of the phase locked loop circuit. 2. The apparatus according to claim 1, further comprising means for controlling the reference signal to be equal to the reference signal.
The described SECAM line identification circuit. 3. A color difference demodulation circuit having a second phase locked loop circuit configuration, wherein the reference signal is supplied from a second oscillator controlled by a voltage or current in a loop of the color difference demodulation phase locked loop circuit. 2. The SECAM type line identification circuit according to claim 1, wherein: 4. A third phase locked loop circuit, which also serves as a first oscillator in a loop of the first phase locked loop circuit and forms a different loop from the first phase locked loop circuit, 3. The SECAM line identification circuit according to claim 2, further comprising means for pulling a free-run frequency of a first oscillator into said reference signal by a third phase locked loop circuit when said reference signal is input. 5. A means for sample-holding a demodulated output of the first phase-locked loop circuit during a non-signal period input to the loop, and the sample-hold information and the reference signal are used by the first phase-locked loop. And means for comparing the demodulated output with the demodulated output at the time of demodulation, mixing the comparison result into loop control information of the first phase locked loop circuit, and equalizing the two demodulated outputs. 2. A SECAM type line identification circuit according to 2.