JP2885441B2 - Color signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a time-division multiplexed FM signal, for example,
The present invention relates to a color signal processing device for processing a SECAM television signal.

(Prior Art) At present, there are three color television signal systems, NTSC, PAL, and SECAM, which are used in the world.
Of these, the SECAM method is mainly used in eastern countries and France. In the SECAM system, color signals (RY) and (BY) are converted to FM to improve characteristics against transmission distortion.
It is demodulated and transmitted line-sequentially. FM demodulation carrier is
(RY) and (BY) are different, (RY) is 282f
H and (BY) are 272fH (fH = 15.625 KHz). In order to determine whether the (RY) signal or the (BY) signal has been received on the receiving side, detection is performed by detecting an identification signal called an identity signal or an ID signal of each line. I have. The ID signal is inserted between the back porch and the vertical blanking period.

Also, similar to the carrier suppression performed in the NTSC system, the SE
Even in the CAM method, in order to reduce the influence of the color signal on the luminance signal, the color signal is processed through a band suppression filter (an inverted bell type at the time of transmission) called a bell filter.

In a color television receiver that receives and processes the above-described color signals, since only one of the color difference signals is always present when focusing only on one horizontal period (1H line), the color difference signal of the previous line is delayed until the next line. Need to be kept and synchronized. Therefore, conventionally, a glass delay line was used.
1H delayed color difference signal is obtained. Conventionally, this glass delay line
It is provided at a position that provides a delay in the high frequency (RF) band. For this reason, a beat is generated between the direct signal that is not delayed and the delayed signal, and double-sided interference called line crawling has appeared. To avoid this, the demodulated line-sequential color difference signals, that is, the (RY) signal and the (BY) signal may be alternately delayed by 1H and synchronized. As a device for delaying such a demodulated signal, a CCD (Charge Coupled Device) can be used in conjunction with the development of the device, and this can be realized.

By the way, when processing SECAM chroma signals,
The color difference signals, that is, the (RY) signal and the (BY) signal
It is transmitted line-by-line alternately every 1H (one horizontal period),
Moreover, the FM modulation carrier frequency of each signal is different. For this reason, two FM demodulators, one for (RY) and one for (BY), are used.
One is prepared and a color difference signal is obtained. It is conceivable to use a one-axis demodulator in order to reduce the number of demodulators and to achieve a simple configuration. However, when the carrier frequency changes {when the (RY) signal arrives and the (BY) signal arrives} Since the DC level (DC level) of the demodulated output greatly fluctuates, a normal demodulated output cannot be obtained. This means that faithful color reproduction cannot be performed. As described above, the chroma signal transmission method causes the SECAM demodulator to have a complicated configuration.

FIG. 10 shows a characteristic circuit portion for processing a chroma signal of the SECAM system.

The chroma signal is supplied to a bell filter 2 via an input terminal 1. The bell filter 2 corrects the signal characteristics of the transmission side by the inverse bell filter.
, A chroma signal having a constant amplitude can be obtained.

The output chroma signal of the bell filter 2 is supplied to the color difference amplifier 3
It is supplied to the ID amplifier 4. The ID amplifier 4 has a (RY) ID inserted at the head of the FM-modulated (RY) signal.
This circuit amplifies the signal and the (BY) ID signal inserted at the head of the FM-modulated (BY) signal. The timing of the color difference signal and the input timing of the ID signal are determined by the gate pulse supplied from the input terminal 5.

Only the chroma signal from which the ID signal has been removed is extracted from the color difference amplifier 3 and is input to the color difference demodulator 6. The ID signal extracted from the ID amplifier 4 is input to the ID demodulator 7.
In the color difference amplifier 6, the black level of the demodulation is adjusted by using the external regulators VR1 and VR2. Switching of the demodulation axis for each line in the color difference demodulator 6 is executed by a line pulse from the terminal 8. The demodulated color difference signal is input to the baseband processing circuit 9. here,
Synchronization processing of (RY) signal and (BY) signal using 1H delay circuit and (GY) by matrix operation
A signal is generated. On the other hand, the ID signal from the ID amplifier 4 is demodulated in the ID demodulator 7. The adjustment of the demodulation axis in the ID demodulator 7 is adjusted by the volume VR3. I
The demodulated output of the D demodulator 7 is composed of a (RY) signal and a (BY) signal.
A detection output indicating which of the signals is arriving,
It is used for timing and phase control of line switches and switching pulses.

(Problems to be Solved by the Invention) In the above-described chroma signal processing apparatus of the SECAM system, two adjustment points of volume in the color difference demodulator 6 and one adjustment point of volume in the ID demodulator 7 are required. is there. The fact that there is an adjustment part of the volume means that there is an element of the change with time. For this reason, the above-described apparatus has a problem in that it is inferior in reliability in a long term, and has many adjustment steps in the manufacturing process of the image receiver, so that an increase in cost cannot be avoided.

Therefore, the present invention uses a demodulator using a phase-locked loop circuit to follow signals (ID signal, (RY) information, (BY) information) having different demodulation axes input in a time-division manner. Demodulation is performed, and a voltage-controlled oscillator in the loop of the phase-locked loop circuit is incorporated in a second phase-locked loop circuit, and the free-run frequency of the voltage-controlled oscillator is automatically adjusted to a reference frequency signal. By doing so, it is an object to provide a color signal processing device capable of reducing adjustment items.

According to the present invention, a reference signal generator for generating a reference frequency signal and first and second sub-carriers having different frequencies are used.
A phase-locked loop type demodulation circuit for demodulating alternately modulated color difference signals; and an oscillating frequency of an oscillator forming the demodulation circuit, the oscillating frequency being adjusted by the reference frequency signal in predetermined first and second periods. And an adjusting means for alternately adjusting the frequency to the second subcarrier frequency.

(Operation) With the above-described means, it becomes possible to make the oscillator in the phase locked loop non-adjustable, and it is also possible to reduce the temporal change and error of the free-run frequency.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The chroma signal separated from the SECAM television signal is supplied to input terminal 11
And supplied to the bell filter 12. Bell filter 12
Is used to correct the signal characteristics of the transmission side by an inverse bell filter. By passing through the bell filter 12, a chroma signal having a constant amplitude can be obtained.

The output chroma signal of the bell filter 12 is supplied to the color difference amplifier 13.
It is supplied to the ID amplifier 14. The ID amplifier 14 is inserted at the head of the (RY) ID signal inserted at the head of the FM modulated (RY) signal and at the head of the FM modulated (BY) signal (BY). ) Is a circuit for amplifying the ID signal. The timing of the color difference signal and the input timing of the ID signal are
Is determined by the gate pulse supplied from.

Only the chroma signal from which the ID signal has been removed is extracted from the color difference amplifier 13 and input to the PLL color difference demodulator 16. The ID signal extracted from the ID amplifier 14 is input to the PLLID demodulator 17.

Switching of the demodulation axis for each line in the color difference demodulator 16 is as follows.
This is executed by a line pulse from the terminal 18. The adjustment of the demodulation axis at this time is executed based on adjustment information input from an automatic adjustment circuit 20 described later. The demodulated color difference signal is input to the baseband processing circuit 19. here,
Synchronization processing of (RY) signal and (BY) signal using 1H delay circuit and (GY) by matrix operation
A signal is generated. On the other hand, the ID signal from the ID amplifier 14 is demodulated in the ID demodulator 17. The adjustment of the demodulation axis in the ID demodulator 17 is performed by an automatic adjustment circuit 20 described later. The demodulated output of the ID demodulator 17 is a detection output indicating which of the (RY) signal and the (BY) signal has arrived, and is used for line switch and switching pulse timing and phase control. .

The above-described PLL color difference demodulator 16 performs two-axis demodulation. Even if the carrier of the input FM signal is different, as long as the carrier is inputted in a time-division manner, that is, as long as the carrier is alternately inputted every 1H, it follows each carrier. Thus, a demodulated output can be obtained.

Hereinafter, this two-axis demodulation method will be described with reference to FIGS. 2 and 3. FIG.

FIG. 2 is a level chart showing the detection characteristics of the demodulation PLL circuit. Now, the PLL color difference demodulator 16 receives the line pulse in synchronization with the polarity (RY / BY) of the input color difference signal, switches the control signals r and b from the automatic adjustment circuit 20, and selectively introduces them. It is assumed that The control signal is a signal for setting the free-run frequency of the voltage-controlled oscillator incorporated in the loop of the PLL circuit.

When the (BY) signal is input, the automatic adjustment circuit 20
Is selected to set the free-run frequency of the voltage controlled oscillator in the PLL circuit. This set frequency is fOB (= 272fH). Here, the color difference black level on the transmission side is also set at the frequency fOB, and the demodulation output potential VOB obtained at this set frequency is used as a reference. Therefore, the demodulation output signal swings around this potential V OB. Next, when the (RY) signal is input, the control signal r from the automatic adjustment circuit 20 is selected to set the free-run frequency of the voltage controlled oscillator in the PLL circuit. This set frequency is fOR (= 282fH). Here, the color difference black level on the transmission side is also set by the frequency fOR, and the demodulation output potential VOR obtained by this set frequency is used as a reference. Therefore, the demodulated output signal swings around this potential V OR (V OB).

As can be seen from FIG. 2, by switching the free-run frequency of the voltage-controlled oscillator in the PLL circuit line by line, the demodulated output can be extracted as a signal swinging around the potential V OR (= V OB). DC fluctuation does not occur between lines. Thus, the DC level of the demodulated output is determined by where the free-run frequency of the voltage controlled oscillator is located, and the present invention utilizes this fact.

As described above, if the control signal for switching the free-run frequency of the voltage-controlled oscillator of the PLL circuit is supplied from the automatic adjustment circuit 20 for each line, the same PLL demodulator can demodulate and output two types of signals having different carriers. Obtainable.

 Next, the ID demodulator 17 will be described.

The PLL circuit of the demodulator 17 is used, and the free-run frequency of the voltage-controlled oscillator incorporated in the loop is set by the control signal rb / 2 from the automatic adjustment circuit 20. This free-run frequency f OID is 277 fH ｛= (fOB + fOR) /
2｝.

FIG. 3 shows the detection characteristics of the ID demodulator 17. When the free-run frequency is set to 277 fH, (B−
When the ID signal for Y) arrives, a detection output smaller than the set potential VOID can be obtained, and when the ID signal for (RY) arrives, a demodulated output larger than the set potential VOID can be obtained. It can be identified by this polarity. The ID signal inserted in the vertical flyback period is fm as shown in FIG.
The frequency of ax and fmin.
Demodulated outputs of Vmax and Vmin are obtained for VOID.

As described above, also in the ID demodulator 17, by giving the control signal rb / 2 from the automatic adjustment circuit 20, two signals having different frequencies are provided.
The demodulated output of one ID signal can be obtained.

The voltage controlled oscillator in the demodulator described above is also incorporated in a second phase locked loop circuit in the automatic adjustment circuit, and is controlled so that its free-run frequency is phase locked to the reference signal. For this reason, if a high-precision signal source is adopted as the reference signal, it is possible to greatly reduce the time-dependent change and error of the free-run frequency in the voltage controlled oscillator, and furthermore, the deviation due to the offset.

FIG. 4 shows the inside of the automatic adjustment circuit 20 and the PLL color difference demodulator 16 more specifically.

The chroma signal from the color difference amplifier 13 at the preceding stage is
It is input to 161 and is compared in phase with an oscillation signal from a voltage controlled oscillator (VCO) 162. The phase difference output is a demodulated output. This phase difference output is input to the voltage / current converter 163, and the current conversion output is fed back to the frequency and phase control terminal of the VCO 162. As a result, the oscillation frequency of the VCO 162 is phase-locked to the input chroma signal, and the phase difference output, which is control information of the VCO 162, becomes the demodulated output.

Here, in order to switch the demodulation axis line by line,
From 4, a line pulse is supplied to the VCO 162 as an alternating signal. The VCO 162 has two current source input terminals, and a selection switch of a current source connected to the VCO 162 is controlled by a line pulse.

Furthermore, the oscillation signal of the VCO 162, in addition to the phase comparator 161,
It is also input to the frequency divider 201 inside the automatic adjustment circuit 20.

The automatic adjustment circuit 20 includes a reference signal generator 204 that stably outputs two types of reference signals, and a switch 205 that selects the output and supplies the output to one of the phase comparators 203. The frequency divider 201 also has two types of frequency division ratios, and can obtain two types of frequency divided outputs obtained by dividing the output of the VCO 162. One of the divided outputs is selected by the switch 202 and supplied to the other of the phase comparator 203. The output of the phase comparator 203 is supplied to drivers 206 and 209. This driver
One of 206 and 209 is controlled to turn on and the other is turned off every 1H at a timing described later. The output of the driver 206 is filtered by the filter 208 and supplied to the voltage-current converter 207, and the output of the driver 209 is
The data is filtered by the filter 211 and supplied to the voltage-current converter 210.

The outputs IOB and IOR of the voltage-to-current converters 207 and 210 are supplied to a current source terminal of the VCO 162. Thus, if the current source current of VCO 162 is switched, the free-run frequency of VCO 162 is switched. Further, the automatic adjustment circuit 20 includes a timing controller.
211, thereby selecting the switches 205, 202,
Controls on / off of drivers 206 and 209. The timing controller 212 also outputs a switching control signal based on the ID demodulation output.

Now, assuming that the (BY) signal has arrived, VC
O162 is a frequency divider 201, a phase comparator 203, a driver 206,
The VCO is incorporated in a phase locked loop of the voltage-to-current converter 207 (hereinafter, this loop is referred to as an fOB adjustment loop).
162 free-run frequencies are set. Next, (R-
Y) When the signal arrives, the VCO 162 is incorporated in a phase locked loop of the frequency divider 201, the phase comparator 203, the driver 209, and the voltage / current converter 210 (hereinafter, this loop is referred to as an fOR adjustment loop). Is set.

 The fOB adjustment loop will be described.

The output signal of VCO 162 is first supplied to frequency divider 201 and divided. Assuming that the frequency division ratio at this time is 1/17, the free-run frequency near fOB (= 272 fH) oscillated by the VCO 162 is frequency-divided to a frequency near 16 fH. Now, the reference signal generator 204-1
Assuming that a signal of 6fH is output, the phase comparator 203 compares the phases of both signals, and if the phases are shifted, a beat signal is generated. At this time, the driver 206 is active and the driver bar 209 is cut off. The driver 206 outputs the input phase comparison result with a gain of 1, and drives the loop filter 208. The filtered phase comparison signal is input to the voltage / current converter 207, and is converted to a current output. This current drives the free-run frequency of VCO 162 to fOB. That is, the VCO 16 is controlled so that the divided output of the output of the VCO 162 in the phase comparator 203 and the reference signal from the reference signal generator 204 become equal.
The oscillation frequency of 2 is controlled and maintained. In this case, the free-run frequency is 272 fH, which is 17 times 16 fH, and the adjustment of fOB is completely obtained.

 Next, the fOR adjustment loop will be described.

At this time, the frequency divider 201 is set to a frequency division ratio of 1/141. The free-run signal oscillated by the VCO 162 is
The frequency is divided into / 141 and input to the phase comparator 203. Now, assume that a signal of 2fH is extracted from the reference signal generator 204 and input to the phase comparator 203. If the phase is out of phase, a beat signal is output from the phase comparator 203. At this time, the driver 206 is cut off and the driver bar 209 is active. The driver 209 outputs the input phase comparison result with a gain of 1, and drives the loop filter 211. The filtered phase comparison signal is input to the voltage-to-current converter 210 and converted to a current output. This current drives the free-run frequency of VCO 162 to fOB. That is, in the phase comparator 203, the oscillation frequency of the VCO 162 is controlled and maintained such that the frequency-divided output of the output of the VCO 162 becomes equal to the reference signal from the reference signal generator 204. At this time, the free-run frequency becomes 282 fH, which is 141 times 2fH, and the adjustment of fOR is completely obtained.

In the above configuration, if the frequency divider 201 does not malfunction, the frequency division ratio surely takes the above value, so that the accuracy of the free-run frequency of fOB and fOR depends on the absolute frequency accuracy of the reference signal. There is no problem if a high-accuracy signal can be obtained from other blocks of the television receiver. However, if this is difficult, it is necessary to prepare a separate signal.

 FIG. 5 is an example of the reference signal generator 204.

For example, a 4 MHz (= 256 fH) oscillator is used as crystal oscillator 221. The oscillation signal is supplied to the frequency divider 222 and
Divided to / 128. As a result, a reference signal having a frequency of 2fH is obtained from the frequency divider 222. As the frequency divider 222, seven 1/2 frequency dividers are connected in series, and a 16 fH reference signal can be obtained in the frequency dividing process. Since the frequency division ratio of the frequency divider 222 is also accurately determined, the accuracy of the reference signal depends on the oscillation frequency accuracy of the crystal oscillator 221. Generally, the accuracy of the crystal oscillator 221 is 2
Because it is below 00 ppm and on the order of 10 ^-4 , VCO162
Is sufficient as the free-run accuracy.

The frequency division ratio is not limited to the purpose of the present invention, and may be any frequency as long as the PLL circuit for adjusting the free-run frequency fO of the VCO 162 is established. For example, when performing fOB and FOR adjustment, use the frequency of fH and
An oscillator for obtaining an oscillation frequency of fH may be prepared, or a horizontal deflection signal of fH may be used as a reference signal.

It is necessary to select a period during which the free-run frequency fO of the VCO 162 is adjusted using the above-described automatic adjustment circuit 20 without affecting the demodulation of the color difference signal. As an example, FIG. 6 is a timing chart when the above-mentioned free-run frequency adjustment is performed during the vertical blanking period. The frequency of the phase comparison signal after frequency division as described above is low,
Comparison cannot be made only in the horizontal blanking period. Therefore, a sufficient comparison time margin can be obtained in the case of a frame cycle. However, since there are two frequencies to be adjusted, fOB and fOR, a method of adjusting by switching the adjustment loop alternately for each frame is used. Vertical sync signal is 3H for each frame
Each one, so use this as a trigger
The key pulse K1 is supplied to 6, 209. Key pulse K1 is
The state is created by the timing controller 212, and the state is changed every other frame for 16fH from the leading edge of the vertical synchronization signal. The key pulse for driver 206 is (n-
1) The frame becomes the low level Lo in the frame and the (n + 1) frame, and the driver 206 is activated during this period. The key pulse for the driver 209 becomes low level Lo in the nth frame and the (n + 2) th frame, and the driver 209 is activated during this period. The key pulse K2 is used as an input signal switching pulse to the phase comparator 203. The key pulse K2 is a pulse whose state changes in synchronization with the falling edge of the vertical synchronization signal,
High level in (n-1) and (n + 1) frames
Become Hi. When the key pulse K2 is at a high level, the fOB adjustment loop is selected, and the switches 205 and 202 are switched to predetermined terminals.

As described above, the color difference signal processing is substantially eliminated by the PLL color difference adjustment method and the automatic adjustment circuit that sets the free-run frequency of the VCO inside the PLL.

Next, the ID demodulator 17 side and its non-adjustment will be described.

In order to eliminate the adjustment of the fOID (= 277fH) of the PLLID demodulator 17, the output of the VCO in the PLL circuit inside the demodulator 17 is frequency-divided as in the case of the PLL color difference demodulator, and another stable operation is performed. What is necessary is just to incorporate in the PLL circuit which has a reference signal. For example, 277
The frequency of fH may be divided by 277, converted into a signal near fH, compared with the phase of the reference signal fH, and the VCO may be locked in phase. In this way, the VCO inside the ID demodulator 17 can obtain fOID (see FIG. 3) in which fH is multiplied by 277 exactly, as in the case of the color difference demodulator 16 side. Note that the 1/277 frequency dividing stage may be shared with the frequency divider 201, or a PLL circuit may be provided independently for ID.

 Next, a specific circuit of each part will be described.

FIG. 7 is a specific circuit of the VCO 162. VCO162 consists of transistors Q1-Q15, Q20-Q23, resistors R1-R10, capacitors
It is composed of C1. Transistors Q1 to Q15 constitute an emitter-coupled multivibrator oscillator, and transistors Q20 to Q23 constitute a current switch. The multivibrator alternately charges and discharges the capacitor C1 to obtain an oscillation output. The discharge current is
3. This is the collector current of Q14, and since the transistors Q13 to Q15 form a current mirror circuit, the total is the sum of the input currents from the current switch and the voltage-current converter. The oscillation voltage generated at the resistors R1 and R2 is
It is equal to the potential difference generated in the resistor R3 because it is clamped by 1, Q2 and Q3. The oscillation output is derived from the emitters of the transistors Q2 and Q3. The above current sum is set to Icont and the resistance R3
Assuming that the potential difference generated at this time is VR3, the oscillation frequency fosc becomes fosc = Icont / (4 × C1 × VR3). Since VR3 is constant, the oscillation frequency changes linearly with respect to the control current.

The current switch is a part for switching the current flowing through the multivibrator, and the line pulse is applied to the transistor Q20.
To a predetermined base of Q23. As shown in the figure,
When the line pulse is at the low level Lo, the transistor Q2
1 and Q22 are turned on, and the current Ifob supplied to the collector of the transistor Q21, that is, the control signal b shown in FIG.
Will be added as the VCO current. When the line pulse is at the high level Hi, the transistors Q20 and Q23 are turned on, and the current IfOR supplied to the collector of the transistor Q21, that is, the control signal r shown in FIG. 1 is applied as the VCO current. become. Thereby, the free-run frequency of the VCO is determined. Therefore, the currents IfOB and IfOR are adjusted to give oscillation frequencies of fOB and fOR, respectively. Therefore, the demodulation axis of the demodulator 16 can be switched by the line pulse (see FIG. 2).

FIG. 8 shows a specific circuit example of the phase comparator 161 and the voltage-current converter 163.

The phase comparator 161 includes transistors Q24 to Q37 and Q44 and resistors R17 to R24 and R34. Also, the voltage-current converter 163 includes transistors Q38 to Q43, Q45 to Q47, and R25 to
It is composed of R33 and R35 to R38.

A chroma signal is input to the bases of the differential transistors Q28 and Q29, and the oscillation output of the VCO shown in FIG. 7 is supplied to the differential pair transistors Q24 to Q27. The phase comparison output is inverted and single-ended by the current mirror circuit of the transistors Q30 to Q37, flows to the load resistance of the resistor R25, and is converted into a voltage.

This voltage is applied to the base of the transistor Q28 of the voltage-to-current converter. The differential amplifier of the transistors Q38 and Q39 obtains a current return output. Both collector currents of the transistors Q38 and Q39 are single-ended by the current mirror circuit of the transistors Q40 and Q41, and the conversion current is
Output from 1 collector. This current is supplied to the VCO 162 (the bases of the transistors Q13 and Q14). Assuming that the conversion rate of the voltage-current converter 161 is Gm, Gm = 1 / (re + R27) re = (Ic / Vt), Ic: collector current, and Vt: thermoelectromotive force.

 When re << R27, it is given by 1 / R27.

Next, a demodulated color difference signal Vout of the PLL color difference demodulator will be obtained.

Assuming that the frequency shift of the input chroma signal as the FM signal is Δf, the control current ΔI required for the VCO is ΔI = 4 × C1 × VR3 × Δf. Vout for generating ΔI is as follows: Vout = ΔI / Gm = 4 × C1 × VR3 × Δf × 2R27

The same can be said for the PLLID demodulator 17 in FIG. In the case of the ID demodulator 17, since the internal VCO does not need to switch the demodulation axis for each line, only one fo adjustment is required,
A portion corresponding to the switch including the transistors Q20 to Q23 shown in the drawing is unnecessary. The demodulation output of the ID demodulator 17 is given by the same parameters as the above-described Vout equation, as in the case of the color difference demodulation.

FIG. 9 shows a specific circuit example of the driver 206, the filter 208, and the voltage-current converter 207.

The driver 206 includes transistors Q48 to Q59 and a resistor R39 to
The loop filter 208 includes a resistor R42 and capacitors C2 and C3. The voltage-to-current converter 207 includes transistors Q60 to Q67 and resistors R43 to R53. The driver 206 is a voltage follower, and the difference voltage detected by the differential amplifier by the transistors Q48 and Q49 is driven by a low impedance driver of the transistors Q52 to Q56 and supplied to the resistor R42. This voltage is smoothed by a filter
Applied to the base of Q60. This voltage is amplified by the differential pair transistors Q60, Q61, and the transistors Q62, Q63
The current is converted by the current mirror circuit and is derived. The current conversion rate can be changed by changing the values of the resistors R43 and R44.

As described above, the PLL circuit method is used as the demodulator,
This VCO is used to determine the free-run frequency of the internal VCO.
Can be incorporated in a PLL circuit using another reference signal, thereby making it possible to eliminate the need for a demodulator. In addition, by switching the free-run frequency, the demodulation axis can be switched in a time-division manner, and the number of demodulators for demodulating the chroma signal of the SECAM system can be reduced. In the case of an integrated circuit, although the number of elements is increased, the demodulation system can be integrated into one chip, and there are no manual adjustment points, which is advantageous in terms of the manufacturing process, time, and final adjustment, resulting in low cost.

[Effects of the Invention] As described above, the present invention uses a PLL circuit as a demodulator, can form a plurality of demodulation axes, can demodulate a plurality of FM signals having different modulation axes, and furthermore has no adjustment. Can be obtained. Further, the production cost can be reduced due to the non-adjustment, which is advantageous for maintaining long-term operation reliability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams each for explaining the operation principle of the device of the present invention, and FIG. 4 is a circuit diagram of FIG. FIG. 5 is a circuit diagram showing a part of the block in detail, FIG. 5 is a diagram showing an example of a reference signal generator in FIG. 4, FIG. 6 is a timing chart shown for explaining an operation example of the circuit in FIG. FIG. 7 is a circuit diagram showing a specific example of the voltage-controlled oscillator of FIG. 4, FIG. 8 is a circuit diagram showing a specific example of the phase comparator and the voltage-current converter of FIG. 4, and FIG. FIG. 10 is a circuit diagram showing a specific example of a driver, a filter, and a voltage-current converter, and FIG. 10 is a diagram showing an example of a color demodulation circuit of the SECAM system. 12: Bell filter, 13: Color difference amplifier, 14: ID amplifier, 16: PLL color difference demodulator, 17: PLLID demodulator, 19 ...
Baseband processing circuit, 20 …… Automatic adjustment circuit, 161 ……
Phase comparator, 162 …… Voltage controlled oscillator (VCO), 163 ……
Voltage-current converter, 201: frequency divider, 202, 205 ... switch, 203: phase comparator, 204 ... reference signal generator, 20
6, 209 …… Driver, 207, 210 …… Voltage-current converter,
208, 211 ... Filter, 212 ... Timing controller.

Claims (1)

(57) [Claims] A reference signal generator for generating a reference frequency signal; a phase locked loop type demodulation circuit for demodulating a color difference signal alternately modulated by first and second subcarriers having different frequencies; Adjusting means for alternately adjusting the oscillation frequency of the oscillator forming the demodulation circuit to the first and second sub-carrier frequencies by the reference frequency signal during predetermined first and second periods. Characteristic color signal processing device.