JP3349835B2 - Sampling rate converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling rate converter for converting a sampling rate of a digitized component signal into a sampling rate of a digitized composite signal in, for example, a television signal processor.

[0002]

2. Description of the Related Art In recent years, digitization of processing has been advanced in television signal processing devices. Along with this, digitization of processing has also been attempted in an encoder for converting a component signal into a composite signal.

Here, the component signal is a signal constituting a television signal, such as a luminance signal and a color difference signal. On the other hand, a composite signal is a signal obtained by modulating a color subcarrier with a color difference signal and superimposing this modulated wave on a luminance signal.

As a method of converting a component signal into a PAL composite signal by digital processing, there is a method of converting the sampling rate of the component signal without changing the sampling rate, and then converting the sampling rate to the sampling rate of the composite signal. .

In the case of the conversion method, an analog / digital converter for digitizing the chrominance subcarrier and two multipliers for modulating the chrominance subcarrier with two color difference signals are required. Is increased. Further, in the case of this conversion method, there is a problem that a signal conforming to the digital standard of the composite signal cannot be obtained.

On the other hand, in the case of the conversion method, such a problem does not occur. For this reason, when it is desired to obtain a signal that complies with the digital standard of the composite signal on a small hardware scale, the conversion method of (1) is adopted.

In order to convert a component signal into a composite signal based on the above conversion method, a sampling rate conversion device for converting the sampling rate of the component signal into the sampling rate of the composite signal is required.

In this sampling rate conversion device, in addition to the function of converting the sampling rate, an interpolation function for converting a signal discontinuous by this conversion into a continuous signal is required.

In order to realize this interpolation function, in a conventional sampling rate converter, an interpolation coefficient corresponding to a conversion ratio of a sampling rate is determined, and interpolation processing is performed using the interpolation coefficient. Had become.

[0010]

However, in such a configuration, for example, when the sampling rate of a component signal is converted to the sampling rate of a PAL composite signal, the configuration of a digital filter for interpolation becomes complicated. There was a problem.

This is the color subcarrier frequency f of the PAL system.
between the sc and the line frequency f _H, it is from relationship of 4fsc = {1135+ (1/625)} f H ... (1). That is, because of such a relationship, if the conversion of the sampling rate is to be performed accurately, the conversion of 540000: 709379 must be performed, and the interpolation coefficient increases.

[0012] In order to solve this problem, the relationship of the formula (1), it is conceivable to approximate the _{4fsc = 1135f H ... (2)} . That is, it is conceivable that the offset amount (4/625) f _H is not considered.

According to such a configuration, 864: 113
5, the number of interpolation coefficients can be reduced. Thereby, the configuration of the digital filter can be simplified.

However, in such a configuration, the configuration of the digital filter can be simplified.
A new problem arises in that an error due to approximation appears as image distortion.

As described above, in the sampling rate converter for converting the sampling rate of a component signal into the sampling rate of a PAL composite signal, the configuration of the interpolation digital filter can be simplified without causing image distortion. Therefore, a sampling rate conversion device that can perform the above is desired.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a phase change of a data change point of a digital signal after converting the sampling rate with respect to a data change point of the digital signal before the conversion of the sampling rate. Paying attention to the point that the phase gradually advances for each sample, and returns to substantially the original phase at a predetermined sample. Based on the phase detection means for detecting the phase and the detection result of the phase detection means,
And control means for controlling the sampling rate conversion operation and the inner挿動operation provided, said phase detecting means, sampling rate
Data conversion point of the digital signal before conversion
On the other hand, after converting the sampling rate,
Of multiple phases that the data change point of the total signal can take
A specific phase detecting means for detecting a predetermined phase;
Reset based on the detection output of the specified phase detection means.
Clock signal corresponding to the conversion destination sampling rate.
The signals indicating the plurality of phases are counted by counting the signals.
And counting means for outputting a signal.
Things .

[0017]

With the above arrangement, it is possible to obtain an interpolation output corresponding to the phase at the data change point before and after the sampling rate conversion.

Further, interpolation processing can be performed using interpolation coefficients for the number of samples necessary for returning the phase of the data change point after the conversion of the sampling rate to the original state. As a result, the interpolation process can be performed using a small number of interpolation coefficients, so that the configuration of the interpolation digital filter can be simplified.

Furthermore, since the interpolation coefficient can be set based on the phase of the data change point after the conversion of the sampling rate with respect to the data change point before the conversion of the sampling rate, the conversion considering the offset amount can be performed. It can be carried out. As a result, the image distortion can <br/> I do not want to occur Unisuru. Also, the specific phase detection means
Configuration for detecting a specific phase can be simplified and counting
Means can simplify the phase detection configuration
You.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following description, a case where the present invention is applied to a sampling rate conversion device of a PAL encoder will be described as a representative.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. However, FIG. 1 shows a configuration of a color difference signal processing unit of a PAL type encoder including a sampling rate conversion device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes an input terminal to which a multiplexed signal of two color difference signals is supplied. Here, the sampling frequency of each color difference signal is set to 6.75 MHz. Therefore, the sampling frequency of the multiplex signal input from input terminal 11 is 13.5 MHz.
z. In the following description, for example, RY and BY are used as the color difference signals.

Numeral 12 synchronizes with the multiplexed signal RY / BY input from the input terminal 11 and has a horizontal synchronizing frequency f.
_This is an input terminal to which a pulse signal S1 having the same frequency as _H is supplied.

Reference numeral 13 denotes a multiplexed signal RY / BY synchronized with the multiplexed signal RY / BY input from the input terminal 11, and
This is an input terminal to which a clock signal S2 having the same frequency as the Y / BY sampling frequency of 13.5 MHz is supplied.

An input 14 is supplied with a clock signal S3 synchronized with the multiplexed signal RY / BY input from the input terminal 11 and having the same frequency as the sampling frequency 4fsc of the PAL composite signal. Terminal.

Reference numeral 15 denotes 1 input from the input terminal 13.
5. The frequency of the 3.5 MHz clock signal S2 is halved,
This is a 1/2 frequency divider that outputs a 75 MHz clock signal S4. 16 is 4 fs input from the input terminal 14
This is a 分 frequency divider that divides the frequency of the clock signal S3 of c by １ ／ and outputs the clock signal S5 of 2fsc.

Reference numeral 17 compares the phases of the two clock signals S4 and S5, thereby setting the sampling rate with respect to the data change point of the color difference signal RY (or BY) before converting the sampling rate. A predetermined phase (hereinafter, referred to as “specific phase”) among a plurality of phases (four or five) that can be taken by the data change point of the converted color difference signal RY (or BY). This is a specific phase detection unit to be detected.

The specific phase is, for example, within one sample period of the color difference signal RY (or BY) before the conversion of the sampling rate, the color difference signal RY (after the conversion of the sampling rate). Alternatively, a phase in which two data change points (BY) exist is selected.

Reference numeral 18 denotes a buffer memory for converting the sampling rate of the multiplexed signal RY / BY input from the input terminal 11 into the sampling rate of a PAL composite signal.

Reference numeral 19 denotes an input terminal 1 for the buffer memory 18.
This is a write control unit that outputs a write control signal and a write address for writing the multiplexed signal RY / BY input from the input unit 1.

The write control unit 19 outputs a write control signal in synchronization with the clock signal S2 input from the input terminal 13. The write control unit 19 updates the horizontal write address in synchronization with the clock signal S2, and updates the pulse signal S input from the input terminal 12.
In synchronization with 1, a horizontal write address is initialized.

Reference numeral 20 denotes a read control unit for outputting a read control signal for reading the multiplexed signal RY / BY stored in the buffer memory 18 and a read address.

The read control unit 20 outputs a read control signal in synchronization with the clock signal S3 input from the input terminal 14. The read control unit 20 updates the horizontal read address in synchronization with the clock signal S3, and updates the pulse signal S input from the input terminal 12.
In synchronization with 1, a horizontal read address is initialized. Further, when the specific phase is detected by the specific phase detection unit 17, the read control unit 20 stops the generation of the read control signal and the update of the read address during that period.

Reference numeral 21 denotes a multiplexed signal RY / B read from the buffer memory 18 having, for example, three taps.
By delaying −Y, each color difference signal BY, RY
Is a delay unit that simultaneously outputs data for three consecutive samples X0, X1, and X2 for each of the three samples.

The delay section 21 is composed of four shift registers 211, 212, 213 and 214 connected in series. Each shift register 211, 212, 2
13 and 214 are 4fsc input from the input terminal 14.
Is driven by the clock signal S3.

In such a configuration, the data of the current sample X0 read from the buffer memory 18 appears at the input terminal of the shift register 211, and the output terminal of the shift register 212 displays the data of one sample before the current sample X0. The data of the sample X1 appears, and the shift register 214
, The data of the sample X2 two samples earlier appears.

The reason why the delay unit 21 is composed of four shift registers instead of two shift registers is that the signals read from the buffer memory 18 are 4 fsc and the color difference signals RY and BY are multiplexed. This is because the signal has been processed.

A selection unit 22 selects, for example, data D1 and D2 for two samples for interpolation from among the data for three samples output from the delay unit 21 at the same time.
The selection unit 22 stores the data of the sample X2 and the sample X2.
Switch 221 for selecting any one of data 1
And a switch 222 for selecting one of the data of the sample X1 and the data of the sample X2.

Reference numeral 23 denotes a load adding unit that adds a load to the data D1 and D2 for the two samples selected by the selecting unit 22 using the interpolation coefficients k1 and k2. This load adding unit 23
Is the interpolation k to the data D1 selected by the switch 221.
A multiplier 231 that multiplies the data D2 selected by the switch 222 by an interpolation coefficient k2.
And an adder 233 for adding the multiplied outputs of the two multipliers 231 and 232.

Reference numeral 24 denotes a detection signal S of the specific phase detector 15
By counting the 2fsc clock signal S5 reset by 6 and output from the 1/2 frequency divider 16, the data change point after the sampling rate conversion can be taken with respect to the data change point before the sampling rate conversion. It is a counter that outputs a signal indicating one or five phases.

Reference numeral 25 denotes a count value S of the counter 24.
7 is a selection control unit that controls the selection operation of the selection unit 22 based on the control unit 7.

Reference numeral 26 denotes interpolation coefficients k1 and k supplied to the load adder 23 based on the count value S7 of the counter 24.
This is a coefficient generator that generates 2.

Reference numeral 27 denotes a multiplexed signal RY / BY output from the load adder 23, which converts the multiplexed signal RY / BY into a color difference signal RY and a color difference signal BY.
This is a separation section for separating into Y.

The separation unit 27 includes a shift register 271 driven by a 4 fsc clock signal S3 input from the input terminal 14, and a shift register 271 output from the 1/2 frequency dividing unit 16.
The shift registers 272 and 273 are driven by the clock signal S5 of fsc, and perform the above-described separation. Note that the figure shows a case where the color difference signal RY is output from the shift register 272 and the color difference signal BY is output from the shift register 273.

A low-pass filter 28 limits the band of the color difference signal RY output from the shift register 272. Reference numeral 29 denotes a low-pass filter for band-limiting the color difference signal BY output from the shift register 273.

A modulation section 30 modulates the color difference signal RY band-limited by the low-pass filter 28 and the color difference signal BY band-limited by the low-pass filter 29. Reference numeral 31 denotes an output terminal to which a modulation output of the modulation unit 30 is supplied.

In the above configuration, the 1/2 frequency divider 15,
16, a specific phase detecting unit 17, a buffer memory 18
, A write control unit 19, a read control unit 20, a delay unit 21, a selection unit 22, a load addition unit 23, a counter 2
4, the selection control unit 25, and the coefficient control unit 26 constitute the sampling rate conversion device of this embodiment.

In this sampling rate converter, 1/2 frequency dividers 15 and 16 and specific phase detector 17
And the counter 24 constitute phase detecting means.
The buffer memory 18, the write control unit 19, and the read control unit 20 constitute a sampling rate conversion unit. The delay unit 21, the selection unit 22, and the load addition unit 23 constitute an interpolation unit. Further, the read control unit 20, the selection control unit 25, and the coefficient generation unit 26 constitute a control unit.

In the above configuration, referring to FIG.
The operation will be described. FIG. 2 is a timing chart showing the operation of FIG.

First, an outline of the operation of the embodiment will be described.
In FIG. 1, the conversion of the sampling rate of the color difference signal RY and the conversion of the sampling rate of the color difference signal BY are performed. However, both conversion operations are the same. Therefore, in the following description, the conversion operation of the color difference signal RY will be described as a representative.

FIG. 2A shows a data string of the color difference signal RY before the sampling rate is converted. That is,
6 shows a data string of 6.75 MHz. On the other hand, FIG. 3B shows a data sequence of the color difference signal RY after the sampling rate has been converted. That is, it shows a data string of 2fsc.

As shown in the figure, the phase of the change point of the data of 2fsc gradually advances for each sample with respect to the phase of the change point of the data of 6.75 MHz, and returns to almost the original phase at the fourth sample. . However, due to the relationship between the two sampling rates, the phase does not completely return to the original phase.
There is a portion that returns to the original phase at the fifth sample each time.

In any case, however, the phase of the change point of the 2fsc data changes in a predetermined repetition pattern with respect to the phase of the change point of the 6.75 MHz data.

This embodiment pays attention to this point, and 6.75
The phase of the data change point of 2 fsc with respect to the phase of the data change point of MHz is detected, the read operation of the buffer memory 18 is controlled based on the detected output, and an interpolation coefficient corresponding to the read data is assigned. Things.

That is, data reading is stopped for one sample period every four samples or every five samples of 2fsc data, and an interpolation coefficient corresponding to the read data is assigned.

According to such a configuration, an interpolation output corresponding to the phase of the data change point before and after the sampling rate conversion can be obtained.

Further, the interpolation processing can be executed only by switching at least four or five interpolation coefficients. Thereby, the configuration of the digital filter can be simplified.

By the way, as a method of detecting the phase of the change point of the data of 2fsc with respect to the data change point of 6.75 MHz, a method of detecting the actual phase of each change point of the data of 2fsc can be considered. However, in the case of this method, the configuration may be complicated.

Therefore, in this embodiment, 6.75 MHz
Out of the four or five phases that the 2fsc data transition point can take with respect to the data transition point, a predetermined specific phase is detected.
By counting the clock signal S5 of fsc,
All four or five phases are detected.

According to such a configuration, four or five
The detection output of all phases can be obtained by detecting substantially one of the phases, so that the phase detection configuration can be simplified as compared with the configuration in which all phases are actually detected. Can be.

Here, as the specific phase, as described above,
In one sample period of 6.75 MHz data, 2 fsc
Are determined such that two data change points exist.

That is, focusing on the data change point of 2fsc, as is apparent from FIGS. 2A and 2B, two such change points exist in the period of one sample of 6.75 MHz data. A case and a case where one exists. If two of them exist, they appear only once every 4 or 5 sample periods of 2 fsc data.

Therefore, the data change point of 2fsc is 2
By detecting the presence of two clock signals and using this detection output as a reset signal to count a clock signal of 2 fsc, substantially one phase is detected.
All four or five phases can be detected.

The above is the outline of the operation of the embodiment. Next, this operation will be described with reference to FIG. Input terminal 11
Of the multiplexed signal RY / BY input from the buffer memory 18, the write control unit 19, and the read control unit 20, the sampling rate is converted.

Next, the converted output is subjected to an interpolation process by the delay unit 21, the selection unit 22, and the weight addition unit 23. As a result, the multiplexed signal RY / BY that is discontinuous due to the conversion of the sampling rate is converted into a continuous signal.

Finally, the converted output is supplied to the separation unit 27,
Modulation is performed by low-pass filters 28 and 29 and a modulation unit 30. Thereby, a transport color signal is obtained. The carrier chrominance signal is output from the output terminal 31 and is synthesized with a luminance signal provided from a luminance signal processing unit (not shown).

The above operation will be described in detail as follows. The multiplexed signal RY /
BY is sequentially stored in the buffer memory 18 by the write control unit 19 in synchronization with the clock signal S2 of 13.5 MHz.
Is written to.

The data sequence written in the buffer memory 18 is sequentially read by the read control unit 20 in synchronization with the 4 fsc clock signal S3. As a result, the frequency of the multiplexed signal RY / BY is converted from 13.5 MHz to 4 fsc.

In parallel with this read operation, the specific phase detector 17 compares the phases of the clock signals S4 and S5.
Here, the frequencies of the clock signals S4 and S5 are 6.75 MHz and 2fsc, respectively, and both the signals S4 and S5 are
S5 is synchronized. Therefore, by this phase comparison, a phase (specific phase) in which two 2fsc data change points exist in one sample period of 6.75 MHz data is detected.

As shown in FIG. 2C, the detection signal S6 of the specific phase is at a high level, for example, at a portion where only one change point exists, and at a low level at a portion where there are two change points. The signal becomes as follows. This detection signal S6 is supplied to the read control unit 20 and the counter 24.

When the detection signal S6 is at a high level, the read control unit 20 executes a read operation. When the detection signal S6 is at a low level, the read control unit 20 stops reading for that period. As a result, as shown in FIG. 2E, the read output of the buffer memory 18 is such that data for one sample is missing every four or five samples. That is, the color difference signal RY and the color difference signal BY for one sample are missing every four or five samples.

On the other hand, the counter 24 is reset at the rising timing of the detection signal S6, and counts the clock signal S5 of 2 fsc. Thus, a quaternary and quinary counter is configured as shown in FIG. The count value S7 of the counter 24 indicates the phase of the data change point of 2 fsc with respect to the data change point of 6.75 MHz.

The data sequence read from the buffer memory 18 is delayed by the delay unit 21 by one sample. Thereby, as shown in FIGS. 2 (e), (f) and (g),
Data for three consecutive samples (X0, X1, X2) are output simultaneously. At this time, the data of the color difference signal RY and the data of the color difference signal BY are output alternately at a period of 1 / (4 fsc).

The data for three samples output from the delay unit 21 is supplied to the selection unit 22. The selection unit 22 calculates the data D for two samples from the data for three samples.
1 and D2 are selected as interpolation data.

The selection operation is performed based on the count value S7 of the counter 24 (see FIG. 2D).
Is controlled by The selection control unit 25 basically does not select the missing data from the data of three samples, and newly selects the data D newly created by the interpolation processing.
The selection operation of the selection unit 22 is controlled so that two data D1 and D2 having a strong correlation with No. 3 are selected.

Data D1, D2 selected by selection section 22
Is supplied to the load adding unit 23, and the load is added based on the interpolation coefficients k1 and k2. As a result, the signal that has become discontinuous due to the conversion of the sampling rate is converted into a continuous signal. FIG. 2H shows data D3 obtained by this interpolation processing.

The interpolation coefficients k 1 and k 2 are output from the coefficient generator 26 based on the count value S 7 of the counter 24. The coefficient generation unit 26 basically selects interpolation coefficients k1 and k2 according to the strength of the correlation between the data D3 and the data D1 and D2 from among a plurality of predetermined coefficients. It is provided to multipliers 231 and 232.

FIG. 3 shows an example of an interpolation process in a portion where a quaternary counter is formed, and FIG. 4 shows an example of an interpolation process in a portion where a quinary counter is formed.

As described above, the data D1 and D2 are:
A data having a strong correlation with the data D3 is selected. For this reason,
For example, when creating data (7) 'as data D3, data (5) and (6) are selected as data D1 and D2, respectively, as shown in FIG. In FIG. 2, double parentheses indicate data that is not selected.

The interpolation coefficients k1 and k2 are 2f
Assuming that the phase of the change point of the data of the sc changes at the period of n samples, n pieces are prepared. The values of the interpolation coefficients k1 and k2 are set to, for example, a natural number times 1 / n.

In this case, k1 + k2 is naturally set to 1. Therefore, as the interpolation coefficient k1,
When n coefficients of 1 / n, 2 / n, ..., (n-1) / n, 1 are prepared, the interpolation coefficient k2 is (n-
1) / n, (n−2) / n,..., 1 / n, 0 n coefficients are prepared.

In this embodiment, n is 4 and 5.
Therefore, where a quaternary counter is configured, four coefficients each of which is a natural number times 1/4 are prepared as interpolation coefficients k1 and k2. On the other hand, where a quinary counter is configured, five coefficients that are a natural number times 1/5 are prepared.

However, in this embodiment, even when a quinary counter is formed, as shown in FIG. 4, by using a certain coefficient twice, the same interpolation coefficient as the quaternary counter is formed. k1 and k2 are used. The reason for this is that since the number of parts constituting the quinary counter is much smaller than the number of parts constituting the quaternary counter, simplification of the structure is prioritized, and four types of coefficients are used.

In the example of FIG. 4, by using the same interpolation coefficients k1 and k2 for the fifth sample and the fourth sample,
The same interpolation coefficients k1 and k2 as those used in the quaternary counter are used in the quinary counter.

In the fifth sample, the interpolation coefficients k1 and k2 of the immediately preceding fourth sample are used because the interpolation coefficients k1 and k2 of the sample closer to the own sample are used, thereby deteriorating the signal quality. This is for minimizing the occurrence. In this sense, the interpolation coefficients k1 and k2 of the first sample of the next cycle may be used at the fifth sample of the certain cycle.

The data D obtained by the above-described interpolation processing
3 is supplied to the separation unit 27 and is separated into data of the color difference signal RY and data of the color difference signal BY. Each data is
After being band-limited by the corresponding low-pass filters 28 and 29, the signals are modulated by the modulator 30.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the phase of the data change point after the sampling rate conversion with respect to the data change point before the sampling rate conversion is detected.
Based on this detection output, the read operation of the buffer memory 18 is controlled, and the interpolation coefficients k1,
Since k2 is assigned, an interpolation output corresponding to the phase of the data change point before and after the sampling rate conversion can be obtained.

Further, at least four kinds of interpolation coefficients k1,
Since the interpolation processing can be performed only by switching k2, the interpolation processing can be performed using a small number of interpolation coefficients. Thereby, the configuration of the interpolation digital filter can be simplified.

Further, since the interpolation coefficients k1 and k2 can be set based on the phase of the data change point after the sampling rate conversion with respect to the data change point before the sampling rate conversion, the offset amount (1/625) f _The conversion considering _H can be performed. As a result, image distortion can be prevented even though the configuration of the digital filter can be simplified.

(2) According to this embodiment, a specific phase is selected from among four or five possible phases of a data change point after the sampling rate conversion with respect to the data change point before the sampling rate conversion. The clock signal S5 of 2fsc is detected as a reset signal.
Is counted, so that all the remaining phases are detected, so that the phase detection configuration can be simplified as compared with the case where all the phases are directly detected.

(3) According to this embodiment, as a specific phase, a phase in which two data change points after the sampling rate conversion exist in one sample period of the data before the sampling rate conversion is detected. With this configuration, the configuration for detecting a specific phase can be simplified as compared with the case of detecting a phase in which only one data change point exists.

This is because if a phase in which only one data change point exists is detected as a specific phase,
This is because, because there are three or four such phases, a predetermined specific phase must be identified from the plurality of phases.

(4) Further, according to this embodiment, when the sampling rate is converted, it is converted to 4 fsc, so that the configuration of the modulation section 30 can be simplified and the composite signal can be converted. Digital standard can be satisfied.

Although the embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment.

(1) For example, in the above embodiment, the present invention is applied to a case where the sampling rate of the component signal is set to PA
The case where the present invention is applied to a sampling rate conversion device that converts the sampling rate of an L-type composite signal into a sampling rate has been described.

However, the present invention is also applicable to a sampling rate converter for converting the sampling rate of a component signal into the sampling rate of a composite signal of the NTSC system.

When converting the sampling rate of the component signal to the sampling rate of the composite signal of the NTSC system, a hexadecimal counter is configured as the above-described counter.

(2) In the above embodiment, a case has been described in which the present invention is applied to a sampling rate conversion device that converts a sampling rate of a component signal into a sampling rate of a composite signal.

However, the present invention can also be applied to a sampling rate converter for converting the sampling rate of a composite signal into the sampling rate of a component signal.

In this case, the conversion of the sampling rate is as follows.
For example, data may be thinned out based on the phase detection result. However, in this case, it is necessary to perform the interpolation processing using the thinned data.

(3) The present invention is applicable not only to a sampling rate converter for converting a sampling rate of a television signal such as a component signal or a composite signal, but also to a sampling rate converter for converting a general sampling rate of a digital signal. Can also be applied.

(4) In addition, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0104]

As described in detail above, according to the present invention, the configuration of the interpolation digital filter can be simplified without causing image distortion, and a specific phase can be detected.
A sampling rate conversion device capable of simplifying a configuration for detecting the phase and a phase detection configuration can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of one embodiment.

FIG. 3 is a diagram illustrating an example of an interpolation process in a quaternary counter part according to an embodiment;

FIG. 4 is a diagram illustrating an example of an interpolation process in a quinary counter part according to an embodiment;

[Explanation of symbols]

11, 12, 13, 14 ... input terminals 15, 16 ... 1/2 frequency divider 17 ... specific phase detector 18 ... buffer memory 19 ... write controller 20 ... read controller 21 ... delay unit 22 ... selector 23 ... Load adder 24 ... Counter 25 ... Selection controller 26 ... Coefficient generator 27 ... Separator 28,29 ... Low pass filter 30 ... Modulator 31 ... Output terminal 211,212,213,214,271,272,2
73: shift register 231, 232: multiplier 233: adder

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03H 17/00-17/08

Claims (3)

(57) [Claims] 1. A sampling rate conversion device for converting a sampling rate of a digital signal, wherein the sampling rate conversion means for converting the sampling rate of the digital signal and the sampling rate conversion operation of the sampling rate conversion means are discontinued. Interpolation means for converting a digital signal into a continuous digital signal by interpolation processing, and detecting the phase of the data change point of the digital signal after converting the sampling rate with respect to the data change point of the digital signal before converting the sampling rate a phase detecting means for, based on a detection output of the phase detecting means, and control means for controlling the inner挿動operation of said interpolation means conversion operation and the sampling rate conversion unit, said phase detecting means, sampling Convert rates The digital signal
Convert the sampling rate for the data change point
After the data change point of the digital signal
A specific phase that detects a predetermined phase from among a number of phases
Detecting means and a detection output of the specific phase detecting means.
To reset to the sampling rate of the conversion destination.
By counting clock signals,
A sampling rate conversion device comprising: a counting unit that outputs a signal indicating a phase . 2. The control unit according to claim 1, wherein the control unit switches and sets interpolation coefficients for a plurality of phases detected by the phase detection unit based on a detection output of the phase detection unit. 2. The insertion operation is controlled.
The sampling rate converter according to the above. 3. The digital signal is a component signal constituting a television signal, and the sampling rate conversion means converts a sampling rate of the component signal into a sampling rate of a composite signal obtained by synthesizing the component signal. The sampling rate conversion device according to claim 1, wherein the sampling rate conversion device is configured to convert the sampling rate into a value.