JPH0888539A - Sampling rate converter - Google Patents

Abstract

PURPOSE: To provide a sampling rate converter capable of simplifying the constitution of a digital filter for interpolation without causing picture distortion. CONSTITUTION: The sampling rate of a multiplex signal R-Y/B-Y is converted by buffer memory 18. The multiplex signal R-Y/B-Y made discontinuous by such conversion is converted into a continuous signal by the interpolation processing of a delay part 21, a selection part 22 and a load addition part 23. In parallel with such operation, the phase of a data change point after sampling rate conversion for that of the data change point before sampling rate conversion is detected by 1/2-frequency dividing parts 15, 16 a specific phase detecting part 17 and a counter 24. The readout operation of the buffer memory 18 is controlled by a readout control part 20 based on a detected result, and also, the interpolation processing is controlled by a selection control part 25 and a coefficient generating part 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling rate conversion apparatus for converting a sampling rate of a digitized component signal into a sampling rate of a digitized composite signal in a television signal processing apparatus, for example.

[0002]

2. Description of the Related Art In recent years, digitalization of processing has been promoted in television signal processing devices. Along with this, digitization of processing is also attempted in an encoder for converting a component signal into a composite signal.

Here, the component signal is a signal forming a television signal, such as a luminance signal and a color difference signal. On the other hand, the composite signal is a signal obtained by modulating a color subcarrier with a color difference signal and superimposing this modulated wave on a luminance signal.

As a method of converting a component signal into a PAL-type composite signal by digital processing, there is a method of converting the sampling rate of the component signal as it is and a method of converting the sampling rate to the sampling rate of the composite signal and then converting. .

In the case of the above conversion method, an analog / digital converter for digitizing the color subcarrier and two multipliers for modulating the color subcarrier with two color difference signals are required, and the scale of hardware is increased. Has a problem that becomes large. Further, in the case of this conversion method, there is a problem that a signal conforming to the digital standard of the composite signal cannot be obtained.

On the other hand, in the case of the conversion method, such a problem does not occur. Therefore, when it is desired to obtain a signal conforming to the digital standard of the composite signal with a small hardware scale, the conversion method of is adopted.

By the way, in order to convert the component signal into the composite signal based on the above conversion method, a sampling rate conversion device for converting the sampling rate of the component signal into the sampling rate of the composite signal is required.

In this sampling rate conversion device, in addition to the function of converting the sampling rate, an interpolation function for converting a signal discontinuous due to this conversion into a continuous signal is required.

In order to realize this interpolation function, in the conventional sampling rate conversion device, an interpolation coefficient is determined according to the conversion ratio of the sampling rate, and the interpolation processing is performed using this interpolation coefficient. It was.

[0010]

However, in such a configuration, for example, when the sampling rate of the component signal is converted into the sampling rate of the PAL composite signal, the configuration of the interpolation digital filter becomes complicated. There was a problem.

This is the color subcarrier frequency f of the PAL system.
between the sc and the line frequency f _H, it is from relationship of 4fsc = {1135+ (1/625)} f H ... (1). That is, because of such a relationship, if the conversion of the sampling rate is to be performed accurately, the conversion of 540000: 709379 must be performed, and the interpolation coefficient increases.

In order to solve this problem, it can be considered to approximate the relation of the equation (1) to 4fsc = 1135f _H (2) That is, it may be considered not to consider the offset amount (4/625) f _H.

According to this structure, 864: 113
Since the conversion of 5 is sufficient, the number of interpolation coefficients can be reduced. Thereby, the configuration of the digital filter can be simplified.

However, while such a structure can simplify the structure of the digital filter,
There is a new problem that the error due to approximation appears as image distortion.

From the above, in the sampling rate conversion device for converting the sampling rate of the component signal into the sampling rate of the PAL system composite signal, the construction of the interpolation digital filter can be simplified without causing image distortion. A sampling rate conversion device capable of achieving the above is desired.

[0016]

In order to solve the above-mentioned problems, the present invention relates to the phase of the data change point of the digital signal after the sampling rate conversion with respect to the data change point of the digital signal before the sampling rate conversion. Gradually progresses for each sample, and paying attention to the point that the phase returns to the original phase at the predetermined sample, based on the phase detection means for detecting the phase and the detection result of this phase detection means,
A control means for controlling the sampling rate conversion operation and the interpolation operation is provided.

[0017]

With the above arrangement, it is possible to obtain the interpolated output corresponding to the phase at the data change point before and after the sampling rate conversion.

Further, it is possible to perform the interpolation processing by using the interpolation coefficient for the number of samples necessary for returning the phase of the data change point after the sampling rate conversion. With this, the interpolation process can be performed using a small number of interpolation coefficients, so that the configuration of the digital filter for interpolation can be simplified.

Furthermore, since the interpolation coefficient can be set based on the phase of the data change point after the sampling rate conversion with respect to the data change point before the sampling rate conversion, the conversion considering the offset amount can be performed. It can be carried out. As a result, it is possible to prevent image distortion.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the following description, the case where the present invention is applied to a sampling rate conversion device of a PAL system encoder will be described as a representative.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. However, FIG. 1 shows the configuration of the color difference signal processing unit of the PAL encoder provided with the sampling rate conversion apparatus according to an embodiment of the present invention.

In the figure, 11 is an input terminal to which a multiplexed signal of two color difference signals is supplied. Here, the sampling frequency of each color difference signal is set to 6.75 MHz. Therefore, the sampling frequency of the multiplexed signal input from the input terminal 11 is 13.5 MH
It is set to z. In the following description, for example, RY and BY are used as color difference signals.

Reference numeral 12 is synchronized with the multiplexed signal R-Y / B-Y input from the input terminal 11 and has a horizontal synchronization frequency f.
It is an input terminal to which a pulse signal S1 having the same frequency as _H is supplied.

Reference numeral 13 is synchronized with the multiplexed signal R-Y / B-Y input from the input terminal 11, and this multiplexed signal R-Y / B-Y
It is an input terminal to which a clock signal S2 having the same frequency as the sampling frequency 13.5 MHz of Y / B-Y is supplied.

An input 14 is supplied with a clock signal S3 which is synchronized with the multiplexed signal R-Y / B-Y input from the input terminal 11 and which has the same frequency as the sampling frequency 4fsc of the PAL composite signal. It is a terminal.

Reference numeral 15 denotes 1 input from the input terminal 13.
5. The clock signal S2 of 3.5 MHz is divided by 2 and 6.
It is a 1/2 frequency divider that outputs a 75 MHz clock signal S4. 16 is 4fs input from the input terminal 14
It is a 1/2 frequency divider that divides the clock signal S3 of c by 1/2 and outputs the clock signal S5 of 2fsc.

Reference numeral 17 compares the phases of the two clock signals S4 and S5 to determine the sampling rate with respect to the data change point of the color difference signal RY (or BY) before conversion of the sampling rate. A predetermined phase (hereinafter, referred to as "specific phase") out of a plurality of phases (four or five) that the data change point of the color difference signal R-Y (or B-Y) after conversion can take. It is a specific phase detection unit for detecting.

As the specific phase, for example, within one sample period of the color difference signal RY (or BY) before the sampling rate conversion, the color difference signal RY (after the sampling rate conversion is performed. Alternatively, a phase is selected so that there are two data change points of BY.

Reference numeral 18 denotes a buffer memory for converting the sampling rate of the multiplexed signal R-Y / B-Y input from the input terminal 11 into the sampling rate of the PAL composite signal.

Reference numeral 19 denotes an input terminal 1 in the buffer memory 18.
The write control unit outputs a write control signal and a write address for writing the multiplexed signal R-Y / B-Y input from 1.

The write control section 19 outputs a write control signal in synchronization with the clock signal S2 input from the input terminal 13. Further, the write control unit 19 updates the horizontal write address in synchronization with the clock signal S2 and outputs the pulse signal S input from the input terminal 12.
In synchronization with 1, the write address in the horizontal direction is initialized.

A read control unit 20 outputs a read control signal and a read address for reading the multiplexed signal RY / BY stored in the buffer memory 18.

The read control section 20 outputs a read control signal in synchronization with the clock signal S3 input from the input terminal 14. Further, the read control unit 20 updates the horizontal read address in synchronization with the clock signal S3 and outputs the pulse signal S input from the input terminal 12.
In synchronization with 1, the read address in the horizontal direction is initialized. Further, when the specific phase detection unit 17 detects the specific phase, the read control unit 20 stops the generation of the read control signal and the update of the read address only during that period.

Reference numeral 21 denotes, for example, a multiplexed signal RY / B read from the buffer memory 18 having three taps.
By delaying -Y, each color difference signal BY, RY
It is a delay unit that simultaneously outputs data for three consecutive samples X0, X1, and X2.

The delay section 21 is composed of four shift registers 211, 212, 213 and 214 connected in series. Each shift register 211, 212, 2
13 and 214 are 4 fsc input from the input terminal 14.
Of the clock signal S3.

In such a configuration, the data of the current sample X0 read from the buffer memory 18 appears at the input terminal of the shift register 211 and the output terminal of the shift register 212 is one sample before the current sample X0. The data of sample X1 appears and shift register 214
Similarly, the data of the sample X2 two samples before appears at the output terminal of the.

The delay unit 21 is configured by four shift registers instead of two shift registers because the signal read from the buffer memory 18 is multiplexed with the color difference signals RY and BY at 4 fsc. This is because it is a signal that has been processed.

Reference numeral 22 is a selection unit for selecting, for example, two samples of data D1 and D2 for interpolation from the data of three samples simultaneously output from the delay unit 21.
The selection unit 22 is configured to collect the data of the sample X2 and the sample X2.
Switch 221 for selecting one of the 1 data
And a switch 222 for selecting either the data of the sample X1 or the data of the sample X2.

Reference numeral 23 is a load addition unit for adding the weights of the two samples of data D1 and D2 selected by the selection unit 22 using the interpolation coefficients k1 and k2. This load addition unit 23
Is the interpolation coefficient k for the data D1 selected by the switch 221.
A multiplier 231 that multiplies 1 and a multiplier 232 that multiplies the data D2 selected by the switch 222 by the interpolation coefficient k2.
And an adder 233 that adds the multiplication outputs of the two multipliers 231 and 232.

Reference numeral 24 is a detection signal S of the specific phase detection section 15.
By counting the 2 fsc clock signal S5 that is reset by 6 and is output from the 1/2 frequency divider circuit 16, the data change point before the sampling rate conversion can be taken as the data change point after the sampling rate conversion 4 It is a counter that outputs a signal indicating one or five phases.

25 is a count value S of the counter 24
7 is a selection control unit that controls the selection operation of the selection unit 22 based on 7.

Numeral 26 is an interpolation coefficient k1, k supplied to the load adder 23 based on the count value S7 of the counter 24.
2 is a coefficient generation unit that generates 2.

Reference numeral 27 represents the color difference signal R-Y and the color difference signal B- from the multiplex signal R-Y / B-Y output from the weight addition unit 23.
It is a separation unit that separates into Y.

The separating unit 27 is driven by the 4 fsc clock signal S3 input from the input terminal 14, and the shift register 271 is output from the 1/2 frequency dividing unit 16.
The shift registers 272 and 273 are driven by the fsc clock signal S5, and are configured to perform the above-described separation. Note that the drawing shows the case where the color difference signal RY is output from the shift register 272 and the color difference signal BY is output from the shift register 273.

Reference numeral 28 is a low pass filter for band limiting the color difference signal RY output from the shift register 272. Reference numeral 29 is a low-pass filter that band-limits the color difference signals BY output from the shift register 273.

Reference numeral 30 denotes a modulator for modulating the color difference signal RY band-limited by the low pass filter 28 and the color difference signal B-Y band limited by the low pass filter 29. Reference numeral 31 is an output terminal to which the modulated output of the modulator 30 is supplied.

In the above configuration, the 1/2 frequency division section 15,
16, a specific phase detection unit 17, and a buffer memory 18
A write control unit 19, a read control unit 20, a delay unit 21, a selection unit 22, a load addition unit 23, and a counter 2.
4, the selection control unit 25, and the coefficient control unit 26 constitute the sampling rate conversion device of this embodiment.

In this sampling rate conversion device, the 1/2 frequency dividers 15 and 16 and the specific phase detector 17 are provided.
The counter 24 constitutes a phase detecting means.
Further, the buffer memory 18, the write controller 19, and the read controller 20 constitute a sampling rate conversion means. Further, the delay unit 21, the selection unit 22, and the load addition unit 23 constitute an interpolation means. Further, the read control unit 20, the selection control unit 25, and the coefficient generation unit 26 constitute control means.

In the above structure, referring to FIG.
The operation will be described. 2. FIG. 2 is a timing chart showing the operation of FIG.

First, the outline of the operation of one embodiment will be described.
In FIG. 1, conversion of the sampling rate of the color difference signal RY and conversion of the sampling rate of the color difference signal BY are performed. However, the conversion operation of both is the same. Therefore, in the following description, the conversion operation of the color difference signal R-Y will be described as a representative.

FIG. 2A shows a data string of the color difference signal RY before conversion of the sampling rate. That is,
A data string of 6.75 MHz is shown. On the other hand, FIG. 6B shows a data string of the color difference signal RY after the sampling rate is converted. That is, a 2 fsc data string is shown.

As shown in the figure, the phase of the change point of the 2fsc data gradually advances with respect to the phase of the change point of the 6.75 MHz data for each sample and returns to the original phase at the fourth sample. . However, due to the relationship between the sampling rates of the two, it does not completely return to the original phase, and
At the 5th sample once, there is a part that returns to the original phase.

In any case, however, the phase of the change point of the 2fsc data changes in a predetermined repeating pattern with respect to the phase of the change point of the 6.75 MHz data.

In this embodiment, focusing on this point, 6.75.
The phase of the data change point of 2fsc with respect to the phase of the data change point of MHz is detected, the read operation of the buffer memory 18 is controlled based on this detection output, and the interpolation coefficient according to this read data is assigned. It is a thing.

That is, the reading of data is stopped only for one sample period every 4 samples of 2 fsc data or every 5 samples, and the interpolation coefficient corresponding to the read data is assigned.

With such a configuration, it is possible to obtain an interpolated output corresponding to the phase of the data change point before and after the sampling rate conversion.

Further, the interpolation processing can be executed only by switching at least four or five interpolation coefficients. Thereby, the configuration of the digital filter can be simplified.

By the way, as a method of detecting the phase of the change point of the 2fsc data with respect to the 6.75 MHz data change point, a method of detecting the actual phase of each change point of the 2fsc data can be considered. However, with this method, the configuration may be complicated.

Therefore, in this embodiment, 6.75 MHz
Of the four or five phases that the data change point of 2 fsc can take with respect to the data change point of 2 fsc, a predetermined specific phase is detected, and this detection output is used as a reset signal.
By counting the clock signal S5 of fsc,
It is designed to detect all four or five phases.

According to such a configuration, four or five
By detecting substantially one of the two phases, the detection output of all phases can be obtained, so the phase detection configuration is simpler than the configuration that actually detects all phases. You can

Here, as the specific phase, as described above,
2 fsc in one sample period of 6.75 MHz data
The phase of the portion where there are two data change points is defined.

That is, paying attention to the data change point of 2fsc, as is clear from FIGS. 2A and 2B, there are two such change points in the period of one sample of 6.75 MHz data. There are cases and one case. If there are two of them, they appear only once every 4 or 5 sample periods of 2fsc data.

Therefore, the data change point of 2fsc is 2
If one of the two phases is detected, and this detection output is used as a reset signal to count the clock signal of 2 fsc, by substantially detecting one phase,
All four or five phases can be detected.

The above is the outline of the operation of the embodiment. Next, this operation will be described with reference to FIG. Input terminal 11
First, the sampling rate of the multiplexed signal R-Y / B-Y input from is converted by the buffer memory 18, the write control unit 19, and the read control unit 20.

Next, this conversion output is subjected to interpolation processing by the delay unit 21, the selection unit 22, and the weight addition unit 23. As a result, the multiplexed signal R-Y / B-Y, which is discontinuous due to the conversion of the sampling rate, is converted into a continuous signal.

Finally, this converted output is
It is modulated by the low-pass filters 28 and 29 and the modulator 30. As a result, the carrier color signal is obtained. The carrier color signal is output from the output terminal 31 and is combined with the brightness signal supplied from the brightness signal processing unit (not shown).

The above operation will be described in detail below. Multiplex signal RY / input from the input terminal 11
BY is sequentially written in the buffer memory 18 in synchronization with the 13.5 MHz clock signal S2 by the write control unit 19.
Is written to.

The data string written in the buffer memory 18 is sequentially read by the read control unit 20 in synchronization with the 4 fsc clock signal S3. As a result, the frequency of the multiplexed signal R-Y / B-Y is converted from 13.5 MHz to 4 fsc.

In parallel with this read operation, the specific phase detector 17 compares the phases of the clock signals S4 and S5.
Here, the frequencies of the clock signals S4 and S5 are 6.75 MHz and 2 fsc, respectively, and both signals S4 and S5 are
S5 is synchronized. Therefore, by this phase comparison, a phase (specific phase) in which two 2fsc data change points exist in one sample period of 6.75 MHz data is detected.

As shown in FIG. 2C, the detection signal S6 of the specific phase has a high level in a portion having only one change point, and has a low level in a portion having two change points. The signal becomes The detection signal S6 is supplied to the read control unit 20 and the counter 24.

The read control unit 20 executes the read operation when the detection signal S6 is at the high level, and when the detection signal S6 is at the low level, stops the read for that period. As a result, the read output of the buffer memory 18 is such that one sample of data is lost every four or five samples, as shown in FIG. That is, the color difference signal R-Y and the color difference signal B-Y for one sample are missing every four or five samples.

On the other hand, the counter 24 is reset at the rising timing of the detection signal S6 and counts the 2fsc clock signal S5. As a result, quaternary and quinary counters are configured as shown in FIG. The count value S7 of the counter 24 indicates the phase of the data change point of 2fsc with respect to the data change point of 6.75 MHz.

The data string read from the buffer memory 18 is delayed by one sample by the delay unit 21. As a result, as shown in FIGS. 2 (e), (f), and (g),
Data for three consecutive samples (X0, X1, X2) are simultaneously output. At this time, the data of the color difference signal R-Y and the data of the color difference signal B-Y are alternately output at a cycle of 1 / (4fsc).

The data for three samples output from the delay unit 21 is supplied to the selection unit 22. The selection unit 22 selects the data D for two samples from the data for three samples.
1, D2 are selected as data for interpolation.

This selection operation is performed on the basis of the count value S7 of the counter 24 (see FIG. 2 (d)).
Controlled by. The selection control unit 25 basically does not select the missing data from the data of the three samples, and the data D newly created by the interpolation processing.
The selection operation of the selection unit 22 is controlled so as to select two data D1 and D2 having a strong correlation with 3.

Data D1 and D2 selected by the selection unit 22
Is supplied to the weight adding unit 23, and the weight is added based on the interpolation coefficients k1 and k2. As a result, the signal that is discontinuous due to the conversion of the sampling rate is converted into a continuous signal. The data D3 obtained by this interpolation processing is shown in FIG.

The interpolation coefficients k1 and k2 are output from the coefficient generator 26 based on the count value S7 of the counter 24. The coefficient generator 26 basically selects the interpolation coefficients k1 and k2 according to the strength of the correlation between the data D3 and the data D1 and D2 from a plurality of predetermined coefficients, and selects the interpolation coefficients k1 and k2. It is adapted to be applied to the multipliers 231 and 232.

FIG. 3 shows an example of the interpolating process in the part that constitutes the quaternary counter, and FIG. 4 shows an example of the interpolating process in the part that constitutes the quinary counter.

As described above, as the data D1 and D2,
The one having a strong correlation with the data D3 is selected. For this reason,
For example, when the data (7) 'is created as the data D3, the data (5) and (6) are selected as the data D1 and D2, respectively, as shown in FIG. Note that, in FIG. 2, double brackets indicate data that is not selected.

The interpolation coefficients k1 and k2 are 2f.
Assuming that the phase of the change point of sc data changes in n sample periods, n pieces are prepared for each. The values of the interpolation coefficients k1 and k2 are set to be natural numbers times 1 / n, for example.

In this case, k1 + k2 is naturally set to 1. Therefore, as the interpolation coefficient k1,
When n coefficients of 1 / n, 2 / n, ..., (n-1) / n, 1 are prepared, the interpolation coefficient k2 is (n-
N coefficients of 1) / n, (n-2) / n, ..., 1 / n, 0 are prepared.

In this example, n is 4 and 5.
Therefore, where a quaternary counter is configured, four coefficients each having a natural number multiple of 1/4 are prepared as the interpolation coefficients k1 and k2. On the other hand, where a quinary counter is configured, five coefficients that are natural numbers times 1/5 are prepared.

However, in this embodiment, even in the part in which the quinary counter is constructed, the same interpolation coefficient as in the part in which the quaternary counter is constructed by using a certain coefficient twice as shown in FIG. k1 and k2 are used. This is because, since the part that constitutes the quinary counter is much smaller than the part that constitutes the quaternary counter, the simplification of the structure is prioritized and four types of coefficients are used for each.

In the example of FIG. 4, by using the same interpolation coefficients k1 and k2 as in the fourth sample in the fifth sample,
In the portion that constitutes the quinary counter, the same interpolation coefficients k1 and k2 as in the portion that constitutes the quaternary counter are used.

In the fifth sample, the interpolation coefficients k1 and k2 of the immediately preceding fourth sample are used, because the interpolation coefficients k1 and k2 of the sample closer to the own sample are used, the signal quality is deteriorated. This is to prevent as much as possible. From this meaning, the interpolation coefficients k1 and k2 of the first sample of the next period may be used in the fifth sample of a certain period.

Data D obtained by the above-mentioned interpolation processing
3 is supplied to the separation unit 27 and separated into color difference signal RY data and color difference signal BY data. Each data is
The band is limited by the corresponding low-pass filters 28 and 29, and then modulated by the modulator 30.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the phase of the data change point after sampling rate conversion with respect to the data change point before sampling rate conversion is detected,
Based on this detection output, the read operation of the buffer memory 18 is controlled, and the corresponding interpolation coefficient k1,
Since k2 is assigned, it is possible to obtain an interpolated output corresponding to the phase of the change point of the data before and after the sampling rate conversion.

Further, at least four kinds of interpolation coefficients k1,
Since the interpolation processing can be performed only by switching k2, the interpolation processing can be performed using a small number of interpolation coefficients. As a result, the structure of the interpolation digital filter can be simplified.

Further, since the interpolation coefficients k1 and k2 can be set based on the phase of the data change point after the sampling rate conversion with respect to the data change point before the sampling rate conversion, the offset amount (1/625) f It is possible to perform the conversion considering _H. As a result, the image distortion can be prevented even though the configuration of the digital filter can be simplified.

(2) According to this embodiment, the specific phase is selected from the four or five possible phases of the data change point after the sampling rate conversion with respect to the data change point before the sampling rate conversion. The clock signal S5 of 2 fsc is detected by using the detection result as a reset signal.
Since all the remaining phases are detected by counting, the phase detection configuration can be simplified as compared with the case of directly detecting all the phases.

(3) According to this embodiment, as the specific phase, a phase in which there are two data change points after the sampling rate conversion in one sample period of the data before the sampling rate conversion is detected. As a result, the configuration for detecting the specific phase can be simplified as compared with the case of detecting the phase in which only one data change point exists.

This is because when a phase having only one data change point is detected as the specific phase,
This is because, since there are three or four such phases, it is necessary to identify a predetermined specific phase from the plurality of phases.

(4) Further, according to this embodiment, when the sampling rate is converted, the sampling rate is converted to 4 fsc. Therefore, the structure of the modulator 30 can be simplified and the composite signal can be obtained. The digital standard of can also be satisfied.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

(1) For example, in the above embodiment, the present invention is applied to the sampling rate of the component signal PA.
The case where the present invention is applied to the sampling rate conversion device for converting the sampling rate of the L-system composite signal has been described.

However, the present invention can also be applied to a sampling rate conversion device for converting the sampling rate of a component signal into the sampling rate of an NTSC composite signal.

When converting the sampling rate of the component signal into the sampling rate of the composite signal of the NTSC system, a hexadecimal counter is configured as the counter as described above.

(2) Further, in the above embodiment, the case where the present invention is applied to the sampling rate conversion device for converting the sampling rate of the component signal into the sampling rate of the composite signal has been described.

However, the present invention can also be applied to a sampling rate conversion device for converting the sampling rate of a composite signal into the sampling rate of a component signal.

In this case, the sampling rate conversion is
For example, the data may be thinned out based on the phase detection result. However, in this case, the interpolation processing needs to be performed using the thinned data.

(3) Further, the present invention is applicable not only to a sampling rate conversion device for converting a sampling rate of a television signal such as a component signal or a composite signal, but also to a sampling rate conversion device for converting a sampling rate of a general digital signal. Can also be applied.

(4) In addition to this, it is needless to say that the present invention can be variously modified without departing from the scope of the invention.

[0104]

As described above in detail, according to the present invention, it is possible to provide a sampling rate conversion device which can simplify the structure of a digital filter for interpolation without causing image distortion. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment.

FIG. 3 is a diagram showing an example of an interpolation process in a quaternary counter portion of one embodiment.

FIG. 4 is a diagram showing an example of an interpolation process in a quinary counter portion of one embodiment.

[Explanation of symbols]

11, 12, 13, 14 ... Input terminals 15, 16 ... 1/2 frequency division section 17 ... Specific phase detection section 18 ... Buffer memory 19 ... Write control section 20 ... Read control section 21 ... Delay section 22 ... Selection section 23 ... Load addition unit 24 ... Counter 25 ... Selection control unit 26 ... Coefficient generation unit 27 ... Separation unit 28, 29 ... Low-pass filter 30 ... Modulation unit 31 ... Output terminal 211, 212, 213, 214, 271, 272, 2
73 ... Shift register 231, 232 ... Multiplier 233 ... Adder

Claims (4)

[Claims] 1. A sampling rate conversion device for converting a sampling rate of a digital signal, wherein sampling rate conversion means for converting the sampling rate of the digital signal and sampling rate conversion operation of the sampling rate conversion means result in discontinuity. Interpolation means for converting a digital signal into a continuous digital signal by interpolation processing, and detection of the phase of the data change point of the digital signal after conversion of the sampling rate with respect to the data change point of the digital signal before conversion of the sampling rate And a control means for controlling the conversion operation of the sampling rate conversion means and the interpolation operation of the interpolation means based on the detection output of the phase detection means. Converter. 2. The phase detecting means has a plurality of phases of data change points of the digital signal before conversion of the sampling rate, which can be taken by data change points of the digital signal after conversion of the sampling rate. A specific phase detecting means for detecting a predetermined phase from the inside, and resetting based on the detection output of the specific phase detecting means, by counting the clock signal corresponding to the sampling rate of the conversion destination, the plurality of phases 2. The sampling rate conversion device according to claim 1, further comprising a counting means for outputting a signal indicating 3. The interpolation means is configured to switch and set the interpolation coefficients for a plurality of phases detected by the phase detection means, based on the detection output of the phase detection means. The insertion operation is controlled, and the insertion operation is controlled.
The sampling rate conversion device described. 4. The digital signal is a component signal that constitutes a television signal, and the sampling rate conversion means obtains a sampling rate of the component signal by combining the sampling rate of the component signal with the sampling rate of the composite signal. The sampling rate conversion device according to claim 1, wherein the sampling rate conversion device is configured to perform conversion into