JPH0420178A - Video signal processor - Google Patents

Abstract

PURPOSE:To freely set gain correcting accuracy irrespective of clock frequency at modulating in a pulse width modulating circuit by integrating only the signal equipment to bit number digitally before the signal equivalent to the bit number is abandoned in a second coefficient circuit and adding the carry signal to a high order bit. CONSTITUTION:Only the signal equivalent to bit number is integrated and the carry signal is added to a high order bit before the signal equivalent to bit number is abandoned from the lowest order bit with making fixed coefficient times in a coefficient circuit 606 by providing a low order bit integrating circuit 101. Accordingly, since the signal of the low order bit is reflected to the high order bit even when it is made coefficient times in the coefficient circuit 606, accurate gain correcting can be executed without degrading the detecting accuracy of an erroneous signal. Thus, gain correcting accuracy can be set freely irrespective of clock frequency at modulating in a pulse width modulating circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device for performing digital signal processing by AD (analog-to-digital) conversion of a video signal having a synchronization signal such as a television digital signal. It is something.

2. Description of the Related Art In recent years, analog video signals are often converted into digital video signals using an AD converter (hereinafter referred to as ADC) for signal processing. At this time, a video signal processing device is required that includes an automatic gain control circuit (hereinafter referred to as AGC) that maintains the gain of the video signal at a predetermined value.

An example of a conventional video signal processing device will be described below with reference to the drawings.

FIG. 6 shows a block diagram of a conventional video signal processing device.

First, an analog video signal is input to the analog video signal input terminal 610. Then, the variable gain amplifier 601 corrects the error gain output from the integrator 608. The analog video signal corrected to a predetermined gain by the variable gain amplifier 601 is converted into a digital video signal of a predetermined number of bits by an ADC (AD converter) 602 using a clock of a predetermined frequency.

A detection circuit 603 detects the sync level of the digital video signal, that is, the value obtained by subtracting the sync tip level from the pedestal level. The subtracter 6 subtracts the sync level and the reference sync level input to the reference value input terminal 612.
04 to obtain an error signal, and further a coefficient circuit 605 to set a predetermined time constant of the entire feedback system.
is multiplied by a predetermined coefficient, and further multiplied by a predetermined coefficient in a coefficient circuit 606 for pulse width modulation in a PWM 607. This detection circuit 603. Subtractor 604. Coefficient circuit 605.606
．． The reference value input terminal 612 is the gain control circuit 609. By subjecting the output signal of the coefficient circuit 606 to pulse width modulation using the PWM 607 and further integrating it using the integrator 608, an error gain for correction by the variable gain amplifier 801 is obtained. As a result, even if the gain of the input analog video signal fluctuates, the error gain follows the fluctuating sync level based on the time constant set by the coefficient circuit 605, and the sync level of the analog video signal output from the variable gain amplifier 801. is equal to the reference sink level. This is called a sink level feedback type AGC, that is, a keyed AGC. This allows the input analog video signal to
It falls within the dynamic range of 0.02 and can be effectively AD converted. However, this keyed AGC is normally used in conjunction with a peak level feedback type AGC1, that is, a peak AGC, which performs gain correction on the peak level (beak Φ to peak value) of the input signal to a constant value. I will only describe it.

Problems to be Solved by the Invention In such conventional video signal processing devices, the following two problems occur.
There are two issues.

One is, for example, when the clock frequency is 13.5 MHz when performing pulse width modulation with PWM607, and the variable gain amplifier 6
If the period of correction with 01 is once per horizontal synchronization period of the input analog video signal (for example, 63.5 μs e c for an NTSC standard television signal), then 63.
Since 5 μsec corresponds to approximately 857 clocks of a 13.5 MHz clock, the input dynamic range of the PWM 507 is limited to 10 bits (=±512), and if the output of the coefficient circuit 605 is 13 bits, the coefficient circuit 606
must be multiplied by 1/8, and the detection accuracy of the error signal is 3
The gain decreases by the amount of bit, making it impossible to accurately correct the gain. That is, the problem is that the gain correction accuracy is determined by the clock frequency used when modulating with the PWM 607, regardless of the required accuracy.

The other reason is that because the gain control circuit 609 is composed of a digital circuit, even in a stable state in which the sync level of the input analog video signal is gain-corrected to the reference sync level, only the ILSB of the output of the coefficient circuit 806 remains. For example, if the gain of the input analog video signal is lVpp and the number of input bits of the PWM807 is 10
bit, the output of the variable gain amplifier 601 is 115
12VPP fluctuates. This is because when the digital video signal output to the digital video signal output terminal 511 is converted to DA (digital-to-analog) and viewed on a monitor screen, the brightness signal flickers in each horizontal period, causing an unsightly so-called line flicker. This is the issue.

In view of the above problems, the present invention solves the first problem by
We provide a video signal processing device that can freely set the gain correction accuracy regardless of the clock frequency when modulating with M507, and for the second problem, when the AGC enters a steady state, the gain of the output digital video signal An object of the present invention is to provide a video signal processing device that does not have fluctuations in the signal.

Means for Solving the Problems In order to achieve the above objects, the video signal processing device of the present invention includes a variable gain amplifier that corrects the gain of an analog video signal with the output of an integrator, and a variable gain amplifier that corrects the gain of the analog video signal using the output of an integrator. An AD converter that converts into a digital video signal using a clock, a detection circuit that detects a sync level of the output of the AD converter, a subtracter that subtracts a reference sync level and the output of the detection circuit, and an output of the subtracter. a first coefficient circuit that inputs and multiplies it by a predetermined coefficient; a lower bit integrator circuit that integrates only a predetermined number of bits from the least significant bit of the output of the first coefficient circuit; and an output of the lower bit integrator circuit. A second coefficient circuit that multiplies the output by a predetermined coefficient, a pulse width modulation circuit that pulse width modulates the output of the second coefficient circuit, and the integrator that integrates the output of the pulse width modulation circuit. be.

The present invention also provides a variable gain amplifier that corrects the gain of an analog video signal with the output of an integrator, an AD converter that converts the output of the variable gain amplifier into a digital video signal at a predetermined clock, and a a detection circuit that detects a sync level of an output; a subtracter that subtracts the output of the detection circuit from a reference sync level; a first coefficient circuit that multiplies the output of the subtracter by a predetermined coefficient; and the first coefficient. a second coefficient circuit that multiplies the output of the circuit by a predetermined coefficient; a pulse generation circuit that generates a pulse when the output of the subtracter is within a predetermined level; a switch means for switching between output and zero level;
The device includes a pulse width modulation circuit that pulse width modulates the output of the switch means, and the integrator that integrates the output of the pulse width modulation circuit.

Operation The present invention has the above-mentioned configuration, and can solve the first problem by digitally integrating only the 3-bit signal before 178 and discarding the 3-bit signal in the second coefficient circuit. By adding the carry signal to the upper bits, even if the second coefficient circuit performs 178, the signal of the lower bits is reflected in the upper bits, so that gain correction can be performed accurately without reducing the detection accuracy of the error signal.

For the second problem, when the error signal that is the output of the subtracter falls within a predetermined level range, that is, when the AGC
When the signal reaches a steady state, the PWM input is fixed to zero, so that the gain of the analog video signal output from the variable gain amplifier does not change at all, so no line flicker occurs when viewed on a monitor screen.

Embodiment Hereinafter, a video signal processing device according to an embodiment of the present invention will be described.
This will be explained with reference to the drawings.

However, the same components as those of the conventional video signal processing device shown in FIG. 6 are given the same reference numerals, and explanations of their operations will be omitted.

FIG. 1 shows a block diagram of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 shows a block diagram of the lower bit integration circuit 101 in the video signal processing device of FIG. 1.

A lower bit integration circuit 101 integrates only a predetermined lower bit of the output of the coefficient circuit 605, and outputs an error signal obtained by adding the carry output to the upper bit. The output of the lower bit integration circuit 101 is multiplied by a predetermined coefficient in a coefficient circuit 606. This detection circuit 603, subtracter 6o4. Coefficient circuit 6
05. Lower bit integration circuit 101. Coefficient circuit 606. The reference value input terminal θ12 is the gain control circuit 102. The number of lower bits integrated by the lower bit integration circuit 101 matches the number of lower bits discarded by the coefficient circuit 606. For example, when the coefficient circuit 606 integrates 178, the lower 3 bits are integrated by the lower bit integration circuit 101, and the number of lower bits is also 1. When it is /4, the lower 2 bits are integrated, and when it is 1/1B, the lower 4 bits are integrated.
Integrate t.

This lower bit integration circuit 101 is included in a gain control circuit 102.

The lower bit integration circuit 101 will now be explained using FIG. 6. An adder 201 adds the input of the lower bit integration circuit 101, that is, the signal input to the input terminal 204, and the output of the delay circuit 203. The output of the adder 201 is input to the lower bit extractor 202. A predetermined number of bits are extracted from the least significant bit. The predetermined number of bits is the number of lower bits integrated by the lower bit integrator 101 described above. The output of the lower bit extractor 202 is delayed by a predetermined period in a delay circuit 203. The predetermined delay corresponds to the period corrected by the variable gain amplifier 601 and is one horizontal opening period. The output of the adder 201 is sent to the output terminal 20
5, and this is the output of the lower bit integration circuit 101.

FIG. 3 shows a block diagram of a video signal processing device according to a second embodiment of the present invention.

The error signal which is the output of the subtracter 604 is sent to the pulse generation circuit 3.
For example, if the error signal is within the range of ±4 steps, it is defined that the AGC is in the holding mode, and the output pulse is set to high level. If it is outside the range of ±4 steps, the pulse is set to low level. Switch means 3
The output of the coefficient circuit 606 and the zero level input to the zero level input terminal 304 are input to 01, and when the pulse is at a low level, the output of the coefficient circuit 606 is input to the switch means 3.
01 output, and when it is at a high level, that is, in the holding mode, it is switched to the zero level input terminal 304 side.

These pulse generating circuits 302 and switch means 301.
Gain control circuit 30 including zero level input terminal 304
Set it to 3.

FIG. 4 shows a block diagram of a video signal processing device according to a third embodiment of the present invention.

The difference from the second embodiment is that the variable gain amplifier 4.1 and the integrator 402 are constructed with digital circuits, but their operation is the same as when constructed with analog circuits. For example, variable gain amplifier 401 can be realized by a multiplier. By using a digital circuit, there is no need for PWM to convert the error gain into an analog signal.

FIG. 5 shows a block diagram of a video signal processing device according to a fourth embodiment of the present invention. This embodiment is configured by combining the lower bit integration circuit 101 of the first embodiment, the switch means 201, the pulse generation circuit 202, and the zero level input terminal 204 of the second embodiment. Therefore, this fourth embodiment is similar to P in the first embodiment.
The advantage is that the gain correction accuracy can be freely set regardless of the clock frequency when modulating with WM607, and when the AGC in the second embodiment reaches a steady state, the PW
This video signal processing device has the effect that the gain of the analog video signal output from the variable gain amplifier 601 does not change at all by fixing the input of the M607 to zero.

Effects of the Invention As described above, according to the present invention, by providing the lower bit integration circuit 101, the coefficient circuit 606 multiplies the signal by a predetermined coefficient and discards the signal for a predetermined number of bits starting from the least significant bit. By digitally integrating only the signal for that number of bits before storage and adding the carry signal to the upper bits, even if the coefficient circuit 606 multiplies the coefficient, the signal of the lower bits is reflected in the upper bits. , it is possible to accurately correct the gain without reducing the detection accuracy of the error signal. That is, the gain correction accuracy can be freely set regardless of the clock frequency when modulating with the PWM 607.

Further, by providing a pulse generation circuit 302, a switch means 301, and a zero level input terminal 304, the subtracter 6
When the error signal that is the output of the variable gain amplifier 601 falls within a predetermined level range, that is, when the gain correction is in a steady state, the input of the PWM 607 is fixed to zero, and the analog video signal that is the output of the variable gain amplifier 601 is Since the gain does not change at all, no line flicker occurs when viewed on a monitor screen.

In this way, it is extremely useful when performing digital signal processing on video signals, and has great industrial value.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a video signal processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a lower bit integration circuit in the first and fourth embodiments, and FIG. Figure 3 shows the second embodiment of the present invention.
FIG. 4 is a block diagram of a video signal processing device according to a third embodiment of the present invention,
FIG. 5 is a block diagram of a video signal processing device according to a fourth embodiment of the present invention, and FIG. 6 is a block diagram of a conventional video signal processing device. 101...lower bit integration circuit, 102, 303
．． 403,501...gain control circuit, 201.
... Adder, 202 ... Lower bit extractor, 2
03...Delay circuit, 301...Switch means,
302...Pulse generation circuit, 304...Zero level input terminal, 401.601...Variable gain amplifier, 408.602...Integrator, 602...A
DC1603...Detection circuit, 604...Subtractor, 605°606...Coefficient circuit, 607...
・PWM.

Claims (4)

[Claims] (1) A variable gain amplifier that corrects the gain of an analog video signal with the output of an integrator, an AD converter that converts the output of the variable gain amplifier into a digital video signal at a predetermined clock, and an output of the AD converter. a detection circuit that detects a sync level that is a value obtained by subtracting a sync tip level from a pedestal level; a subtracter that subtracts the output of the detection circuit from a reference sync level; and inputting the output of the subtracter and multiplying it by a predetermined coefficient. a first coefficient circuit; a lower bit integration circuit that integrates only a predetermined number of bits from the least significant bit of the output of the first coefficient circuit; and a second lower bit integration circuit that multiplies the output of the lower bit integration circuit by a predetermined coefficient.
A video signal processing device comprising: a coefficient circuit; a pulse width modulation circuit that pulse width modulates the output of the second coefficient circuit; and the integrator that integrates the output of the pulse width modulation circuit. (2) a variable gain amplifier that corrects the gain of an analog video signal with the output of an integrator; an AD converter that converts the output of the variable gain amplifier into a digital video signal at a predetermined clock; a detection circuit that detects a sync level; a subtracter that subtracts the output of the detection circuit from a reference sync level; a first coefficient circuit that multiplies the output of the subtracter by a predetermined coefficient; a second coefficient circuit that multiplies the output by a predetermined coefficient; a pulse generation circuit that generates a pulse when the output of the subtracter is within a predetermined level; and a pulse generator that multiplies the output of the second coefficient circuit by the pulse. A video signal processing device comprising: switch means for switching a zero level; a pulse width modulation circuit for pulse width modulating the output of the switch means; and the integrator for integrating the output of the pulse width modulation circuit. (3) an AD converter that converts an analog video signal into a digital video signal at a predetermined clock; a variable gain amplifier that corrects the gain of the output of the AD converter with the output of an integrator; a detection circuit that detects a sync level; a subtracter that subtracts the output of the detection circuit from a reference sync level; a first coefficient circuit that multiplies the output of the subtracter by a predetermined coefficient; a second coefficient circuit that multiplies the output by a predetermined coefficient; a pulse generation circuit that generates a pulse when the output of the subtracter is within a predetermined level; and a pulse generator that multiplies the output of the second coefficient circuit by the pulse. A video signal processing device comprising: a switch for switching a zero level; and the integrator for integrating an output of the switch. (4) a variable gain amplifier that corrects the gain of an analog video signal with the output of an integrator; an AD converter that converts the output of the variable gain amplifier into a digital video signal at a predetermined clock; a detection circuit that detects a sync level; a subtracter that subtracts the reference sync level and the output of the detection circuit; a first coefficient circuit that inputs the output of the subtracter and multiplies it by a predetermined coefficient; and the first coefficient. a lower bit integration circuit that integrates only a predetermined number of bits from the least significant bit of the output of the circuit; and a second lower bit integration circuit that multiplies the output of the lower bit integration circuit by a predetermined coefficient.
a coefficient circuit; a pulse generating circuit that generates a pulse when the output of the subtracter is within a predetermined level; and a switch means that switches between the output of the second coefficient circuit and a zero level using the pulse; A video signal processing device comprising: a pulse width modulation circuit that pulse width modulates the output of the switching means; and the integrator that integrates the output of the pulse width modulation circuit.