JPS6153884A - Video signal processing device - Google Patents

Abstract

PURPOSE:To decrease the deterioration of S/N of a video signal due to quantitizing noise by adding a positive polarity synchronizing signal to a video signal and demodulating the video signal having a negative polarity synchronizing signal after applying A/D conversion, signal processing and D/A conversion. CONSTITUTION:A video signal from a terminal 6 is added to a positive polarity synchronizing signal and supplied to an A/D converter 2 by a synchronizing signal adding circuit 1. The A/D converted video signal is processed at a signal processing circuit 3, and after that, the signal is supplied to a D/A converter 4. The D/A converted video signal is reloaded to the video signal having a negative synchronizing signal by a synchronizing signal reloading circuit 5. In such a way, since the video signal to which the positive polarity synchronizing signal is added is A/D converted, resolution can be improved. Thus, the deterioration of S/N of a video signal due to a quantitizing noise can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device for electronic equipment that converts a video signal from analog to digital and then converts it from digital to analog again.

Conventional Structures and Problems There has been a trend in recent years to process video signal circuits with digital signals in televisions or video tape recorders (hereinafter abbreviated as VTR). In such electronic devices, analog video signals must be converted to digital video signals, and digital video signals must be converted to analog video signals.

Conventionally, video signals with horizontal synchronization signals were converted into analog/
When digital conversion is performed, the horizontal synchronization signal without video information is also quantized in two ways, which reduces the resolution for effectively converting video information from analog to digital, resulting in a problem of deteriorating the signal-to-noise ratio of the video signal. there were.

To solve the above problem, remove the horizontal sync signal,
It is conceivable to convert only the video information of the video signal from analog to digital. However, when a digitally converted video signal is converted from digital to analog, it becomes a video signal without a horizontal synchronizing signal, and in order to obtain a video signal with a horizontal synchronizing signal added, information on the time and amplitude of the horizontal synchronizing signal is required. must be memorized accurately. Furthermore, it is extremely difficult to reproduce video information and horizontal synchronization signals without time lag.

OBJECTS OF THE INVENTION An object of the present invention is to provide a video signal processing device that reduces deterioration in the signal-to-noise ratio of a video signal due to quantization noise in a device that converts a video signal from analog to digital and then converts it from digital to analog again. There is a particular thing.

Constituent structure of the invention A synchronization signal adding circuit that adds a positive synchronization signal to a video signal, an analog/digital conversion circuit that converts the video signal having the positive polarity synchronization signal into digital, and a video signal converted to digital. It consists of a signal processing circuit that processes the digital video signal digitally, a digital/analog conversion circuit that converts the digitally processed video signal to analog, and a synchronization signal restoration circuit that restores the negative polarity synchronization signal. This allows digital signal processing to be performed without impairing the time relationship between information and synchronization signals.

DESCRIPTION OF EMBODIMENTS As shown in FIG. 1A, a video signal whose video information and horizontal synchronization signal are on different sides of the pedestal level Ep is referred to as a video signal with a negative polarity synchronization signal. A video signal in which the video information and the horizontal synchronization signal are on the same side of the pedestal level Ep as shown in B will be referred to as a video signal with a positive synchronization signal.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a schematic diagram of a video signal processing apparatus according to an embodiment of the present invention. In FIG. 2, 1 is a synchronization signal addition circuit that adds a positive polarity synchronization signal, 2 is an analog/digital conversion circuit, 6 is a signal processing circuit, 4 is a digital/analog conversion circuit,
5 is a synchronization signal restoration circuit for restoring a synchronization signal, 6 is an input terminal, and 7 is an output terminal.

The operation of the video signal processing apparatus of this embodiment configured as described above will be described below.

First, the video signal shown in FIG. 1A is input to the synchronization signal addition circuit 1 via the input terminal 6.

The synchronization signal addition circuit 1 outputs a video signal to which a positive polarity synchronization signal is added as shown in FIG. Ep becomes the maximum voltage HMAX of the video signal, the necessary video information part is converted from analog to digital by the analog/digital conversion circuit 2, and the signal processing circuit 3 converts the necessary video information from analog to digital.
The digitally converted video signal is subjected to digital signal processing and input to the digital/analog conversion circuit 4, where it is converted into an analog video signal. A video signal having a positive polarity synchronization signal converted into an analog signal is input to the synchronization signal restoration circuit 5, and the synchronization signal restoration circuit 6 restores the video signal to a video signal having a positive polarity and the same 7-part signal. Output a signal.

As described above, according to this embodiment, a positive polarity synchronization signal is added to a video signal, analog/digital conversion is performed, signal processing is performed, digital/analog conversion is performed, and a positive polarity synchronization signal is used to generate a negative polarity. By restoring the video signal to a video signal having a synchronization signal, it becomes possible to restore the video information and the synchronization signal without time lag.

Next, other embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows a block diagram of a video signal processing device in another embodiment of the present invention.

Components that are the same as those in FIG. 2 are given the same numbers. In FIG. 4, 8 is a sync signal separation circuit that separates the horizontal sync signal from the video signal, 9 is a pulse generation circuit for gating the horizontal sync signal portion, 1o is a pulse path generated by the pulse generation circuit, and 14 is a pulse generation circuit for gating the horizontal sync signal portion. This is a second switch circuit.

The operation of the video signal processing apparatus of this embodiment configured as described above will be described below.

First, the video signal shown in FIG. 3A is input to the first switch circuit 12 and the first inversion circuit 11 via the input terminal 6. The first inverting circuit 11 inverts the input video signal around the gold pedestal level Ep and outputs the inverted video signal shown in FIG. 3B.

On the other hand, the video signal input to the input terminal 6 is also input to the synchronization signal separation circuit 8. The synchronization signal separation circuit 8 separates and outputs the horizontal synchronization signal. Since the output horizontal synchronization signal is a repeating signal, it is a monostable multivibrator circuit (
(not shown) etc. in the pulse generating circuit 9 shown in FIG. 3C.
A pulse including a synchronization signal period is generated and output as shown in FIG. When the output of the pulse generation circuit 9 is L#, the input terminal 6
The first switch circuit 12 is controlled so as to select the video signal inputted to the input signal, and when the output of the pulse generation circuit 9 is "H", the first switch circuit 12 is controlled so as to select the output of the first inverting circuit 11. The circuit 12 is controlled to convert the video signal input to the analog/digital conversion circuit 2 into a video signal to which a positive synchronization signal is added as shown in the third diagram.

The analog/digital conversion circuit 2 converts the video signal from analog to digital, and digitally processes the converted video signal in a signal processing circuit 3 configured with a digital memory (not shown). The digitally processed video signal is converted into an analog video signal by a digital/analog conversion circuit 6.

The output of the digital/analog conversion circuit 6 is a video signal to which a positive synchronization signal is added as shown in FIG. 3E.

The output of the digital/analog conversion circuit 6 is input to the second switch circuit 14 and the second inversion circuit 13. Second
The inverting circuit 13 inverts the output of the digital/analog conversion circuit 6 around the pedestal level Ep, and inputs the video signal shown in FIG. 3F to the second switch circuit.

The delay circuit 1o is connected to the pulse generation circuit 9 by the time τ during which the video signal is delayed by the analog/digital conversion circuit 10, the signal processing circuit 3, and the digital/analog conversion circuit 4.
delay the output. The output of the delay circuit 1o shown in FIG. 3G is input to the second switch circuit 14.

When the output of the delay circuit 10 is L2, the second switch circuit 14 is controlled to select the output of the digital/analog conversion circuit 6, and when the output of the delay circuit 10 is H#, the second switch circuit 14 is controlled to select the output of the digital/analog conversion circuit 6.
The second switch circuit is controlled to select the output of the inverting circuit 13, and the video signal shown in FIG. 3H is output to the output terminal 7.

Effects of the Invention As is clear from the above description, the present invention provides a synchronization signal addition circuit that adds a positive synchronization signal, an analog/digital conversion circuit that converts a video signal to which a positive synchronization signal is added, and a digital It consists of a signal processing circuit that digitally processes the converted video signal, a digital/analog conversion circuit that converts the digitally processed video signal to analog, and a synchronization signal restoration circuit that restores it to a negative polarity synchronization signal. Therefore, since a video signal having a negative polarity synchronization signal is restored with a positive polarity synchronization signal, it is possible to reproduce the video signal without causing a time lag between the video information and the synchronization signal.

Furthermore, since the video signal input to the analog/digital conversion circuit is conventionally a video signal with a negative polarity synchronization signal shown in FIG. 6A, when converted using the analog/digital conversion characteristics shown in FIG. 5B, the synchronization signal However, according to the present invention, the video signal input to the analog/digital conversion circuit is a video signal having a positive polarity synchronization signal as shown in FIG. 5C. When converting using the analog/digital conversion characteristics shown in Figure 5B, only the video information from the pedestal level E to the maximum voltage EMAX of the video signal is converted from analog to digital, so it is possible to improve the resolution of the video information. It becomes possible. For example, when analog/digital conversion is performed using an 8-bit analog/digital conversion circuit, the number of steps to decompose video information increases from 179 steps to 266 steps, which is a significant improvement. An excellent effect of improving the signal-to-noise ratio of the signal can be obtained.

In a system that removes the synchronization signal to restore the synchronization signal and transmits the video information and the synchronization signal separately, in order to maintain the time relationship between the video information and the synchronization signal, a system with high time accuracy is required. Although a synchronization signal must be transmitted over a transmission path, the video signal processing device according to the present invention transmits the video signal with synchronization signal information added to it and restores the synchronization signal, so that the time between the synchronization signal and the video signal is The advantageous effect is that the relationships are transmitted very accurately.

Furthermore, since the pulses necessary to restore the synchronization signal are created to include the synchronization signal, the delay time of the delay circuit that delays the pulses necessary to restore the synchronization signal is
The time may be approximately equal to the time during which the video signal is delayed by the analog/digital conversion circuit, signal processing circuit, and digital/analog conversion circuit.

For example, if the pulse width of the pulse necessary to restore the synchronization signal is Tp, and the synchronization signal period is T8, then 13'.
- ±(Tp's) The delay time of the delay circuit can be tolerated by □ time, which has the great effect of restoring an accurate synchronization signal without requiring a highly time-accurate delay circuit.

Furthermore, in a system that transmits video information and synchronization signals separately, it is extremely difficult to restore the amplitude information of the synchronization signal, but the video signal processing circuit according to the present invention can convert the amplitude information of the synchronization signal into video information. Since the synchronization signal is transmitted together with the synchronization signal, an excellent effect can be obtained in that extremely accurate amplitude information of the synchronization signal can also be easily transmitted.

[Brief explanation of the drawing]

FIG. 1A is a waveform diagram of a video signal input to input terminal 1,
FIG. 1B is a waveform diagram of the video signal input to the A/D conversion circuit, FIG. 1C is a waveform diagram of the video signal output to the output terminal 7, and FIG. A block diagram of the signal processing device, FIG. 3 is a signal waveform diagram of each part thereof, FIG. 4 is a block diagram of another embodiment of the present invention, and FIG. 6A is a waveform diagram of a video signal having a synchronization signal of negative polarity. , Figure 5B is A/D
. FIG. 5C, which is a characteristic diagram of the 14ba/conversion circuit, is a waveform diagram of a video signal having a positive polarity synchronization signal. 2...A/D conversion circuit, 3...Signal processing circuit, 4...D/A conversion circuit, 6...Input terminal, 7-...Output terminal , 8... Synchronization signal separation circuit, 9... Pulse generation circuit, 10... Delay circuit, 11... First inversion circuit, 12...
- First switch circuit, 13... Second inversion circuit, 14... Second switch circuit.

Claims (4)

[Claims] (1) a synchronization signal addition circuit that adds a positive synchronization signal to a video signal; an analog/digital conversion circuit that converts the video signal to which the positive synchronization signal has been added into a digital signal;
A signal processing circuit that digitally processes a video signal that has been converted into a digital signal, a digital/analog conversion circuit that converts the digitally processed video signal into an analog signal, and a synchronization signal restoration circuit that restores it to a negative polarity synchronization signal. A video signal processing device that processes digital signals without damaging the time relationship between video information and a synchronization signal. (2) The synchronization signal addition circuit creates a gate pulse containing a synchronization signal from the input video signal, and uses the gate pulse to convert a video signal with a negative polarity synchronization signal into a video signal with a positive polarity synchronization signal. 2. The video signal processing device according to claim 1, wherein a positive polarity synchronization signal is added by converting the signal. (3) The synchronization signal restoration circuit applies a delay approximately equal to the delay time delayed by the analog/digital conversion circuit, the signal processing circuit, and the digital/analog conversion circuit to the gate pulse that controls the synchronization signal addition circuit, and Claim 1, characterized in that the synchronization signal is restored by converting a video signal having a positive polarity synchronization signal after digital/analog conversion into a video signal having a negative polarity synchronization signal using the gate pulse generated by the gate pulse. The video signal processing device according to item 1. (4) Conversion from a video signal having a negative polarity synchronization signal to a video signal having a positive polarity synchronization signal is performed by converting a video signal having a negative polarity synchronization signal and a signal obtained by inverting the video signal to the gate The selection is controlled by pulses, and the conversion from a video signal with a positive polarity synchronization signal to a video signal with a negative polarity synchronization signal is achieved by inverting the video signal with a positive polarity synchronization signal and the video signal. 2. The video signal processing apparatus according to claim 1, wherein said signal is selected by controlling said delayed gate pulse.