JPH0659091B2 - Sync signal generator - Google Patents

Description

The present invention relates to a synchronizing signal generating circuit for video equipment.

(Prior Art) In a video device such as a TV camera or a TV monitor that handles two-dimensional information as a one-dimensional time-series signal, the position of the object is specified in addition to the video information representing the brightness and the like of the object by the magnitude of the amplitude. Synchronization signal is required. Therefore, in the television standard system such as NTSC and PAL, FIG.
As shown in, the negative polarity pulse (binary waveform) is inserted during the blanking period of the video signal to make it a synchronizing signal. However, this method has a drawback in that a delay error in the transmission system and a deviation of the sync discrimination level between the video equipment appear as a deviation of the reproduction sync signal phase. For this reason, a positive / negative bipolar sync signal using a ternary waveform shown in FIG. 4 (b) has been proposed as a sync signal for a high-definition television which requires a smaller phase deviation of the sync signal. That is, in this positive / negative bipolar sync signal, since the sync discrimination level is a pedestal level that can be accurately reproduced by many video devices, it is possible to reduce the above-mentioned delay error in the transmission system and the deviation of the sync discrimination level. .

FIG. 5 and FIG. 6 show an example of a conventional circuit for generating the positive / negative bipolar sync signal described above and its operation timing. In FIG. 5, 101 and 102 are buffer amplifiers, 103 is a capacitor for blocking a direct current component, 104 is a diode for preventing a pulse applied to the buffer amplifier 102 from flowing back to the power source of the buffer amplifier 101, and 105 is A mix amplifier for synthesizing a video signal and a synchronization signal.
This circuit operates as follows. First buffer amplifier 10
At time 1, the first synchronizing signal generation pulse 106, which is at a low level, is applied during the period from the time ▲ t ^′ ₁ ▼ to ▲ t ^′ ₂ ▼. Next, the second synchronization signal generation pulse 107, which is at a high level during the period from the time ▲ t ^′ ₂ ▼ to ▲ t ^′ ₃ ▼, is applied to the buffer amplifier 102, and the output signal of the buffer amplifier 101 is output via the capacitor 103. It is superimposed. Therefore, the output terminal 108 of the buffer amplifier 101 is at a low level during the period from the time ▲ t ^′ ₁ ▼ to ▲ t ^′ ₂ ▼, is at the high level during the time ▲ t ^′ ₂ ▼ to ▲ t ^′ ₃ ▼, and otherwise A ternary positive / negative bipolar sync signal 109 having an intermediate level during the period is obtained. This positive / negative bipolar sync signal 1
09 is combined with the video signal 111 input from the terminal 110 by the mix amplifier 105 and output as a composite video signal 112.

(Invention Problems to be Solved) such conventional circuit, the time ▲ t _^'2 ▼ at the rising timing and the second first synchronous signal generating pulses 106
If the rising timings of the synchronizing signal generation pulse 107 are completely matched, the operation is performed without any problem. However, the timings of the two pulses are often deviated due to temperature fluctuations, etc., and in the worst case, as shown in the enlarged waveform 113, the rising from the low level to the high level, which is the most important for the positive / negative bipolar sync signal. There will be a step in the middle. In such a state, even if the sync discrimination level is fixed to the pedestal level, the phase of the reproduced sync signal fluctuates by the width of the step, which causes jitter in the reproduced image, which is not preferable.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a synchronization signal generating circuit which eliminates the above-mentioned conventional drawbacks, has a small deviation of the reproduction synchronization signal phase, and has a simple circuit configuration.

(Means for Solving the Problems) According to the present invention, there is provided a sync signal generating circuit for a video device, which uses a ternary waveform as a sync signal, and which receives the first and second sync signal generating pulses and outputs both of them. A pulse synthesizing unit for generating the ternary waveform by pulse synthesizing is provided, and the pulse synthesizing unit sets the ternary waveform to a low level when both the first and second synchronization signal generating pulses are at a low level. ,
When the first sync signal generation pulse is at the high level and the second sync signal generation pulse is at the low level, the ternary waveform is set to the high level, and the first and second sync signal generation pulses are the above-mentioned. A synchronization signal generating circuit is obtained which sets the ternary waveform to an intermediate level when there is no level relationship.

(Operation) In the above-described synchronization signal generation circuit of the present invention, the rising timing of the ternary waveform from the low level to the high level is the first
Since it is uniquely determined at the timing of the rising edge of the sync signal generation pulse, there is no step difference in the middle and the reproduced sync signal phase does not fluctuate as in the conventional case. Moreover, since the circuit configuration is easy, the number of circuit designing steps and adjusting steps can be reduced.

(Example) Hereinafter, the Example of this invention is described with reference to drawings.

1 and 2 are a block diagram and an operation timing diagram of the first embodiment of the present invention, respectively. In this embodiment, a non-inverting buffer 1 having a 3-state output is used as a pulse synthesizing means for a ternary waveform. Also, 2 and 3 are output terminals 4 when the non-inverting buffer 1 is in a high impedance state.
A resistor 5 for determining the electric potential of 5 is a mix amplifier for synthesizing the video signal and the synchronizing signal. The operation of this circuit is as follows.
At ▼, the synchronization signal generation pulse SYNC2 having a low level is applied during the period from time t ₁ to t ₃ . Therefore, the non-inverting buffer 1 is active only during the period from time t ₁ to t ₃ , and is in the high impedance state during the other period.
Next, at the input terminal A of the non-inverting buffer 1, from time t ₂ to t ₃
Sync signal generation pulse SYNC2 which becomes high level during the period
Is applied. By these operations, the output terminal 4 has a low level during the time t ₁ to t _2, a high level during the time t ₂ to t ₃ , and an intermediate level determined by the division ratio of the resistors 2 and 3 in the other time periods. A positive / negative bipolar sync signal 6 having the following three-valued waveform is obtained. The positive / negative bipolar sync signal 6 is combined with the video signal 8 input from the terminal 7 by the mix amplifier 5 and output as a composite video signal 9. According to the operation of this embodiment, the rising timing of the ternary waveform from the low level to the high level, which is the most important by the positive / negative bipolar sync signal 6, is uniquely the rising timing of the sync signal generation pulse SYNC1. It is determined. Therefore,
By increasing only the phase accuracy of the rising timing of the sync signal generation pulse SYNC1, it is possible to generate a very accurate positive / negative bipolar sync signal. Or it may be anywhere in the timing of the falling edge of the synchronization signal generation pulse SYNC2 from time t ₃ to t _4.

A second embodiment according to the present invention is shown in FIG. The operation timing of this embodiment is similar to that of FIG. In this embodiment, the analog multiplexer 10 is used as the pulse synthesizing means for the ternary waveform. Analog multiplexer
Various types of 10 are available as standard logic ICs from various manufacturers and can be obtained at low cost.
In the figure, 11 to 14 are analog switches, which switch the input signals from the input terminals X _{0 to} X ₃ by the data from the decoder 15 and transmit them to the output terminal X. 11-15 are integrated in the analog multiplexer 10. 16 and 17
Is a resistor for determining the intermediate level of the ternary waveform according to the division ratio, and 18 is a mix amplifier for synthesizing the video signal and the synchronizing signal. This circuit operates as follows. First, the sync signal generation pulse SYNC1 shown in FIG. 2 is applied to the control input terminal A of the analog multiplexer 10.
Is applied. Further, a sync signal generation pulse SYNC2 is applied to the control input terminal B. Therefore, the third
According to the truth table of the analog multiplexer 10 shown in FIG. 9B, the input terminal X ₀ is selected from the output terminal X during the period from time t ₁ to t ₂ and becomes low level, and from time t ₂ to t _3. , The input terminal X ₂ is selected to have a high level, and in other periods, either the input terminal X ₁ or X ₃ is selected to have an intermediate level, which is an intermediate level positive / negative bipolar sync signal 6
Is obtained. The positive / negative bipolar sync signal 6 is combined with the video signal 8 input from the terminal 19 by the mix amplifier 18,
It is output as a composite video signal 9. According to the operation of the present embodiment, as in the first embodiment, the rising timing of the ternary waveform from the low level to the high level is uniquely determined by the rising timing of the synchronization signal generation pulse SYNC1. It is possible to generate a positive / negative bipolar sync signal with high accuracy. Further, in the case of the first embodiment, since the fall of the ternary waveform from the high level to the intermediate level is performed by discharging through the resistor 3, for example, the resistor 3 is
For 1.5kΩ, a fall time of about 50nS is required. On the other hand, the falling edge in this embodiment is the switch 11
Very fast because it depends only on the switching speed of ~ 14. For example, high-speed CMOS IC μP-D74HC
The fall time when using the 4052 is accelerated to about 10 nS.

(Effects of the Invention) As described above, according to the synchronization signal generation circuit of the present invention, it is possible to obtain a positive / negative bipolar synchronization signal with little fluctuation in the synchronization identification level and excellent phase accuracy.

In the explanation of the first embodiment according to the present invention,
Although a non-inverting buffer having a 3-state output is used as the pulse synthesizing means for the ternary waveform, the same effect can be obtained by using an inverting buffer, a latch, a flip-flop or the like if the IC has a 3-state output.

[Brief description of drawings]

1 and 2 are a block diagram of a first embodiment of a synchronizing signal generating circuit according to the present invention and an operation timing chart thereof, respectively, and FIG. 3 (a) is a second embodiment of a synchronizing signal generating circuit according to the present invention. FIG. 3 is a block diagram showing an example, FIG. 3 (b) is a diagram showing a truth value of the analog multiplexer in the second embodiment, FIG. 4 is a diagram for explaining a positive / negative bipolar sync signal, FIG. FIG. 6 is a block diagram of a conventional synchronizing signal generating circuit and its operation timing chart. In the figure, 1 is a 3-state output non-inverting buffer,
5, 18 and 105 are mix amplifiers, 10 is an analog multiplexer, and 101 and 102 are buffer amplifiers.

Claims (1)

[Claims] 1. A sync signal generation circuit for a video device, which uses a tri-level waveform as a sync signal, inputs pulse signals for generating first and second sync signals, and synthesizes these pulses to generate the tri-level waveform. Means is provided, and the pulse synthesizing means sets the ternary waveform to a low level when both the first and second synchronization signal generation pulses are at a low level, and the first synchronization signal generation pulse is at a high level. Further, the ternary waveform is set to a high level when the second synchronization signal generation pulse is at a low level, and the ternary waveform is set to an intermediate level when the first and second synchronization signal generation pulses have a relationship other than the level relationship described above. A synchronizing signal generating circuit characterized by setting to a level.