JPH04249496A - Video signal detector - Google Patents

Abstract

PURPOSE:To detect accurately the presence of an input of a video signal with configuration able to be integrated with respect to the detector detecting the presence of the video signal by means of a digital circuit. CONSTITUTION:A sampled signal generating circuit 11 extracts a sampled signal synchronously with a horizontal synchronizing signal or a vertical synchronizing signal of an input video signal. A sampling circuit 13 uses a sampling pulse from a pulse generating circuit 12 to sample the sampled signal thereby generating a video detection signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal detection device, and more particularly to a device for detecting the presence or absence of a video signal using a digital circuit.

In a system that superimposes a composite video signal and an image signal from a personal computer, if the composite video signal is no longer input for some reason, part of the superimposed image will be lost. It is desirable to automatically switch to only the image signal from the personal computer. In addition, even when a television broadcast ends, the power switch of the television receiver is automatically turned off because it is a complete waste of power to continue receiving images from before the television broadcast ends. It would be convenient if it could be done.

Furthermore, in magnetic recording and playback devices and video disk playback devices, during the period of playing back unrecorded areas of a recorded medium (magnetic tape or video disk), images of video signals from other video sources are displayed. It would be convenient if it could be switched automatically.

[0004] In view of the above requirements, it is necessary to accurately detect the presence or absence of a video signal using a device having a small configuration.

[0005]

2. Description of the Related Art FIG. 6 shows a block diagram of an example of a conventional video signal detection device. In the figure, an analog composite video signal from a video source is separated into synchronization signals by a synchronization separation circuit 1, and then supplied to an integration circuit 2, where it is converted into a DC voltage. When a composite video signal is input, the output DC voltage of the integrating circuit 2 is a predetermined value or more, whereas when a composite video signal is not input, the DC voltage is less than the predetermined value.

The level detector 3 compares the level of the DC voltage from the integrating circuit 2 with a reference voltage corresponding to the above-mentioned predetermined value, and when the input DC voltage is higher than the reference voltage, it indicates that a composite video signal is input, and the reference voltage is When it is less than the value, a video detection signal indicating that no composite video signal is input is output.

[0007]

[Problems to be Solved by the Invention] However, in the conventional video signal detection device described above, the integrating circuit 2 is an analog circuit consisting of a capacitor and a resistor, and the number of stages is not limited to one in order to obtain the necessary characteristics. It often has a multi-stage configuration. Therefore, the circuit scale of the integrating circuit 2 is large, and the presence of a capacitor makes it difficult to integrate it into an integrated circuit (IC).

[0008] Furthermore, the setting of outputting a video detection signal indicating that no composite video signal has been input after a certain time has elapsed after the composite video signal disappears is determined by the time constant of the capacitor and resistor that constitute the integrating circuit 2. However, because the capacitors and resistors only have constants specified by the Electronics Industry Association of Japan (EIAJ) standards, it may not be possible to obtain the desired setting time, and there may also be problems with the stability of time setting due to variations in the constants of the parts. There is.

[0009] The present invention has been made in view of the above points.
It is an object of the present invention to provide a video signal detection device that has an IC-enabled configuration and can accurately detect the presence or absence of input of a video signal.

0010

[Means for Solving the Problems] FIG. 1 shows a diagram of the basic configuration of the present invention. In the figure, 11 is a sampled signal generation circuit that generates a sampled signal synchronized with an input signal;
2 is a pulse generation circuit that generates a sampling pulse with a higher frequency than the sampled signal synchronized with the input signal;
Reference numeral 13 denotes a sampling circuit that outputs a video detection signal based on data obtained by sampling the sampled signal with a sampling pulse.

[0011]

[Operation] When a signal is input to the sampled signal generation circuit 11 via the terminal 10, a sampled signal synchronized with the signal is extracted, whereas when no signal is input to the sampled signal generation circuit 11. The sampled signal is not extracted.

Therefore, the sampling circuit 13 can output a video detection signal of a predetermined logical value to the terminal 14 only when the sampled signal is input (when there is an input video signal). Here, since the sampled signal generation circuit 11, the pulse generation circuit 12, and the sampling circuit 13 are all configured to output pulse signals, they can be configured as digital circuits. Further, the time of the video detection signal can be set based on the sampling pulse of a constant period from the pulse generation circuit 12.

[0013]

Embodiment FIG. 2 shows a block diagram of a first embodiment of the present invention. In the figure, the same components as those in FIG. In FIG. 2, an interlaced composite video signal input to a terminal 10 is supplied to a field discrimination signal generation circuit 21, which generates field discrimination signals having different logic values for odd and even fields. This field discrimination signal generation circuit 21 can be configured using a known IC (for example, LM1881), and is phase-synchronized with the vertical synchronization signal shown in FIG. 3(A) in the input composite video signal, and A field discrimination signal shown in FIG. 3B having logical values assigned to each field of the signal is generated.

On the other hand, the pulse generating circuit 22 is a circuit that generates pulses with a period equal to the vertical scanning period of the input composite video signal, and constitutes the pulse generating circuit 12.
Regardless of whether or not a composite video signal is input to 0, pulses as shown in FIG. 3(C) are always generated.

D-type flip-flops 231 to 233
are latch circuits connected in three stages in cascade, and the pulses of the vertical scanning period from the pulse generating circuit 22 are commonly input to the clock (CLK) terminals of the latch circuits. On the other hand, the output signal of the field discrimination signal generation circuit 21 is input to the data input terminal D of the D-type flip-flop 231 in the first stage, and the D-type flip-flops 232 and 233 in the second and third stages are inputted.
The output signals of the Q output terminals of the D-type flip-flops 231 and 232 in the previous stage are input to each data input terminal D of the data input terminal D.

Furthermore, a 3-input NOR circuit 24 and a 3-input A
The ND circuits 25 are D-type flip-flops 231 to 2, respectively.
33 output signals are input, and the signals obtained by performing the NOR or AND operation of these signals are output to the OR circuit 26, respectively. These D type flip-flops 231 to 233,
The NOR circuit 24, the AND circuit 25, and the OR circuit 26 constitute the sampling circuit 13 described above.

When a composite video signal is input to the terminal 10, the data input terminal of the D-type flip-flop 231 receives a field as shown in FIG. 3(B) which is inverted every field (every vertical scanning period). Since the discrimination signal is input, the Q output terminal of the D-type flip-flop 231 outputs a pulse that is sampled with a clock pulse of one vertical scanning period and is inverted every vertical scanning period.

Further, the D type flip-flop 232 is D
A pulse that is inverted every vertical scanning period from the Q output terminal of the D-type flip-flop 231 is supplied to the data input terminal, but at the time the clock pulse is input, the propagation delay time inherent in the circuit of the D-type flip-flop 231 Therefore, the data input pulse has the logical value just before it is inverted. Therefore, a pulse whose logic value is inverted from the output pulse of the D-type flip-flop 231 is taken out from the Q output terminal of the D-type flip-flop 232 . Similarly, from the Q output terminal of the D-type flip-flop 233, a pulse of one vertical scanning period whose logical value is inverted from the output pulse of the D-type flip-flop 232 is taken out.

Therefore, when a composite video signal is input to the terminal 10, the D-type flip-flops 231 and 233 and the D-type flip-flop 232 generate pulses (sampling data) of one vertical scanning period with mutually different logical values. is taken out. Therefore, in this case, N
Since the respective output signals of the OR circuit 24 and the AND circuit 25 are both low level, a low level signal is taken out from the OR circuit 26 and outputted to the terminal 14 as a video detection signal indicating the presence of video input.

On the other hand, when no composite video signal is input to the terminal 10, the field discrimination signal generating circuit 11 holds the output logic value immediately before the input composite video signal was interrupted. Therefore, if the input of the composite video signal is interrupted after time t1 in FIG. 3, the output signal of the field discrimination signal generation circuit 21 is held at the low level immediately before t1.

[0021] As a result, the time t when a clock pulse is output from the pulse generation circuit 22 for the third time after time t1
2, three D-type flip-flops 231 to 233
Since the respective output signals of the NOR circuit 24 all have the same logical value (low level here), the output signal of the NOR circuit 24 becomes high level. Therefore, the video detection signal outputted to the terminal 14 through the OR circuit 26 is transmitted at time t as shown in FIG. 3(D).
At 2, it changes to high level indicating that no composite video signal is input.

Note that after the point in time when the composite video signal is no longer input to the terminal 10, the field discrimination signal generation circuit 21
When the output signal of D-type flip-flops 231 to 233 is held at high level, all the output signals of D-type flip-flops 231 to 233 become high level when the third clock pulse is generated. The signal is taken out, so that a high-level video detection signal can be output to the terminal 14 in this case as well.

Next, a second embodiment of the present invention will be explained with reference to FIGS. 4 and 5. FIG. 4 shows a configuration diagram of a second embodiment of the present invention. In the figure, the same components as those in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 4, a non-interlaced video signal or synchronization signal from a personal computer or the like is input to a vertical synchronization separation circuit 31 via a terminal 10. Since a non-interlaced video signal or synchronization signal does not have an odd field or an even field, a field discrimination signal cannot be generated, but a horizontal synchronization signal and a vertical synchronization signal do exist.

Therefore, when a non-interlaced video signal or a synchronization signal is input from the vertical synchronization separation circuit 31, a vertical synchronization signal is taken out as shown in FIG. 5(A). This vertical synchronizing signal is input to the flip-flop 32, frequency-divided by 1/2, and inverted every vertical scanning period (FIG. 5).
After being converted into a toggle output as shown in B), it is applied to the data input terminal of the D-type flip-flop 231.

On the other hand, the pulse generating circuit 33 is a circuit that generates pulses with a period equal to the vertical scanning period of a non-interlaced video signal or a synchronizing signal, and constitutes the pulse generating circuit 12. Or, regardless of whether a synchronization signal is input, always as shown in Figure 5 (C)
The pulse shown in is generated.

Accordingly, in the case of this embodiment as well, when the input of the video signal or synchronization signal is interrupted after time t10 in FIG.
The video detection signal outputted from the R circuit 26 to the terminal 14 is at high level, and in other cases, the video detection signal is at low level.

[0027] In this manner, each of the above embodiments can be configured with digital circuits, and is therefore suitable for IC implementation. Further, the pulse generation circuit 22,
Since the sampling operation is performed using a clock pulse of a constant period from 33, it is possible to set the time for image detection more stably and accurately than the time constant of CR.

It should be noted that the present invention is not limited to the above embodiments, and for example, the D-type flip-flops 231 to
233 may be increased or decreased, thereby making it possible to arbitrarily set the time for outputting no video signal input. Further, a signal other than the vertical synchronization signal, for example, a sampled signal synchronized with the horizontal synchronization signal may be generated.

[0029]

As described above, according to the present invention, it is possible to configure a digital circuit, so it can be easily integrated into an IC, and since sampling is performed using a clock pulse of a constant period, there is no need to input a video signal or a synchronization signal. The present invention has features such as being able to more accurately and freely set the output time of the video detection signal indicating .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of FIG. 2;

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of FIG. 4;

FIG. 6 is a block diagram of an example of a conventional device.

[Explanation of symbols]

11 Sampled signal generation circuit 12 Pulse generation circuit 13 Sampling circuit 14 Field discrimination signal generation circuit 231 to 233 D-type flip-flop 32
flip flop

Claims (3)

[Claims] 1. A sampled signal generation circuit (11) that generates a sampled signal synchronized with an input video signal or a synchronization signal, and a pulse generation circuit (11) that generates a sampling pulse having a higher frequency than the sampled signal.
2), and a sampling circuit (13) that samples the sampled signal using the sampling pulse and generates and outputs a video detection signal indicating the presence or absence of the input video signal based on the sampling data. Video signal detection device. Claim 2: The sampled signal generating circuit (1
1) is a circuit (21) that generates a pulse that is phase-synchronized with the input video signal or synchronization signal in an interlaced format, and the sampling circuit (13) sequentially samples the phase synchronization pulse with the sampling pulse; A plurality of latch circuits (231
~233) and the latch circuit (231~233)
), which indicates that the input video signal or synchronization signal is not input only when all the output sampling data match, and otherwise generates and outputs a signal indicating the presence of input as the video detection signal (24 to 26 2. The video signal detection device according to claim 1, wherein the video signal detection device comprises: Claim 3: The sampled signal generating circuit (1
1) is a circuit (31
, 32), and the sampling circuit (13) includes a plurality of cascade-connected latch circuits (231 to 233) that sequentially sample the phase synchronization pulse with the sampling pulse, and the latch circuit (231).
-233) A logic circuit that indicates the absence of input of the input video signal or synchronization signal only when all the output sampling data of (233) coincide with each other, and otherwise generates and outputs a signal indicating the presence of input as the video detection signal ( 24-26
2. The video signal detection device according to claim 1, wherein the video signal detection device comprises: