JPH02185167A - Noninterlace scanning and discrimination circuit - Google Patents

Abstract

PURPOSE:To obtain an accurate noninterlace scanning discrimination signal by providing 2 majority decision circuits discriminating which is larger logical H or L in number at all output terminals of an odd number stages of each D flip-flop and at all output terminals of an even number stages of each D flip-flop, and outputting logic level large in number. CONSTITUTION:A shift register consists of n (n=2+4m and m is an integer number of '0' or over) sets of D FFs, and every time a vertical synchronizing signal is inputted, a field discrimination signal of the existing field is latched from a data input terminal D of the D-FF1. Then an output of a noninverting output terminal Q of the D-FF 1 being a field discrimination signal of one preceding field is latched from a data input terminal D of a D-FF 2. Then majority decision circuits 7, 8 take majority decision of which of logical H, L is large in number in all signals of odd number and even number stages at the output terminal Q' of the n-th stage of D-FF 6. Thus, the majority logic level is outputted from the majority decision circuits 7, 8 and the two outputted signals are exclusive ORed by an EX-OR circuit 9 and the result is outputted from an output terminal 13.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to video signals such as VTRs that are interlaced scanned or
The present invention relates to a non-interlaced scanning identification circuit that identifies non-interlaced scanning.

[Conventional technology]

Using two TV signals or a video signal from a VTR, you can create a picture-in-picture (PIP), etc.
When reproducing Senryo, the conventional technique is to determine the first field and the second field of the sub-screen video signal and store them in separate memory areas. This stored child screen data in memory is synchronized with the video signal of the main screen.
The data of the first field of the child screen is output to the first field of the main screen, and the data of the second field of the child screen is output to the second field of the parent screen.

Also, when inputting a still image signal from a VTR as a small screen signal, the still image signal becomes non-interlaced scanning due to the VTR's function, so the field identification signal is fixed to the first field or the second field. This situation is occurring.

As a conventional circuit for generating a non-interlaced scanning identification signal, there is a circuit shown in FIG. This is n D-F
/F 1 to 6 (n is a natural number of 2 or more) constitute a shift register, and each time a vertical synchronization signal is input, the field identification signal of the current field is latched from the data input terminal 2 of DF/Fl, The output of the non-inverting output terminal Q of D-F/Fl, which is the field identification signal of one field before, is converted to D-F/F1.
Latch from the data input end of F2. In addition, the output of the non-inverted output terminal Q of DF/F2, which is the field identification signal of two fields before, is latched from the data input terminal of D-F/F3. Shifting data.

Next, field identification signals for n fields outputted from the non-inverting output terminals Q of n D-F/Fs are outputted to an AND circuit 2.
1, and the field identification results for n fields outputted from the inverted output circuits of n D-F/Fs are ANDed by an AND circuit 22, respectively. These AND circuits 21.
If either result of 22 becomes logical H, it means that all the data in n DF/Fs match, and the field identification result is always fixed while scanning n fields. I can see that. The fact that the field identification results are continuous and fixed in this way means that the image signal is subjected to non-interlaced scanning like a still image signal of a VTR.

Therefore, when the output of the OR circuit 23 obtained by calculating the logical sum of the AND circuits 21 and 22 is logic H, it is always identified as non-interlaced scanning.

[Problem to be solved by the invention]

The conventional non-interlaced scanning identification signal mentioned above is n
Since the logical product of field identification signals for fields is taken, out of the field identification signals for n fields,
If even one erroneous field identification signal is input due to the influence of noise, the output of the AND circuit becomes erroneous and always outputs an erroneous signal during the period when n-field scanning is completed. There is.

The purpose of the present invention is to solve such problems and to
The field identification signal for each field is extracted from the image signal D-
By latching the F/F and taking a majority vote on the logic level of the output signal at all output terminals of odd-numbered stages and all output terminals of even-numbered stages of the D-F/F, some errors in the field identification signal can be avoided. To provide a non-interlaced scanning identification circuit which can obtain an accurate non-interlaced scanning identification signal even when the field is fixed to odd or odd during non-interlaced scanning. It is in.

[Means to solve the problem]

The configuration of the non-interlaced scanning identification circuit of the present invention is n
A shift register composed of D-type flip-flops has a logic H1 logic at one output terminal of each odd-numbered stage and one output terminal of each even-numbered stage of each flip-flop. two majority circuits that identify whether the number is larger and output the logic level of the larger number;
It is characterized by comprising an exclusive OR circuit which calculates the exclusive OR of these majority circuits and generates a non-interlaced identification signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the non-interlaced discrimination circuit of the present invention.
(where m is an integer greater than or equal to 0) DF/F constitutes a shift register, and each time a vertical synchronization signal is input, the field identification signal of the current field is input from the data input end of DF/Fl. D-
Latch from the data input end of F/F2. In addition, the output of the non-inverted output terminal Q of DF/F2, which is the field identification signal of two fields before, is latched from the data input terminal of DF/F3, and so on. will shift.

Then, at the output terminals Q and Q of the n-stage D-F/F 6, a majority decision circuit 7 determines which signal has more by using logic H2 logic for all the signals in the odd-numbered stages and all the signals in the even-numbered stages. 8, the logic level with the higher value is output from the majority circuit 7.8, and the exclusive OR (EX-OR) of the two signals output from the majority circuits 7 and 8 of the odd-numbered stage and the even-numbered stage is performed. is obtained by the EX-OR circuit 9 and output from the output terminal 13.

For example, when performing interlaced scanning, D-
Since the data latched in the F/F is alternated between logic H1 and logic L (logic H: odd field, logic L: even field), the majority decision of the Q signal in the odd stage and the G signal in the even stage The logic level output from circuit 7.8 is
The signal will always match. Therefore, the output of the BX-OR circuit 9 is always logical.

Next, in the case of non-interlaced scanning, the data latched in the D-F/F is all fixed to logic H or logic high, so the Q signal of odd-numbered stages and the signalable signal of even-numbered stages If one of the logic levels output from the majority circuit 7.8 is logic H, the other is always logic low. Therefore, the non-interlace identification signal output from the EX-OR circuit 9 becomes logic H, making it possible to distinguish between interlace scanning and non-interlace scanning.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The structure of the shift register with n DF/Fl to 6 is the same as in the first embodiment, but an odd number of stages is used. When the majority circuits 7 and 8 take a majority decision using all the signals of the first stage and all the signals of the even-numbered stages, the majority decision is made only with the signal of the non-inverting output terminal Q of the D-F/F. The EX-OR circuit 15 calculates the exclusive OR (EX-NOR) of the signals output from the EX-OR circuit 15.

Also, by calculating the logical sum of this non-interlaced scanning identification signal and the output of one of the majority circuits 7 and 8 using an AND circuit 16, a field identification signal indicating which field is fixed (odd or even) during non-interlaced scanning is determined. The advantage is that the signal can be easily detected.

〔Effect of the invention〕

As explained above, the present invention obtains field identification signals for n consecutive fields from an image signal and latches them in the D-F/F, and at the same time outputs the output terminals Q or all of the odd-numbered stages of the D-F/F. By taking a majority vote on the logic level of the output signal at all the output terminals Q or Q of even-numbered stages, and calculating the exclusive OR of these, even if there is some error in the field identification signal, it is accurately determined that the signal is non-interlaced. This has the advantage that a scanning identification signal can be obtained, and it is also possible to easily determine whether the field is fixed to odd or even during non-interlaced scanning.

AND circuit, 23/OR circuit.

Claims (1)

[Claims] A shift register composed of n stages of D-type flip-flops, and one output terminal of each of the odd-numbered stages and one output terminal of all the even-numbered stages of each D-type flip-flop are set to logic H and logic L, respectively. The present invention is characterized by comprising two majority circuits that identify which one has the highest logic level and output the logic level of the higher one, and an exclusive OR circuit that takes the exclusive OR of these majority circuits and generates a non-interlaced identification signal. Non-interlaced scanning identification circuit.