JPS5925416A - Waiting circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of a waiting circuit when a large number of bits exist, by using an n-stage shift register to compare successively the present signal with the n-bit earlier signal and therefore detecting a signal which changes from 0 to 1 and then holding this signal by a holding circuit. CONSTITUTION:The signals of (n) units of information sources are multiplexed to be turned into serial signals. These serial signals are supplied to a shift register 10 and a rise detecting circuit 11. At the same time, a clock is supplied to a register 10, and the binary signal of the input shifted by the clock is applied to the input terminal of the other side of the circuit 11 from the final stage. The signal of the final stage side of two inputs of the circuit 11 is delayed by (n) bits compared with an input signal. Thus it is possible to compare the present input signal with the n-bit earlier input signal. Then it is detected that the input signal changes from 0 to 1 when the n-bit earlier signal and the present signal are set at 0 and 1 respectively. The output signal of the circuit 11 is held by a holding circuit 12. Thus the circuit scale is reduced when a large number of bits exist.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention outputs 1 when even one of n binary signals becomes 1, and after forcing the output to 0 with another clear signal, outputs another 2-value signal. value signal becomes 1 or same 2
The standby circuit that outputs 1 when the value signal becomes 0 and then becomes 1 again is related to the circuit.

An example of a conventional standby circuit is shown in FIG. That is,
The input binary signal a is a serial signal obtained by multiplexing signals from n information sources (n = 4 in this circuit example), and is input to the D terminal of the flip-flop 1.2.3.4. . Scan pulse corresponding to each bit of input by e+
d+8 is the CK of each flip-flop 1.2.3.4
Each bit of the binary signal a input to the terminal is read at the rising edge of each scan pulse. The input 6th bit signal h is output to the bit signal QK of the flip-flop 4, and the input 4th bit signal i is output to the Q of the flip-flop 4. The f signal is connected to the CK terminal of flip-flop 5, and the g
The signal is input to the CK terminal of Flip-Flora and Pro, the h signal is input to the CK terminal of flip-flop 7, and the i signal is input to the CK terminal of flip-flop 8.
At the rising edge of the signal, 1 is input to the D terminal of flip-flop 5.6.7.8, and
．． 7.8, the L gL h+ 1 signal is held when 1 + m+ n is 1. k + I
The J m,n signals are input to the OR gate 9 and a 0 signal is output. Also, the clear signal j is sent to the flip-flop 5.
6. Input to the CLR terminal of 7.8, 1. The m and n signals become 0.

The signal shown in FIG. 2a is input to this circuit. 1st
In frames, the first to fourth bits are 0, the first bit is 1 in the second, third, and fourth frames, and the first and second bits are 1 in the fifth, sixth, and seventh frames. This input signal is scanned by scanning pulses b and c.

When read with d+e, the Q output signal f of the flip-flop 1 becomes 1 at the first bit of the second frame and remains 1 thereafter. Output signal g from the Q terminal of flip-flop 2
is 1 in the second bit of the fifth frame, so it remains 1. The output signal from the Q terminal of the flip-flop 70 tube 3 and the signal i from the Q terminal of the flip-flop 4 remain at 0. Output signal k from the Q terminal of flip-flop 5
The signal becomes 1 when the trif signal rises, and the 0 signal becomes 1 after passing through the OR gate 19. Next, when the clear signal j becomes 0, the output signal from the Q terminal of the flip-flop 5 becomes 0, and the output signal of the OR gate becomes 0.

Next, when the output signal g from the Q terminal of the flip-flop 6 rises, it becomes 1, and the output signal of the OR gate becomes 1 again, and becomes 0 due to the clear signal j.

As described above, in conventional circuits, a serial signal (n = 4 in the circuit example), which is a multiplexed signal of n information sources, is decomposed into parallel signals for each information source, and each is held. Two flip-flops are required for each information source, and an OR gate with n inputs is required to combine each held output into one, and the circuit scale increases in proportion to the number of n. There were drawbacks.

The present invention solves the above problems, and includes an n-stage shift register that shifts a serial signal obtained by multiplexing signals from n information sources using a clock pulse, and an input signal of the shift register and a final stage output signal. A rising edge detection circuit that takes as input and outputs 1 only when the final stage output signal is O and the input signal is 1, and an output signal and clear signal of the rising edge detection circuit that takes the output signal of the rising edge detection circuit as input and outputs according to the output signal of the rising edge detection circuit. 1, and a holding circuit whose output is set to O in response to a clear signal.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 6, in the present invention, a serial signal obtained by multiplexing signals from n information sources is input to a shift register 10 and a rising edge detection circuit 11. Also, shift register 10
A clock is input to , and the input binary signal shifted by the clock is output from the final stage of the shift register 10 and input to another input terminal of the rising edge detection circuit 11 . Of the two inputs of the rising edge detection circuit 11, the signal at the final stage of the shift register 10 has a phase delay of n bits compared to the signal at the input side of the shift register 100, so that the current input signal and the input signal n bits before are different. If the signal inputted at the same time and n bits before is 0 and the current signal is 1, that is, a bit in which the input signal changes from 0 to 1 is detected and output. The output signal of the rising edge detection circuit 11 is input to the holding circuit 12, and when the output of the rising edge detection circuit 11 becomes 1, it becomes 1.
The output becomes 0 only by adding a clear signal from the outside.

Next, an example of a circuit according to the present invention is shown in FIG.

FIG. 4 shows an example of a standby circuit that receives as input a serial signal in which signals from eight information sources are multiplexed.

The input serial signal P is input to the D terminal of the 8-stage shift register 13 and the AND gate 15.

In the 8-stage shift register 15, the input signal is shifted one pit at a time by the clock pulse, and the QH output of the 8-stage shift register 13 outputs a signal whose phase is delayed by 8 bits compared to the input signal, the serial signal P. 1
4 to the other input terminal of the AND gate 15. The AND gate 15 takes out a signal that has changed from 0 to 1 based on the signals at the two input terminals, that is, the current signal and the signal 8 bits earlier. This signal is input to the D terminal of the D-type flip-flop 16, reread by the clock, and input to the C- terminal of the D-type flip-flop 17.

1 is supplied to the D terminal of the D-type flip 70 knob 17, and C
At the rising edge of the signal at the K terminal, 1 is read at the D terminal and 1 is output to the Q terminal of the flip-flop 17. If 0 is supplied as a clear signal to the CLR terminal of the D-type flip-flop 1, Q becomes 0.

This kind of standby is performed in the circuit by the serial signal P shown in FIG. Enter. In the first frame, all 8 bits are 0, and the initial state of the shift register is still 0.
Therefore, all 8 bits of the QH output are 0, and the output r of the inverter 14 is 1. The output S of the AND gate 15 which receives the serial signal P and the output r of the inverter 14 becomes 0, and the flip-flop 1
/1 and 17 are trenches in the initial state. In the second frame, the first bit is 0, which is the same as the first frame, but the second bit is 1, and the r signal at this time is 1. Therefore, the AND gate 15 output S becomes 1. This signal is reread by the flip-flop 16. The flip-flop 17 reads 1 at the D terminal by the t signal, and the Q output becomes 1. Next, the sixth bit is 0, and since the r signal at this time is 1, the output S of the AND gate 15 becomes 0, and the Q output of the flip-flop 17 remains 1.

The same goes for the next 4th to 8th bits. Next, the sixth
The second bit of the frame is 1, but the QH of the shift register 13 to which the 8-bit previous signal is output is 1, and the output r of the inverter 14 is 0, so the output of the AND gate 15 is S is 0. Next, when the clear signal input to the CLR terminal of the flip-flop 17 is temporarily set to 0, the output signal V becomes 0. In the fourth frame, the second and fifth bits are 1. The second bit is set to flip-flop 1 by the same operation as in the 6th frame.
The 6th CK signal remains 0, but the 5th bit is the 3rd bit.
Since the fifth bit of the frame was 0, inverter 1
The output r of 4 is 1, and the output S of AND gate 15
is 1. Therefore, the CK signal of the flip-flop 17 becomes 1, and Q becomes 1 again.

As described above, the standby circuit of the present invention uses an n-stage shift register to divide the current n-bit signal into From 0 to 1 by sequentially comparing previous signals
Since the signal that changes to is detected and held in one holding circuit, even if the number of input signal bits increases, it can be handled by simply increasing the number of shift register stages, and the larger the number of bits, the smaller the circuit scale. It is effective.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional standby circuit;
3 is a block diagram showing an embodiment of the present invention, FIG. 4 is a circuit diagram showing an example of a circuit according to the present invention, and FIG. 5 is a time chart of a conventional standby circuit. 2 is a time chart of a circuit according to the present invention. 1 to 8-I) type flip-flop 9-11 or game) 10--Shift register 11-m-Rise detection circuit 12--Holding circuit 13
--- 8-stage shift register 14 --- Inverter 15 --- AND gate i6, IL-D type flip-flop patent 6"A
8$1 Ki Co., Ltd.:, Agent Patent Attorney Kanno -1 Ryofurei 2 Diagram 0

Claims (1)

[Claims] (IJ The input is a serial signal obtained by multiplexing the signals of n information sources, and the n-stage shift register is shifted by a long lock pulse, and the input signal of the shift register and the final stage output signal are input, and the final stage output a rising edge detection circuit that outputs 1 only when the signal is 0 and the input signal is 1; an output signal and a clear signal of the rising edge detection circuit are input; the output signal is set to 1 by the output signal of the rising edge detection circuit;
A standby circuit is characterized in that it comprises a holding circuit that sets the output to 0 in response to a clear signal.