JPH0424899A - Alarm monitor circuit - Google Patents

Abstract

PURPOSE:To curtail the number of the components of an alarm monitor circuit by delaying an alarm signal by a shift register, and generating an alarm reset signal by using its intermediate tap output. CONSTITUTION:The shift register 3 delays an inputted alarm state signal by using a monitoring clock, and outputs it successively to plural intermediate taps. Then, a flip flop 6 outputs an alarm decision signal based on the output from a last step among the intermediate taps of the shift register 3 and the alarm state signal of flip-flop output. Besides, an OR gate 5 generates the reset signal for an alarm signal sending source one time, at least, by using the intermediate tap output of the shift register 3, and sends it. Thus, the number of parts as the alarm monitor circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an alarm monitoring circuit, and more particularly, the present invention relates to an alarm monitoring circuit that sends at least one reset signal to an alarm signal sending source when an alarm signal is detected, and then determines the alarm state. The present invention relates to an alarm monitoring circuit that performs.

[Conventional technology]

Conventionally, this type of alarm monitoring circuit starts a timer when it receives an alarm signal, generates and outputs a reset signal one or more times, and stops generating the reset signal when the timer reaches the J fixed value. The alarm judgment signal base was output from the alarm signal.

[Problem to be solved by the invention]

The conventional alarm monitoring circuit described above has the disadvantage that the timing circuit and the reset signal generation circuit are independent, and the alarm monitoring circuit has a large number of components.

[Means to solve the problem]

The alarm monitoring circuit of the present invention includes a monitoring clock generating means for generating timing for alarm monitoring, a flip-flop for outputting an inputted alarm signal as an alarm state signal using an external clock, and the inputted alarm state. a shift register that sequentially delays and outputs a signal to a plurality of intermediate taps using the monitoring tarlock;
alarm determination signal output means for outputting an alarm determination signal based on the output from the final stage of the intermediate taps of the shift register and the alarm state signal of the flip-flop output; alarm signal transmission source reset means for generating and transmitting a reset signal for the alarm signal transmission source at least once; and a shift register for clearing the shift register when the alarm state signal output from the flip-flop is in a recovery state. The monitoring clock generating means may be an inverter that inverts the external clock.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In the first embodiment, the alarm input signal ALM is an alarm signal from an alarm signal source and is input to the data input terminal of the flip-flop 2. The clock input signal CLK is a clock pulse and is input to the clock input terminal CK of the flip-flop 2 and the inverter 7, and the inverter 7 outputs an inverted clock signal CLK to the tarlock input terminal CK of the shift register 3. flip flop 2
from the output terminal Q of the AND gate 1 to the input terminal of the shift register 3. Flip flop 4. An alarm state signal S1 is output to each reset input terminal CLR of the flip-flop 6. AND gate 1 inputs alarm state signal s1 from flip 70 block 2 and output signal s4 from flip-flop 4, and outputs output signal S2 to serial data input terminal S of shift register 3. Output terminal Q of shift register 3. The output signal S3 is output to the clock input terminal CK of the flip-flop 4, and the output terminals Q, ~Q
J is connected to the input terminal of the OR gate 5, and the output terminal Qk
An output signal S5 is output from the clock input terminal CK of the flip-flop 6. The data input terminal of the flip-flop 4 is fixed at a high level H, and the inverting output terminal outputs an output signal S4 to the AND gate 1. The data input terminal of the flip-flop 6 is fixed at a high level H, and the output terminal Q outputs an alarm determination signal ALDT. Also, an alarm reset signal R8T is output from the output terminal of the OR gate 5. The flip-flop 2 prevents malfunctions due to noise in the alarm input signal ALM and resets the alarm monitoring circuit when the alarm is restored. And gate 1. Shift register 3. With flip-flop 2,
A high level signal H having a width of one clock is shifted by a shift register 3.

Next, the operation of the first embodiment will be explained with reference to FIG.

FIG. 3 is a timing chart of each signal in the first embodiment.

When the alarm signal sending source enters an alarm state and the alarm input signal ALM becomes high level H, the flip-flop 2 changes its output alarm state signal s1 from low level L to high level H in synchronization with the clock signal CLK. . Here, since the output signal s4 of the flip-flop 4 is at a high level H, the pressure signal S of the AND gate 1
2 becomes a high level H.

The shift register 3 sets the output signal S3 from the output terminal Qo to a high level H in synchronization with the inverted clock signal CLK. Then, the inverted output signal S4 of the flip-flop 4 becomes low level L, and the output signal S2 of the AND gate 1 becomes low level L.

The output signal S3 of the shift register 3 becomes a high level H of one clock width, and then becomes a low level L, and the shift register 3 sequentially shifts a high level H of one clock width to each tap in synchronization with the inverted clock signal CLK. At the output terminals Q+ to Q' and Qk of the shift register 3, a high level H of one clock width appears from the inner terminals Qo to i to j, respectively, with a clock delay.

Alarm reset signals R3T of one clock width each are output from the output terminal of the OR gate 5 with a delay of i to j clock widths. When the signal S5 becomes high level H after a clock delay from the output terminal Qo of the shift register 3, the alarm judgment signal AL is output from the output terminal Q of the flip-flop 6.
DT is output at high level H to notify alarm detection.

Although not shown, when the alarm state of the alarm signal transmission source is restored and the alarm input signal ALM becomes low level L, the alarm state signal S1 changes to the clock signal CL.
The output terminals Qo to Qk of the shift register 3 all become low level L in synchronization with K, the output signal S4 becomes high level H, and the alarm judgment signal AL
DT becomes low level L and notifies alarm recovery.

Next, FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

The alarm input signal ALM is an alarm signal from an alarm signal sending source and is input to the data input terminal of the flip-flop 8. The clock input signal CLK is a clock pulse and is input to the clock input terminal CK of the flip-flop 8 and the inverter 16, and the inverter 16 inputs the inverted clock signal CLK to the clock input terminal CK of the shift register 9.
Output. An alarm state signal S is sent from the output terminal Q of the flip-flop 8 to the reset terminal CLR of the shift register, the serial data input terminal SI, and the AND gate 15.
6 is output. An output signal S7 is output from the output terminal Q of the shift register 9 to the AND gate 11, an inverter 10 is connected to the output terminal Q, and an output signal S8 of the inverter 10 is output to the AND gate 11. AND gate 11 outputs output signal S9 to OR gate 14 based on output signal S7 and output signal Q8. Further, an output signal StO is outputted from the output terminal QJ2 of the shift register 9 to the AND gate 13, an inverter 12 is connected to the output terminals Q, 1, and an output signal Stt of the inverter 12 is outputted to the AND gate 13.

AND gate 13 outputs output signal S12 to OR gate 14 based on output signal SIO and output signal Sll.

OR gate 14 outputs alarm reset signal R8T based on output signals S9 and 81□. Output terminal Q of shift register 9. Output signal S1 from to AND gate 15
3 is output, and the AND gate 15 outputs the output signals S6 and 31.
3, an alarm determination signal ALDT is output.

The flip-flop 8 prevents malfunctions due to noise in the alarm input signal ALM and resets the alarm monitoring circuit when the alarm is restored.

Next, the operation of the second embodiment will be explained with reference to FIG. 4.

FIG. 4 is a timing chart of each signal in the second embodiment.

When the alarm signal sending source enters an alarm state and the alarm input signal ALM becomes a high level H, the flip-flop 8 changes its output alarm state signal S6 from a low level L to a high level H in synchronization with the clock signal CLK. . At this point, the reset of the shift register 9 is released.

In the shift register 9, the alarm state signal S6 (high level H) is sequentially shifted to each tap in synchronization with the inverted clock signal CLK. Output signal S of AND gate 11
9, a level signal H of (ji) clock width appears with a delay of i clocks, and p is output to the output signal S1□ of the AND gate 12.
A level signal H having a clock width of (m-fI) appears with a clock delay. The output signal RST of the OR gate 14 includes:
An OR output of output signals S9 and S12 appears. Sequentially,
The high level signal H is shifted, the output signal S13 of the shift register 9 becomes high level H, the output signal S6 of the flip-flop 8 becomes high level H, and the alarm judgment signal ALDT, which is the output of the AND gate 15, becomes high level H. The level becomes high and an alarm appearance is notified.

Although not shown, when the alarm state of the alarm signal sending edge is restored and the alarm input signal ALM becomes low level L, the alarm state signal S6 changes to the clock signal CL.
It becomes low level L in synchronization with K, and the shift register 9 enters the reset state, and the output terminal Q+ of the shift register 9
~Q, all become low level, and alarm judgment signal A
LDT becomes low level L and notifies alarm recovery.

〔Effect of the invention〕

As explained above, in the present invention, the alarm signal is delayed by the shift register and the intermediate tap output is used to create the alarm reset signal, so the number of components of the alarm monitoring circuit can be reduced. .

Also, by switching the taps of the shift register,
Reset timing, reset interval, reset signal length,
This has the effect that the number of resets can be easily changed.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 respectively show the first embodiment of the present invention. The circuit diagrams of the second embodiment, FIGS. 3 and 4, are the circuit diagrams of the first embodiment. The second example is a timing chart of each signal. 1.11.13.15...and gate, 2°4.6
．． 8...Flip-flop, 3,9...Shift register, 5.14...OR gate, 7.10°12.1
6...Inverter, ALDT...Alarm judgment signal, ALM...Alarm input signal, CLK...
Clock input signal, CLK...inverted clock signal,
...Alarm status signal.

Claims (1)

[Claims] 1. Generate alarm monitoring timing in an alarm monitoring circuit that sends at least one reset signal to the alarm signal sending source when an alarm signal is detected and then determines the alarm state. monitoring clock generation means; a flip-flop that outputs the inputted alarm signal as an alarm state signal using an external clock; and the inputted alarm state signal is sequentially sent to a plurality of intermediate taps using the monitoring clock. a shift register that outputs a delayed output; and an alarm determination signal output means that outputs an alarm determination signal based on the output from the final stage of the intermediate taps of the shift register and the alarm state signal of the flip-flop output; alarm signal transmission source reset means for generating and transmitting a reset signal for the alarm signal transmission source at least once using an intermediate tap output of the shift register; and the alarm status signal of the flip-flop output is in a recovery state. and shift register clearing means for clearing the shift register at certain times. 2. The alarm monitoring circuit according to claim 1, wherein the monitoring clock generation means is an inverter that inverts the external clock.