JPS54156499A - Alarm generator - Google Patents

Alarm generator

Info

Publication number
JPS54156499A
JPS54156499A JP6509078A JP6509078A JPS54156499A JP S54156499 A JPS54156499 A JP S54156499A JP 6509078 A JP6509078 A JP 6509078A JP 6509078 A JP6509078 A JP 6509078A JP S54156499 A JPS54156499 A JP S54156499A
Authority
JP
Japan
Prior art keywords
output
alarm
signal
shb
sha
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6509078A
Other languages
Japanese (ja)
Inventor
Koichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6509078A priority Critical patent/JPS54156499A/en
Publication of JPS54156499A publication Critical patent/JPS54156499A/en
Pending legal-status Critical Current

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Landscapes

  • Alarm Systems (AREA)

Abstract

PURPOSE: To develop alarm signal correctly with less number of components, by converting the parallel input of alarm signal into series output in time sharing manner, even with more or less longer processing time.
CONSTITUTION: The alarm signals a1 to an are set to the shift register SHA with the output signal S1 from the N+1 notation counter CON, and the content of the shift registers SHA and SHB is shifted right every generation of clock signal CL by one bit after that, and the output S2 of SHA is inputted to SHB from the upper rank bit. Further, the output S2 is 1 and the NOT output S3 of SHB is 1, then the output S5 of the AND gate 2 is 1, to set FF2 and to develop the alarm signal ALS. The presence of the output S2 is detected with the detection circuit DET with the output S1 after that, and if no output S2 is present, FF2 is reset with the next output S1 to stop the alarm, and if the output S2 is present, FF2 is not reset and the alarm is continued until the STOP signal is inputted.
COPYRIGHT: (C)1979,JPO&Japio
JP6509078A 1978-05-31 1978-05-31 Alarm generator Pending JPS54156499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6509078A JPS54156499A (en) 1978-05-31 1978-05-31 Alarm generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6509078A JPS54156499A (en) 1978-05-31 1978-05-31 Alarm generator

Publications (1)

Publication Number Publication Date
JPS54156499A true JPS54156499A (en) 1979-12-10

Family

ID=13276877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6509078A Pending JPS54156499A (en) 1978-05-31 1978-05-31 Alarm generator

Country Status (1)

Country Link
JP (1) JPS54156499A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424899A (en) * 1990-05-18 1992-01-28 Nec Corp Alarm monitor circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424899A (en) * 1990-05-18 1992-01-28 Nec Corp Alarm monitor circuit

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