JPS559281A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS559281A
JPS559281A JP8189878A JP8189878A JPS559281A JP S559281 A JPS559281 A JP S559281A JP 8189878 A JP8189878 A JP 8189878A JP 8189878 A JP8189878 A JP 8189878A JP S559281 A JPS559281 A JP S559281A
Authority
JP
Japan
Prior art keywords
circuit
input
input data
register
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8189878A
Other languages
Japanese (ja)
Inventor
Kazumi Mori
Gunshiro Takaku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8189878A priority Critical patent/JPS559281A/en
Publication of JPS559281A publication Critical patent/JPS559281A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase the processing ability for the entire system, by executing the input data selective processing with separate hardware circuit from the processing unit, and performing the processing of input data selected with the hardware circuit with the processing unit.
CONSTITUTION: The hardware circuit consisting of the register 1 inputting the input data, timing generation circuit 2 inputting the strobe signal, and register 1 and operation discrimination circuit 3, is provided, and the circuit 2 produces the timing pulses 1, 2 by taking the strobe signal confirming the input signal newly as the reference. Further, the input A newly incoming the pulse 1 and the preceding input latched at the register 1 are operated at the operation and discrimination circuit 3 for the absolute value of the difference, and the output of the circuit 3 is fed to FF5 taking the reset signal as input via the AND gate 4, the input data at arbitrary time point is compared with the input data latched before, and if a given condition is established between the both, fetch request is made and the data at that time is latched.
COPYRIGHT: (C)1980,JPO&Japio
JP8189878A 1978-07-07 1978-07-07 Data processing system Pending JPS559281A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8189878A JPS559281A (en) 1978-07-07 1978-07-07 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8189878A JPS559281A (en) 1978-07-07 1978-07-07 Data processing system

Publications (1)

Publication Number Publication Date
JPS559281A true JPS559281A (en) 1980-01-23

Family

ID=13759251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8189878A Pending JPS559281A (en) 1978-07-07 1978-07-07 Data processing system

Country Status (1)

Country Link
JP (1) JPS559281A (en)

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